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Fourth Round of Renesas ARM Based SoC DT Updates for v4.3
* Enable Clock Domain support of the Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks driver. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVyvxYAAoJENfPZGlqN0++T74P/Ri9gvMcOgGFZPIntCJX8D4j ymoJdxilpA6c590F6++Zr/hFMXURhXE0viAYebO8iOPKkCArTYTpZ+UWMA1zgfPT J6aPkcRwVAT4DoAWDe1M+YJ+134l9hT+a9x5frbDmG5hP1Asw3ysc5b71e4gQcpX TDl8c+MkBbdXAKBJALOQhTZZsqvO/Ke4IhoS8Ud0PEmREWO/H/PoJjabw2Fd2j4O FYMmqLa4D5zU4QPr8p6UfvXmqVBIlToGxYgTLZ8itsfqb3wR/KtyNbOCqlM3DJjz VtrifAK2Ok0JxaKCRFd5Z6J1walBSeqDfPN5f9gn1FTg+0yTpBLaOWp7pE4/CvWX A2A91tC3+vYpZ0dDNN3FRrYn59xp/6NxXJd9qzTXQMjm0vzS60WdFTSkXhDxqDBi gwXGns/W10JEanrN0H3udLZhmQhA1n6G9sMc6Z9BpeiJCp6dgH/WBPd7Ppqa4U0n kazgchOZiTYXYwBYmA97HiaXL3kZ5rsv56+zuTog5eTW+xdC2s+SkIoj/Irrqt3v BiCsKqpQxTUpJhRvMcYl3MdMOl+1qojAUWLt0fHIC6sbpjz1Qx7msIEuJNw/qUa/ dbvIZIXULmjXhBmWVZNU6pgI3XpIGkEe+KHoqfuQzys2vfyaEtJgNHAPhQ95Alax V/VdcS8VJCaz0RcchKDA =e8Do -----END PGP SIGNATURE----- Merge tag 'renesas-dt4-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Fourth Round of Renesas ARM Based SoC DT Updates for v4.3 * Enable Clock Domain support of the Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks driver. * tag 'renesas-dt4-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain clk: shmobile: rz: Add CPG/MSTP Clock Domain support clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support clk: shmobile: Add CPG/MSTP Clock Domain support Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
582271a3d0
@ -1,7 +1,9 @@
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* Renesas R8A7778 Clock Pulse Generator (CPG)
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The CPG generates core clocks for the R8A7778. It includes two PLLs and
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several fixed ratio dividers
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several fixed ratio dividers.
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The CPG also provides a Clock Domain for SoC devices, in combination with the
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CPG Module Stop (MSTP) Clocks.
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Required Properties:
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@ -10,10 +12,18 @@ Required Properties:
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- #clock-cells: Must be 1
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- clock-output-names: The names of the clocks. Supported clocks are
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"plla", "pllb", "b", "out", "p", "s", and "s1".
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- #power-domain-cells: Must be 0
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SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
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through an MSTP clock should refer to the CPG device node in their
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"power-domains" property, as documented by the generic PM domain bindings in
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Documentation/devicetree/bindings/power/power_domain.txt.
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Example
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-------
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Examples
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--------
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- CPG device node:
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cpg_clocks: cpg_clocks@ffc80000 {
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compatible = "renesas,r8a7778-cpg-clocks";
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@ -22,4 +32,17 @@ Example
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clocks = <&extal_clk>;
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clock-output-names = "plla", "pllb", "b",
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"out", "p", "s", "s1";
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#power-domain-cells = <0>;
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};
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- CPG/MSTP Clock Domain member device node:
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sdhi0: sd@ffe4c000 {
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compatible = "renesas,sdhi-r8a7778";
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reg = <0xffe4c000 0x100>;
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interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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@ -1,7 +1,9 @@
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* Renesas R8A7779 Clock Pulse Generator (CPG)
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The CPG generates core clocks for the R8A7779. It includes one PLL and
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several fixed ratio dividers
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several fixed ratio dividers.
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The CPG also provides a Clock Domain for SoC devices, in combination with the
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CPG Module Stop (MSTP) Clocks.
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Required Properties:
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@ -12,16 +14,36 @@ Required Properties:
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- #clock-cells: Must be 1
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- clock-output-names: The names of the clocks. Supported clocks are "plla",
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"z", "zs", "s", "s1", "p", "b", "out".
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- #power-domain-cells: Must be 0
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SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
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through an MSTP clock should refer to the CPG device node in their
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"power-domains" property, as documented by the generic PM domain bindings in
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Documentation/devicetree/bindings/power/power_domain.txt.
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Example
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-------
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Examples
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--------
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- CPG device node:
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cpg_clocks: cpg_clocks@ffc80000 {
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compatible = "renesas,r8a7779-cpg-clocks";
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reg = <0 0xffc80000 0 0x30>;
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reg = <0xffc80000 0x30>;
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clocks = <&extal_clk>;
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#clock-cells = <1>;
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clock-output-names = "plla", "z", "zs", "s", "s1", "p",
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"b", "out";
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#power-domain-cells = <0>;
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};
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- CPG/MSTP Clock Domain member device node:
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sata: sata@fc600000 {
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compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
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reg = <0xfc600000 0x2000>;
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interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7779_CLK_SATA>;
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power-domains = <&cpg_clocks>;
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};
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@ -2,6 +2,8 @@
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The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
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and several fixed ratio dividers.
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The CPG also provides a Clock Domain for SoC devices, in combination with the
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CPG Module Stop (MSTP) Clocks.
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Required Properties:
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@ -20,10 +22,18 @@ Required Properties:
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- clock-output-names: The names of the clocks. Supported clocks are "main",
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"pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
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"adsp"
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- #power-domain-cells: Must be 0
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SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
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through an MSTP clock should refer to the CPG device node in their
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"power-domains" property, as documented by the generic PM domain bindings in
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Documentation/devicetree/bindings/power/power_domain.txt.
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Example
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-------
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Examples
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--------
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- CPG device node:
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,r8a7790-cpg-clocks",
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@ -34,4 +44,16 @@ Example
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clock-output-names = "main", "pll0, "pll1", "pll3",
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"lb", "qspi", "sdh", "sd0", "sd1", "z",
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"rcan", "adsp";
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#power-domain-cells = <0>;
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};
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- CPG/MSTP Clock Domain member device node:
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thermal@e61f0000 {
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compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
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reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
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interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
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power-domains = <&cpg_clocks>;
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};
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@ -2,6 +2,8 @@
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The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
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CPU and GPU clocks, and several fixed ratio dividers.
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The CPG also provides a Clock Domain for SoC devices, in combination with the
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CPG Module Stop (MSTP) Clocks.
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Required Properties:
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@ -14,10 +16,18 @@ Required Properties:
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- #clock-cells: Must be 1
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- clock-output-names: The names of the clocks. Supported clocks are "pll",
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"i", and "g"
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- #power-domain-cells: Must be 0
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SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
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through an MSTP clock should refer to the CPG device node in their
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"power-domains" property, as documented by the generic PM domain bindings in
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Documentation/devicetree/bindings/power/power_domain.txt.
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Example
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-------
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Examples
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--------
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- CPG device node:
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cpg_clocks: cpg_clocks@fcfe0000 {
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#clock-cells = <1>;
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@ -26,4 +36,19 @@ Example
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reg = <0xfcfe0000 0x18>;
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clocks = <&extal_clk>, <&usb_x1_clk>;
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clock-output-names = "pll", "i", "g";
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#power-domain-cells = <0>;
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};
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- CPG/MSTP Clock Domain member device node:
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mtu2: timer@fcff0000 {
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compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
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reg = <0xfcff0000 0x400>;
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interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tgi0a";
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clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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@ -86,6 +86,7 @@
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reg = <0xfcfe0000 0x18>;
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clocks = <&extal_clk>, <&usb_x1_clk>;
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clock-output-names = "pll", "i", "g";
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#power-domain-cells = <0>;
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};
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/* MSTP clocks */
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@ -157,6 +158,7 @@
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<0 189 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
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clock-names = "sci_ick";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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@ -169,6 +171,7 @@
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<0 193 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
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clock-names = "sci_ick";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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@ -181,6 +184,7 @@
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<0 197 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
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clock-names = "sci_ick";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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@ -193,6 +197,7 @@
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<0 201 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
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clock-names = "sci_ick";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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@ -205,6 +210,7 @@
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<0 205 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
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clock-names = "sci_ick";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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@ -217,6 +223,7 @@
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<0 209 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
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clock-names = "sci_ick";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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@ -229,6 +236,7 @@
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<0 213 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
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clock-names = "sci_ick";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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@ -241,6 +249,7 @@
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<0 217 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
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clock-names = "sci_ick";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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@ -252,6 +261,7 @@
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<0 240 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error", "rx", "tx";
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clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
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power-domains = <&cpg_clocks>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -266,6 +276,7 @@
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<0 243 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error", "rx", "tx";
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clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
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power-domains = <&cpg_clocks>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -280,6 +291,7 @@
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<0 246 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error", "rx", "tx";
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clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
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power-domains = <&cpg_clocks>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -294,6 +306,7 @@
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<0 249 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error", "rx", "tx";
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clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
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power-domains = <&cpg_clocks>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -308,6 +321,7 @@
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<0 252 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error", "rx", "tx";
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clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
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power-domains = <&cpg_clocks>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -338,6 +352,7 @@
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<0 164 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
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clock-frequency = <100000>;
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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@ -356,6 +371,7 @@
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<0 172 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
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clock-frequency = <100000>;
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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@ -374,6 +390,7 @@
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<0 180 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
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clock-frequency = <100000>;
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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@ -392,6 +409,7 @@
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<0 188 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
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clock-frequency = <100000>;
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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@ -402,6 +420,7 @@
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interrupt-names = "tgi0a";
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clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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};
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@ -53,6 +53,7 @@
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reg = <0xfde00000 0x400>;
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interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
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power-domains = <&cpg_clocks>;
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phy-mode = "rmii";
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#address-cells = <1>;
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#size-cells = <0>;
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@ -152,6 +153,7 @@
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reg = <0xffc70000 0x1000>;
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interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
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power-domains = <&cpg_clocks>;
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status = "disabled";
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||||
};
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@ -162,6 +164,7 @@
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reg = <0xffc71000 0x1000>;
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interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
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power-domains = <&cpg_clocks>;
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status = "disabled";
|
||||
};
|
||||
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||||
@ -172,6 +175,7 @@
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reg = <0xffc72000 0x1000>;
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interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
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power-domains = <&cpg_clocks>;
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status = "disabled";
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||||
};
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@ -182,6 +186,7 @@
|
||||
reg = <0xffc73000 0x1000>;
|
||||
interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -193,6 +198,7 @@
|
||||
<0 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
#renesas,channels = <3>;
|
||||
|
||||
@ -207,6 +213,7 @@
|
||||
<0 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
#renesas,channels = <3>;
|
||||
|
||||
@ -221,6 +228,7 @@
|
||||
<0 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
#renesas,channels = <3>;
|
||||
|
||||
@ -288,6 +296,7 @@
|
||||
interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
|
||||
clock-names = "sci_ick";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -297,6 +306,7 @@
|
||||
interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_SCIF1>;
|
||||
clock-names = "sci_ick";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -306,6 +316,7 @@
|
||||
interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_SCIF2>;
|
||||
clock-names = "sci_ick";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -315,6 +326,7 @@
|
||||
interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_SCIF3>;
|
||||
clock-names = "sci_ick";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -324,6 +336,7 @@
|
||||
interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_SCIF4>;
|
||||
clock-names = "sci_ick";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -333,6 +346,7 @@
|
||||
interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_SCIF5>;
|
||||
clock-names = "sci_ick";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -341,6 +355,7 @@
|
||||
reg = <0xffe4e000 0x100>;
|
||||
interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7778_CLK_MMC>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -349,6 +364,7 @@
|
||||
reg = <0xffe4c000 0x100>;
|
||||
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -357,6 +373,7 @@
|
||||
reg = <0xffe4d000 0x100>;
|
||||
interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -365,6 +382,7 @@
|
||||
reg = <0xffe4f000 0x100>;
|
||||
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -373,6 +391,7 @@
|
||||
reg = <0xfffc7000 0x18>;
|
||||
interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -383,6 +402,7 @@
|
||||
reg = <0xfffc8000 0x18>;
|
||||
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -393,6 +413,7 @@
|
||||
reg = <0xfffc6000 0x18>;
|
||||
interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -419,6 +440,7 @@
|
||||
clocks = <&extal_clk>;
|
||||
clock-output-names = "plla", "pllb", "b",
|
||||
"out", "p", "s", "s1";
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
/* Audio clocks; frequencies are set by boards if applicable. */
|
||||
|
||||
@ -173,6 +173,7 @@
|
||||
reg = <0xffc70000 0x1000>;
|
||||
interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -183,6 +184,7 @@
|
||||
reg = <0xffc71000 0x1000>;
|
||||
interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -193,6 +195,7 @@
|
||||
reg = <0xffc72000 0x1000>;
|
||||
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -203,6 +206,7 @@
|
||||
reg = <0xffc73000 0x1000>;
|
||||
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -212,6 +216,7 @@
|
||||
interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_SCIF0>;
|
||||
clock-names = "sci_ick";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -221,6 +226,7 @@
|
||||
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_SCIF1>;
|
||||
clock-names = "sci_ick";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -230,6 +236,7 @@
|
||||
interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_SCIF2>;
|
||||
clock-names = "sci_ick";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -239,6 +246,7 @@
|
||||
interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_SCIF3>;
|
||||
clock-names = "sci_ick";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -248,6 +256,7 @@
|
||||
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_SCIF4>;
|
||||
clock-names = "sci_ick";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -257,6 +266,7 @@
|
||||
interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_SCIF5>;
|
||||
clock-names = "sci_ick";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -278,6 +288,7 @@
|
||||
<0 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
#renesas,channels = <3>;
|
||||
|
||||
@ -292,6 +303,7 @@
|
||||
<0 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
#renesas,channels = <3>;
|
||||
|
||||
@ -306,6 +318,7 @@
|
||||
<0 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
#renesas,channels = <3>;
|
||||
|
||||
@ -317,6 +330,7 @@
|
||||
reg = <0xfc600000 0x2000>;
|
||||
interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7779_CLK_SATA>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
||||
sdhi0: sd@ffe4c000 {
|
||||
@ -324,6 +338,7 @@
|
||||
reg = <0xffe4c000 0x100>;
|
||||
interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -332,6 +347,7 @@
|
||||
reg = <0xffe4d000 0x100>;
|
||||
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -340,6 +356,7 @@
|
||||
reg = <0xffe4e000 0x100>;
|
||||
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -348,6 +365,7 @@
|
||||
reg = <0xffe4f000 0x100>;
|
||||
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -358,6 +376,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -368,6 +387,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -378,6 +398,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -386,6 +407,7 @@
|
||||
reg = <0 0xfff80000 0 0x40000>;
|
||||
interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7779_CLK_DU>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
@ -427,6 +449,7 @@
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "plla", "z", "zs", "s",
|
||||
"s1", "p", "b", "out";
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
/* Fixed factor clocks */
|
||||
|
||||
@ -134,6 +134,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
||||
gpio1: gpio@e6051000 {
|
||||
@ -146,6 +147,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
||||
gpio2: gpio@e6052000 {
|
||||
@ -158,6 +160,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
||||
gpio3: gpio@e6053000 {
|
||||
@ -170,6 +173,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
||||
gpio4: gpio@e6054000 {
|
||||
@ -182,6 +186,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
||||
gpio5: gpio@e6055000 {
|
||||
@ -194,6 +199,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
||||
thermal@e61f0000 {
|
||||
@ -201,6 +207,7 @@
|
||||
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
|
||||
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
||||
timer {
|
||||
@ -218,6 +225,7 @@
|
||||
<0 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
renesas,channels-mask = <0x60>;
|
||||
|
||||
@ -237,6 +245,7 @@
|
||||
<0 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
renesas,channels-mask = <0xff>;
|
||||
|
||||
@ -253,6 +262,7 @@
|
||||
<0 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
@ -281,6 +291,7 @@
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
@ -311,6 +322,7 @@
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
@ -339,6 +351,7 @@
|
||||
"ch12";
|
||||
clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <13>;
|
||||
};
|
||||
@ -367,6 +380,7 @@
|
||||
"ch12";
|
||||
clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <13>;
|
||||
};
|
||||
@ -378,6 +392,7 @@
|
||||
0 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
@ -389,6 +404,7 @@
|
||||
0 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
@ -400,6 +416,7 @@
|
||||
reg = <0 0xe6508000 0 0x40>;
|
||||
interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -410,6 +427,7 @@
|
||||
reg = <0 0xe6518000 0 0x40>;
|
||||
interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -420,6 +438,7 @@
|
||||
reg = <0 0xe6530000 0 0x40>;
|
||||
interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -430,6 +449,7 @@
|
||||
reg = <0 0xe6540000 0 0x40>;
|
||||
interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -442,6 +462,7 @@
|
||||
clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
|
||||
dmas = <&dmac0 0x61>, <&dmac0 0x62>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -454,6 +475,7 @@
|
||||
clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
|
||||
dmas = <&dmac0 0x65>, <&dmac0 0x66>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -466,6 +488,7 @@
|
||||
clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
|
||||
dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -478,6 +501,7 @@
|
||||
clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
|
||||
dmas = <&dmac0 0x77>, <&dmac0 0x78>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -488,6 +512,7 @@
|
||||
clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
|
||||
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
max-frequency = <97500000>;
|
||||
@ -500,6 +525,7 @@
|
||||
clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
|
||||
dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
max-frequency = <97500000>;
|
||||
@ -517,6 +543,7 @@
|
||||
clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
|
||||
dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -527,6 +554,7 @@
|
||||
clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
|
||||
dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -537,6 +565,7 @@
|
||||
clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
|
||||
dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -547,6 +576,7 @@
|
||||
clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
|
||||
dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -558,6 +588,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x21>, <&dmac0 0x22>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -569,6 +600,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x25>, <&dmac0 0x26>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -580,6 +612,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x27>, <&dmac0 0x28>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -591,6 +624,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -602,6 +636,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -613,6 +648,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -624,6 +660,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -635,6 +672,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -646,6 +684,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -657,6 +696,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -665,6 +705,7 @@
|
||||
reg = <0 0xee700000 0 0x400>;
|
||||
interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
phy-mode = "rmii";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -676,6 +717,7 @@
|
||||
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
|
||||
interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -686,6 +728,7 @@
|
||||
reg = <0 0xee300000 0 0x2000>;
|
||||
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -694,6 +737,7 @@
|
||||
reg = <0 0xee500000 0 0x2000>;
|
||||
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -702,12 +746,13 @@
|
||||
reg = <0 0xe6590000 0 0x100>;
|
||||
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
|
||||
renesas,buswait = <4>;
|
||||
phys = <&usb0 1>;
|
||||
phy-names = "usb";
|
||||
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
|
||||
<&usb_dmac1 0>, <&usb_dmac1 1>;
|
||||
dma-names = "ch0", "ch1", "ch2", "ch3";
|
||||
power-domains = <&cpg_clocks>;
|
||||
renesas,buswait = <4>;
|
||||
phys = <&usb0 1>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -718,6 +763,7 @@
|
||||
#size-cells = <0>;
|
||||
clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
|
||||
clock-names = "usbhs";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
|
||||
usb0: usb-channel@0 {
|
||||
@ -732,33 +778,37 @@
|
||||
|
||||
vin0: video@e6ef0000 {
|
||||
compatible = "renesas,vin-r8a7790";
|
||||
clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
|
||||
reg = <0 0xe6ef0000 0 0x1000>;
|
||||
interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin1: video@e6ef1000 {
|
||||
compatible = "renesas,vin-r8a7790";
|
||||
clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
|
||||
reg = <0 0xe6ef1000 0 0x1000>;
|
||||
interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin2: video@e6ef2000 {
|
||||
compatible = "renesas,vin-r8a7790";
|
||||
clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
|
||||
reg = <0 0xe6ef2000 0 0x1000>;
|
||||
interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin3: video@e6ef3000 {
|
||||
compatible = "renesas,vin-r8a7790";
|
||||
clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
|
||||
reg = <0 0xe6ef3000 0 0x1000>;
|
||||
interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -767,6 +817,7 @@
|
||||
reg = <0 0xfe920000 0 0x8000>;
|
||||
interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
renesas,has-sru;
|
||||
renesas,#rpf = <5>;
|
||||
@ -779,6 +830,7 @@
|
||||
reg = <0 0xfe928000 0 0x8000>;
|
||||
interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
renesas,has-lut;
|
||||
renesas,has-sru;
|
||||
@ -792,6 +844,7 @@
|
||||
reg = <0 0xfe930000 0 0x8000>;
|
||||
interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
renesas,has-lif;
|
||||
renesas,has-lut;
|
||||
@ -805,6 +858,7 @@
|
||||
reg = <0 0xfe938000 0 0x8000>;
|
||||
interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
renesas,has-lif;
|
||||
renesas,has-lut;
|
||||
@ -859,6 +913,7 @@
|
||||
clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
|
||||
<&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -869,6 +924,7 @@
|
||||
clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
|
||||
<&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -877,6 +933,7 @@
|
||||
reg = <0 0xfe980000 0 0x10300>;
|
||||
interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7790_CLK_JPU>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
@ -953,6 +1010,7 @@
|
||||
clock-output-names = "main", "pll0", "pll1", "pll3",
|
||||
"lb", "qspi", "sdh", "sd0", "sd1",
|
||||
"z", "rcan", "adsp";
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
/* Variable factor clocks */
|
||||
@ -1343,6 +1401,7 @@
|
||||
clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
|
||||
dmas = <&dmac0 0x17>, <&dmac0 0x18>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -1356,6 +1415,7 @@
|
||||
clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
|
||||
dmas = <&dmac0 0x51>, <&dmac0 0x52>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -1368,6 +1428,7 @@
|
||||
clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
|
||||
dmas = <&dmac0 0x55>, <&dmac0 0x56>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -1380,6 +1441,7 @@
|
||||
clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
|
||||
dmas = <&dmac0 0x41>, <&dmac0 0x42>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -1392,6 +1454,7 @@
|
||||
clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
|
||||
dmas = <&dmac0 0x45>, <&dmac0 0x46>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -1402,6 +1465,7 @@
|
||||
reg = <0 0xee000000 0 0xc00>;
|
||||
interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
phys = <&usb2 1>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
@ -1410,10 +1474,11 @@
|
||||
pci0: pci@ee090000 {
|
||||
compatible = "renesas,pci-r8a7790";
|
||||
device_type = "pci";
|
||||
clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
|
||||
reg = <0 0xee090000 0 0xc00>,
|
||||
<0 0xee080000 0 0x1100>;
|
||||
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
|
||||
bus-range = <0 0>;
|
||||
@ -1444,10 +1509,11 @@
|
||||
pci1: pci@ee0b0000 {
|
||||
compatible = "renesas,pci-r8a7790";
|
||||
device_type = "pci";
|
||||
clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
|
||||
reg = <0 0xee0b0000 0 0xc00>,
|
||||
<0 0xee0a0000 0 0x1100>;
|
||||
interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
|
||||
bus-range = <1 1>;
|
||||
@ -1465,6 +1531,7 @@
|
||||
compatible = "renesas,pci-r8a7790";
|
||||
device_type = "pci";
|
||||
clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
reg = <0 0xee0d0000 0 0xc00>,
|
||||
<0 0xee0c0000 0 0x1100>;
|
||||
interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@ -1517,6 +1584,7 @@
|
||||
interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
|
||||
clock-names = "pcie", "pcie_bus";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@ -91,6 +91,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
||||
gpio1: gpio@e6051000 {
|
||||
@ -103,6 +104,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
||||
gpio2: gpio@e6052000 {
|
||||
@ -115,6 +117,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
||||
gpio3: gpio@e6053000 {
|
||||
@ -127,6 +130,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
||||
gpio4: gpio@e6054000 {
|
||||
@ -139,6 +143,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
||||
gpio5: gpio@e6055000 {
|
||||
@ -151,6 +156,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
||||
gpio6: gpio@e6055400 {
|
||||
@ -163,6 +169,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
||||
gpio7: gpio@e6055800 {
|
||||
@ -175,6 +182,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
||||
thermal@e61f0000 {
|
||||
@ -182,6 +190,7 @@
|
||||
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
|
||||
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
||||
timer {
|
||||
@ -199,6 +208,7 @@
|
||||
<0 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
renesas,channels-mask = <0x60>;
|
||||
|
||||
@ -218,6 +228,7 @@
|
||||
<0 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
renesas,channels-mask = <0xff>;
|
||||
|
||||
@ -240,6 +251,7 @@
|
||||
<0 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
@ -268,6 +280,7 @@
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
@ -298,6 +311,7 @@
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
@ -326,6 +340,7 @@
|
||||
"ch12";
|
||||
clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <13>;
|
||||
};
|
||||
@ -354,6 +369,7 @@
|
||||
"ch12";
|
||||
clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <13>;
|
||||
};
|
||||
@ -365,6 +381,7 @@
|
||||
0 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
@ -376,6 +393,7 @@
|
||||
0 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
@ -388,6 +406,7 @@
|
||||
reg = <0 0xe6508000 0 0x40>;
|
||||
interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -398,6 +417,7 @@
|
||||
reg = <0 0xe6518000 0 0x40>;
|
||||
interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -408,6 +428,7 @@
|
||||
reg = <0 0xe6530000 0 0x40>;
|
||||
interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -418,6 +439,7 @@
|
||||
reg = <0 0xe6540000 0 0x40>;
|
||||
interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -428,6 +450,7 @@
|
||||
reg = <0 0xe6520000 0 0x40>;
|
||||
interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -439,6 +462,7 @@
|
||||
reg = <0 0xe6528000 0 0x40>;
|
||||
interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -452,6 +476,7 @@
|
||||
clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
|
||||
dmas = <&dmac0 0x77>, <&dmac0 0x78>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -464,6 +489,7 @@
|
||||
clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
|
||||
dmas = <&dmac0 0x61>, <&dmac0 0x62>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -476,6 +502,7 @@
|
||||
clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
|
||||
dmas = <&dmac0 0x65>, <&dmac0 0x66>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -492,6 +519,7 @@
|
||||
clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
|
||||
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
max-frequency = <97500000>;
|
||||
@ -504,6 +532,7 @@
|
||||
clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
|
||||
dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -514,6 +543,7 @@
|
||||
clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
|
||||
dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -524,6 +554,7 @@
|
||||
clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
|
||||
dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -535,6 +566,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x21>, <&dmac0 0x22>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -546,6 +578,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x25>, <&dmac0 0x26>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -557,6 +590,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x27>, <&dmac0 0x28>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -568,6 +602,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -579,6 +614,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -590,6 +626,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x23>, <&dmac0 0x24>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -601,6 +638,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -612,6 +650,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -623,6 +662,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -634,6 +674,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -645,6 +686,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -656,6 +698,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -667,6 +710,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -678,6 +722,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -689,6 +734,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -700,6 +746,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -711,6 +758,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -722,6 +770,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -730,6 +779,7 @@
|
||||
reg = <0 0xee700000 0 0x400>;
|
||||
interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
phy-mode = "rmii";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -741,6 +791,7 @@
|
||||
reg = <0 0xee300000 0 0x2000>;
|
||||
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -749,6 +800,7 @@
|
||||
reg = <0 0xee500000 0 0x2000>;
|
||||
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -757,12 +809,13 @@
|
||||
reg = <0 0xe6590000 0 0x100>;
|
||||
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
|
||||
renesas,buswait = <4>;
|
||||
phys = <&usb0 1>;
|
||||
phy-names = "usb";
|
||||
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
|
||||
<&usb_dmac1 0>, <&usb_dmac1 1>;
|
||||
dma-names = "ch0", "ch1", "ch2", "ch3";
|
||||
power-domains = <&cpg_clocks>;
|
||||
renesas,buswait = <4>;
|
||||
phys = <&usb0 1>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -773,6 +826,7 @@
|
||||
#size-cells = <0>;
|
||||
clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
|
||||
clock-names = "usbhs";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
|
||||
usb0: usb-channel@0 {
|
||||
@ -787,25 +841,28 @@
|
||||
|
||||
vin0: video@e6ef0000 {
|
||||
compatible = "renesas,vin-r8a7791";
|
||||
clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
|
||||
reg = <0 0xe6ef0000 0 0x1000>;
|
||||
interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin1: video@e6ef1000 {
|
||||
compatible = "renesas,vin-r8a7791";
|
||||
clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
|
||||
reg = <0 0xe6ef1000 0 0x1000>;
|
||||
interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin2: video@e6ef2000 {
|
||||
compatible = "renesas,vin-r8a7791";
|
||||
clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
|
||||
reg = <0 0xe6ef2000 0 0x1000>;
|
||||
interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -814,6 +871,7 @@
|
||||
reg = <0 0xfe928000 0 0x8000>;
|
||||
interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
renesas,has-lut;
|
||||
renesas,has-sru;
|
||||
@ -827,6 +885,7 @@
|
||||
reg = <0 0xfe930000 0 0x8000>;
|
||||
interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
renesas,has-lif;
|
||||
renesas,has-lut;
|
||||
@ -840,6 +899,7 @@
|
||||
reg = <0 0xfe938000 0 0x8000>;
|
||||
interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
renesas,has-lif;
|
||||
renesas,has-lut;
|
||||
@ -885,6 +945,7 @@
|
||||
clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
|
||||
<&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -895,6 +956,7 @@
|
||||
clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
|
||||
<&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -903,6 +965,7 @@
|
||||
reg = <0 0xfe980000 0 0x10300>;
|
||||
interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7791_CLK_JPU>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
@ -979,6 +1042,7 @@
|
||||
clock-output-names = "main", "pll0", "pll1", "pll3",
|
||||
"lb", "qspi", "sdh", "sd0", "z",
|
||||
"rcan", "adsp";
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
/* Variable factor clocks */
|
||||
@ -1361,6 +1425,7 @@
|
||||
clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
|
||||
dmas = <&dmac0 0x17>, <&dmac0 0x18>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -1374,6 +1439,7 @@
|
||||
clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
|
||||
dmas = <&dmac0 0x51>, <&dmac0 0x52>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -1386,6 +1452,7 @@
|
||||
clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
|
||||
dmas = <&dmac0 0x55>, <&dmac0 0x56>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -1398,6 +1465,7 @@
|
||||
clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
|
||||
dmas = <&dmac0 0x41>, <&dmac0 0x42>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@ -1408,6 +1476,7 @@
|
||||
reg = <0 0xee000000 0 0xc00>;
|
||||
interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
phys = <&usb2 1>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
@ -1416,10 +1485,11 @@
|
||||
pci0: pci@ee090000 {
|
||||
compatible = "renesas,pci-r8a7791";
|
||||
device_type = "pci";
|
||||
clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
|
||||
reg = <0 0xee090000 0 0xc00>,
|
||||
<0 0xee080000 0 0x1100>;
|
||||
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
|
||||
bus-range = <0 0>;
|
||||
@ -1450,10 +1520,11 @@
|
||||
pci1: pci@ee0d0000 {
|
||||
compatible = "renesas,pci-r8a7791";
|
||||
device_type = "pci";
|
||||
clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
|
||||
reg = <0 0xee0d0000 0 0xc00>,
|
||||
<0 0xee0c0000 0 0x1100>;
|
||||
interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
|
||||
bus-range = <1 1>;
|
||||
@ -1503,6 +1574,7 @@
|
||||
interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
|
||||
clock-names = "pcie", "pcie_bus";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@ -68,6 +68,7 @@
|
||||
<0 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
renesas,channels-mask = <0x60>;
|
||||
|
||||
@ -87,6 +88,7 @@
|
||||
<0 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
renesas,channels-mask = <0xff>;
|
||||
|
||||
@ -109,6 +111,7 @@
|
||||
<0 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
||||
scif0: serial@e6e60000 {
|
||||
@ -117,6 +120,7 @@
|
||||
interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7793_CLK_SCIF0>;
|
||||
clock-names = "sci_ick";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -126,6 +130,7 @@
|
||||
interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R8A7793_CLK_SCIF1>;
|
||||
clock-names = "sci_ick";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -134,6 +139,7 @@
|
||||
reg = <0 0xee700000 0 0x400>;
|
||||
interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
phy-mode = "rmii";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -164,6 +170,7 @@
|
||||
clock-output-names = "main", "pll0", "pll1", "pll3",
|
||||
"lb", "qspi", "sdh", "sd0", "z",
|
||||
"rcan", "adsp";
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
/* Variable factor clocks */
|
||||
|
||||
@ -57,6 +57,7 @@
|
||||
<0 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
renesas,channels-mask = <0x60>;
|
||||
|
||||
@ -76,6 +77,7 @@
|
||||
<0 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
|
||||
renesas,channels-mask = <0xff>;
|
||||
|
||||
@ -106,6 +108,7 @@
|
||||
<0 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
@ -140,6 +143,7 @@
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
@ -170,6 +174,7 @@
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
@ -182,6 +187,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x21>, <&dmac0 0x22>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -193,6 +199,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x25>, <&dmac0 0x26>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -204,6 +211,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x27>, <&dmac0 0x28>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -215,6 +223,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -226,6 +235,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -237,6 +247,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x23>, <&dmac0 0x24>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -248,6 +259,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -259,6 +271,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -270,6 +283,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -281,6 +295,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -292,6 +307,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -303,6 +319,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -314,6 +331,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -325,6 +343,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -336,6 +355,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -347,6 +367,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -358,6 +379,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -369,6 +391,7 @@
|
||||
clock-names = "sci_ick";
|
||||
dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -377,6 +400,7 @@
|
||||
reg = <0 0xee700000 0 0x400>;
|
||||
interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
phy-mode = "rmii";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -390,6 +414,7 @@
|
||||
clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
|
||||
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -399,6 +424,7 @@
|
||||
reg = <0 0xee100000 0 0x200>;
|
||||
interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -407,6 +433,7 @@
|
||||
reg = <0 0xee140000 0 0x100>;
|
||||
interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -415,6 +442,7 @@
|
||||
reg = <0 0xee160000 0 0x100>;
|
||||
interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -441,6 +469,7 @@
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "main", "pll0", "pll1", "pll3",
|
||||
"lb", "qspi", "sdh", "sd0", "z";
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
/* Variable factor clocks */
|
||||
sd2_clk: sd2_clk@e6150078 {
|
||||
|
||||
@ -4,6 +4,7 @@ config ARCH_SHMOBILE
|
||||
|
||||
config PM_RCAR
|
||||
bool
|
||||
select PM_GENERIC_DOMAINS if PM
|
||||
|
||||
config PM_RMOBILE
|
||||
bool
|
||||
@ -50,6 +51,7 @@ config ARCH_EMEV2
|
||||
|
||||
config ARCH_R7S72100
|
||||
bool "RZ/A1H (R7S72100)"
|
||||
select PM_GENERIC_DOMAINS if PM
|
||||
select SYS_SUPPORTS_SH_MTU2
|
||||
|
||||
config ARCH_R8A73A4
|
||||
|
||||
@ -2,6 +2,7 @@
|
||||
* R-Car MSTP clocks
|
||||
*
|
||||
* Copyright (C) 2013 Ideas On Board SPRL
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
*
|
||||
* Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
|
||||
*
|
||||
@ -10,11 +11,16 @@
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk/shmobile.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/pm_clock.h>
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
/*
|
||||
@ -236,3 +242,84 @@ static void __init cpg_mstp_clocks_init(struct device_node *np)
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);
|
||||
}
|
||||
CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
|
||||
|
||||
|
||||
#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
|
||||
int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
|
||||
{
|
||||
struct device_node *np = dev->of_node;
|
||||
struct of_phandle_args clkspec;
|
||||
struct clk *clk;
|
||||
int i = 0;
|
||||
int error;
|
||||
|
||||
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
|
||||
&clkspec)) {
|
||||
if (of_device_is_compatible(clkspec.np,
|
||||
"renesas,cpg-mstp-clocks"))
|
||||
goto found;
|
||||
|
||||
of_node_put(clkspec.np);
|
||||
i++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
found:
|
||||
clk = of_clk_get_from_provider(&clkspec);
|
||||
of_node_put(clkspec.np);
|
||||
|
||||
if (IS_ERR(clk))
|
||||
return PTR_ERR(clk);
|
||||
|
||||
error = pm_clk_create(dev);
|
||||
if (error) {
|
||||
dev_err(dev, "pm_clk_create failed %d\n", error);
|
||||
goto fail_put;
|
||||
}
|
||||
|
||||
error = pm_clk_add_clk(dev, clk);
|
||||
if (error) {
|
||||
dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
|
||||
goto fail_destroy;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
fail_destroy:
|
||||
pm_clk_destroy(dev);
|
||||
fail_put:
|
||||
clk_put(clk);
|
||||
return error;
|
||||
}
|
||||
|
||||
void cpg_mstp_detach_dev(struct generic_pm_domain *domain, struct device *dev)
|
||||
{
|
||||
if (!list_empty(&dev->power.subsys_data->clock_list))
|
||||
pm_clk_destroy(dev);
|
||||
}
|
||||
|
||||
void __init cpg_mstp_add_clk_domain(struct device_node *np)
|
||||
{
|
||||
struct generic_pm_domain *pd;
|
||||
u32 ncells;
|
||||
|
||||
if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
|
||||
pr_warn("%s lacks #power-domain-cells\n", np->full_name);
|
||||
return;
|
||||
}
|
||||
|
||||
pd = kzalloc(sizeof(*pd), GFP_KERNEL);
|
||||
if (!pd)
|
||||
return;
|
||||
|
||||
pd->name = np->name;
|
||||
|
||||
pd->flags = GENPD_FLAG_PM_CLK;
|
||||
pm_genpd_init(pd, &simple_qos_governor, false);
|
||||
pd->attach_dev = cpg_mstp_attach_dev;
|
||||
pd->detach_dev = cpg_mstp_detach_dev;
|
||||
|
||||
of_genpd_add_provider_simple(np, pd);
|
||||
}
|
||||
#endif /* !CONFIG_PM_GENERIC_DOMAINS_OF */
|
||||
|
||||
@ -124,6 +124,8 @@ static void __init r8a7778_cpg_clocks_init(struct device_node *np)
|
||||
}
|
||||
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
|
||||
|
||||
cpg_mstp_add_clk_domain(np);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(r8a7778_cpg_clks, "renesas,r8a7778-cpg-clocks",
|
||||
|
||||
@ -168,6 +168,8 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np)
|
||||
}
|
||||
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
|
||||
|
||||
cpg_mstp_add_clk_domain(np);
|
||||
}
|
||||
CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
|
||||
r8a7779_cpg_clocks_init);
|
||||
|
||||
@ -415,6 +415,8 @@ static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
|
||||
}
|
||||
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
|
||||
|
||||
cpg_mstp_add_clk_domain(np);
|
||||
}
|
||||
CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks",
|
||||
rcar_gen2_cpg_clocks_init);
|
||||
|
||||
@ -10,6 +10,7 @@
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clk/shmobile.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of.h>
|
||||
@ -99,5 +100,7 @@ static void __init rz_cpg_clocks_init(struct device_node *np)
|
||||
}
|
||||
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
|
||||
|
||||
cpg_mstp_add_clk_domain(np);
|
||||
}
|
||||
CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);
|
||||
|
||||
@ -16,8 +16,20 @@
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct device;
|
||||
struct device_node;
|
||||
struct generic_pm_domain;
|
||||
|
||||
void r8a7778_clocks_init(u32 mode);
|
||||
void r8a7779_clocks_init(u32 mode);
|
||||
void rcar_gen2_clocks_init(u32 mode);
|
||||
|
||||
#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
|
||||
void cpg_mstp_add_clk_domain(struct device_node *np);
|
||||
int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev);
|
||||
void cpg_mstp_detach_dev(struct generic_pm_domain *domain, struct device *dev);
|
||||
#else
|
||||
static inline void cpg_mstp_add_clk_domain(struct device_node *np) {}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user