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drm/tegra: Add new UAPI to header
Update the tegra_drm.h UAPI header, adding the new proposed UAPI. The old staging UAPI is left in for now, with minor modification to avoid name collisions. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Mikko Perttunen
Thierry Reding
parent
f51632cc0e
commit
57e203953d
@ -1,24 +1,5 @@
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/*
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* Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/* SPDX-License-Identifier: MIT */
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/* Copyright (c) 2012-2020 NVIDIA Corporation */
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#ifndef _UAPI_TEGRA_DRM_H_
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#define _UAPI_TEGRA_DRM_H_
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@ -29,6 +10,8 @@
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extern "C" {
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#endif
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/* Tegra DRM legacy UAPI. Only enabled with STAGING */
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#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)
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#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
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@ -649,8 +632,8 @@ struct drm_tegra_gem_get_flags {
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#define DRM_TEGRA_SYNCPT_READ 0x02
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#define DRM_TEGRA_SYNCPT_INCR 0x03
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#define DRM_TEGRA_SYNCPT_WAIT 0x04
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#define DRM_TEGRA_OPEN_CHANNEL 0x05
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#define DRM_TEGRA_CLOSE_CHANNEL 0x06
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#define DRM_TEGRA_OPEN_CHANNEL 0x05
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#define DRM_TEGRA_CLOSE_CHANNEL 0x06
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#define DRM_TEGRA_GET_SYNCPT 0x07
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#define DRM_TEGRA_SUBMIT 0x08
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#define DRM_TEGRA_GET_SYNCPT_BASE 0x09
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@ -674,6 +657,402 @@ struct drm_tegra_gem_get_flags {
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#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
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#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
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/* New Tegra DRM UAPI */
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/*
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* Reported by the driver in the `capabilities` field.
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*
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* DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT: If set, the engine is cache coherent
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* with regard to the system memory.
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*/
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#define DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT (1 << 0)
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struct drm_tegra_channel_open {
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/**
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* @host1x_class: [in]
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*
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* Host1x class of the engine that will be programmed using this
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* channel.
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*/
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__u32 host1x_class;
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/**
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* @flags: [in]
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*
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* Flags.
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*/
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__u32 flags;
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/**
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* @context: [out]
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*
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* Opaque identifier corresponding to the opened channel.
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*/
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__u32 context;
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/**
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* @version: [out]
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*
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* Version of the engine hardware. This can be used by userspace
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* to determine how the engine needs to be programmed.
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*/
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__u32 version;
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/**
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* @capabilities: [out]
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*
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* Flags describing the hardware capabilities.
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*/
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__u32 capabilities;
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__u32 padding;
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};
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struct drm_tegra_channel_close {
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/**
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* @context: [in]
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*
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* Identifier of the channel to close.
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*/
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__u32 context;
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__u32 padding;
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};
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/*
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* Mapping flags that can be used to influence how the mapping is created.
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*
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* DRM_TEGRA_CHANNEL_MAP_READ: create mapping that allows HW read access
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* DRM_TEGRA_CHANNEL_MAP_WRITE: create mapping that allows HW write access
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*/
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#define DRM_TEGRA_CHANNEL_MAP_READ (1 << 0)
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#define DRM_TEGRA_CHANNEL_MAP_WRITE (1 << 1)
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#define DRM_TEGRA_CHANNEL_MAP_READ_WRITE (DRM_TEGRA_CHANNEL_MAP_READ | \
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DRM_TEGRA_CHANNEL_MAP_WRITE)
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struct drm_tegra_channel_map {
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/**
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* @context: [in]
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*
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* Identifier of the channel to which make memory available for.
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*/
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__u32 context;
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/**
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* @handle: [in]
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*
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* GEM handle of the memory to map.
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*/
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__u32 handle;
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/**
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* @flags: [in]
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*
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* Flags.
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*/
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__u32 flags;
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/**
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* @mapping: [out]
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*
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* Identifier corresponding to the mapping, to be used for
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* relocations or unmapping later.
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*/
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__u32 mapping;
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};
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struct drm_tegra_channel_unmap {
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/**
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* @context: [in]
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*
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* Channel identifier of the channel to unmap memory from.
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*/
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__u32 context;
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/**
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* @mapping: [in]
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*
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* Mapping identifier of the memory mapping to unmap.
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*/
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__u32 mapping;
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};
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/* Submission */
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/**
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* Specify that bit 39 of the patched-in address should be set to switch
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* swizzling between Tegra and non-Tegra sector layout on systems that store
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* surfaces in system memory in non-Tegra sector layout.
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*/
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#define DRM_TEGRA_SUBMIT_RELOC_SECTOR_LAYOUT (1 << 0)
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struct drm_tegra_submit_buf {
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/**
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* @mapping: [in]
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*
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* Identifier of the mapping to use in the submission.
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*/
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__u32 mapping;
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/**
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* @flags: [in]
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*
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* Flags.
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*/
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__u32 flags;
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/**
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* Information for relocation patching.
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*/
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struct {
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/**
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* @target_offset: [in]
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*
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* Offset from the start of the mapping of the data whose
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* address is to be patched into the gather.
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*/
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__u64 target_offset;
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/**
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* @gather_offset_words: [in]
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*
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* Offset in words from the start of the gather data to
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* where the address should be patched into.
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*/
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__u32 gather_offset_words;
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/**
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* @shift: [in]
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*
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* Number of bits the address should be shifted right before
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* patching in.
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*/
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__u32 shift;
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} reloc;
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};
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/**
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* Execute `words` words of Host1x opcodes specified in the `gather_data_ptr`
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* buffer. Each GATHER_UPTR command uses successive words from the buffer.
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*/
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#define DRM_TEGRA_SUBMIT_CMD_GATHER_UPTR 0
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/**
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* Wait for a syncpoint to reach a value before continuing with further
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* commands.
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*/
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#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT 1
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/**
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* Wait for a syncpoint to reach a value before continuing with further
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* commands. The threshold is calculated relative to the start of the job.
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*/
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#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT_RELATIVE 2
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struct drm_tegra_submit_cmd_gather_uptr {
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__u32 words;
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__u32 reserved[3];
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};
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struct drm_tegra_submit_cmd_wait_syncpt {
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__u32 id;
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__u32 value;
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__u32 reserved[2];
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};
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struct drm_tegra_submit_cmd {
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/**
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* @type: [in]
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*
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* Command type to execute. One of the DRM_TEGRA_SUBMIT_CMD*
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* defines.
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*/
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__u32 type;
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/**
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* @flags: [in]
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*
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* Flags.
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*/
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__u32 flags;
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union {
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struct drm_tegra_submit_cmd_gather_uptr gather_uptr;
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struct drm_tegra_submit_cmd_wait_syncpt wait_syncpt;
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__u32 reserved[4];
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};
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};
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struct drm_tegra_submit_syncpt {
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/**
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* @id: [in]
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*
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* ID of the syncpoint that the job will increment.
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*/
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__u32 id;
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/**
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* @flags: [in]
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*
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* Flags.
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*/
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__u32 flags;
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/**
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* @increments: [in]
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*
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* Number of times the job will increment this syncpoint.
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*/
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__u32 increments;
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/**
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* @value: [out]
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*
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* Value the syncpoint will have once the job has completed all
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* its specified syncpoint increments.
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*
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* Note that the kernel may increment the syncpoint before or after
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* the job. These increments are not reflected in this field.
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*
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* If the job hangs or times out, not all of the increments may
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* get executed.
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*/
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__u32 value;
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};
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struct drm_tegra_channel_submit {
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/**
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* @context: [in]
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*
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* Identifier of the channel to submit this job to.
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*/
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__u32 context;
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/**
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* @num_bufs: [in]
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*
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* Number of elements in the `bufs_ptr` array.
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*/
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__u32 num_bufs;
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/**
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* @num_cmds: [in]
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*
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* Number of elements in the `cmds_ptr` array.
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*/
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__u32 num_cmds;
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/**
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* @gather_data_words: [in]
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*
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* Number of 32-bit words in the `gather_data_ptr` array.
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*/
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__u32 gather_data_words;
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/**
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* @bufs_ptr: [in]
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*
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* Pointer to an array of drm_tegra_submit_buf structures.
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*/
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__u64 bufs_ptr;
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/**
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* @cmds_ptr: [in]
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*
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* Pointer to an array of drm_tegra_submit_cmd structures.
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*/
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__u64 cmds_ptr;
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/**
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* @gather_data_ptr: [in]
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*
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* Pointer to an array of Host1x opcodes to be used by GATHER_UPTR
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* commands.
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*/
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__u64 gather_data_ptr;
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/**
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* @syncobj_in: [in]
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*
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* Handle for DRM syncobj that will be waited before submission.
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* Ignored if zero.
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*/
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__u32 syncobj_in;
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/**
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* @syncobj_out: [in]
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*
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* Handle for DRM syncobj that will have its fence replaced with
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* the job's completion fence. Ignored if zero.
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*/
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__u32 syncobj_out;
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/**
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* @syncpt_incr: [in,out]
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*
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* Information about the syncpoint the job will increment.
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*/
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struct drm_tegra_submit_syncpt syncpt;
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};
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struct drm_tegra_syncpoint_allocate {
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/**
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* @id: [out]
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*
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* ID of allocated syncpoint.
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*/
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__u32 id;
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__u32 padding;
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};
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struct drm_tegra_syncpoint_free {
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/**
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* @id: [in]
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*
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* ID of syncpoint to free.
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*/
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__u32 id;
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__u32 padding;
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};
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struct drm_tegra_syncpoint_wait {
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/**
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* @timeout: [in]
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*
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* Absolute timestamp at which the wait will time out.
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*/
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__s64 timeout_ns;
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/**
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* @id: [in]
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*
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* ID of syncpoint to wait on.
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*/
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__u32 id;
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/**
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* @threshold: [in]
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*
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* Threshold to wait for.
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*/
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__u32 threshold;
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/**
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* @value: [out]
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*
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* Value of the syncpoint upon wait completion.
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*/
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__u32 value;
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__u32 padding;
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};
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#define DRM_IOCTL_TEGRA_CHANNEL_OPEN DRM_IOWR(DRM_COMMAND_BASE + 0x10, struct drm_tegra_channel_open)
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#define DRM_IOCTL_TEGRA_CHANNEL_CLOSE DRM_IOWR(DRM_COMMAND_BASE + 0x11, struct drm_tegra_channel_close)
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#define DRM_IOCTL_TEGRA_CHANNEL_MAP DRM_IOWR(DRM_COMMAND_BASE + 0x12, struct drm_tegra_channel_map)
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#define DRM_IOCTL_TEGRA_CHANNEL_UNMAP DRM_IOWR(DRM_COMMAND_BASE + 0x13, struct drm_tegra_channel_unmap)
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#define DRM_IOCTL_TEGRA_CHANNEL_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + 0x14, struct drm_tegra_channel_submit)
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#define DRM_IOCTL_TEGRA_SYNCPOINT_ALLOCATE DRM_IOWR(DRM_COMMAND_BASE + 0x20, struct drm_tegra_syncpoint_allocate)
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#define DRM_IOCTL_TEGRA_SYNCPOINT_FREE DRM_IOWR(DRM_COMMAND_BASE + 0x21, struct drm_tegra_syncpoint_free)
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#define DRM_IOCTL_TEGRA_SYNCPOINT_WAIT DRM_IOWR(DRM_COMMAND_BASE + 0x22, struct drm_tegra_syncpoint_wait)
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#if defined(__cplusplus)
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}
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#endif
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