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Microblaze patches for 6.1-rc1
- Add architecture support for Microblaze manager for error injection via break handler in BRAM. -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYz/WpgAKCRDKSWXLKUoM Ie2XAJ9LcKtheIlv2XmdSFiBa2957V6LfwCfUtd7QWilzu8b5JUZQIigFy9Dv+4= =UnyV -----END PGP SIGNATURE----- Merge tag 'microblaze-v6.1' of git://git.monstr.eu/linux-2.6-microblaze Pull microblaze updates from Michal Simek: "This adds architecture support for error injection which can be done only via local memory (BRAM) with enabling path for recovery after reset. These patches targets Triple Modular Redundacy (TMR) configuration where 3 Microblazes are running in parallel with monitoring logic. When an error happens (or is injected) system goes to break handler with full CPU reset and system recovery back to origin context. More information can be found at [1]" Link: https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/tmr/v1_0/pg268-tmr.pdf [1] * tag 'microblaze-v6.1' of git://git.monstr.eu/linux-2.6-microblaze: microblaze: Add support for error injection microblaze: Add custom break vector handler for mb manager microblaze: Add xmb_manager_register function
This commit is contained in:
Linus Torvalds
commit
57c92724c8
@ -204,6 +204,16 @@ config TASK_SIZE
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hex "Size of user task space" if TASK_SIZE_BOOL
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default "0x80000000"
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config MB_MANAGER
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bool "Support for Microblaze Manager"
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depends on ADVANCED_OPTIONS
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help
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This option enables API for configuring the MicroBlaze manager
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control register, which is consumed by the break handler to
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block the break.
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Say N here unless you know what you are doing.
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endmenu
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menu "Bus Options"
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29
arch/microblaze/include/asm/xilinx_mb_manager.h
Normal file
29
arch/microblaze/include/asm/xilinx_mb_manager.h
Normal file
@ -0,0 +1,29 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2022 Xilinx, Inc.
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*/
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#ifndef _XILINX_MB_MANAGER_H
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#define _XILINX_MB_MANAGER_H
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# ifndef __ASSEMBLY__
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#include <linux/of_address.h>
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/*
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* When the break vector gets asserted because of error injection, the break
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* signal must be blocked before exiting from the break handler, Below api
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* updates the manager address and control register and error counter callback
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* arguments, which will be used by the break handler to block the break and
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* call the callback function.
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*/
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void xmb_manager_register(uintptr_t phys_baseaddr, u32 cr_val,
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void (*callback)(void *data),
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void *priv, void (*reset_callback)(void *data));
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asmlinkage void xmb_inject_err(void);
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# endif /* __ASSEMBLY__ */
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/* Error injection offset */
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#define XMB_INJECT_ERR_OFFSET 0x200
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#endif /* _XILINX_MB_MANAGER_H */
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@ -120,5 +120,12 @@ int main(int argc, char *argv[])
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DEFINE(CC_FSR, offsetof(struct cpu_context, fsr));
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BLANK();
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/* struct cpuinfo */
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DEFINE(CI_DCS, offsetof(struct cpuinfo, dcache_size));
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DEFINE(CI_DCL, offsetof(struct cpuinfo, dcache_line_length));
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DEFINE(CI_ICS, offsetof(struct cpuinfo, icache_size));
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DEFINE(CI_ICL, offsetof(struct cpuinfo, icache_line_length));
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BLANK();
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return 0;
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}
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@ -27,9 +27,11 @@
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#include <asm/page.h>
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#include <asm/unistd.h>
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#include <asm/xilinx_mb_manager.h>
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#include <linux/errno.h>
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#include <asm/signal.h>
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#include <asm/mmu.h>
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#undef DEBUG
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@ -287,6 +289,44 @@ syscall_debug_table:
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.text
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.extern cpuinfo
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C_ENTRY(mb_flush_dcache):
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addik r1, r1, -PT_SIZE
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SAVE_REGS
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addik r3, r0, cpuinfo
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lwi r7, r3, CI_DCS
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lwi r8, r3, CI_DCL
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sub r9, r7, r8
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1:
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wdc.flush r9, r0
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bgtid r9, 1b
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addk r9, r9, r8
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RESTORE_REGS
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addik r1, r1, PT_SIZE
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rtsd r15, 8
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nop
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C_ENTRY(mb_invalidate_icache):
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addik r1, r1, -PT_SIZE
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SAVE_REGS
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addik r3, r0, cpuinfo
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lwi r7, r3, CI_ICS
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lwi r8, r3, CI_ICL
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sub r9, r7, r8
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1:
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wic r9, r0
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bgtid r9, 1b
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addk r9, r9, r8
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RESTORE_REGS
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addik r1, r1, PT_SIZE
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rtsd r15, 8
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nop
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/*
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* User trap.
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*
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@ -753,6 +793,160 @@ IRQ_return: /* MS: Make global symbol for debugging */
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rtid r14, 0
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nop
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#ifdef CONFIG_MB_MANAGER
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#define PT_PID PT_SIZE
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#define PT_TLBI PT_SIZE + 4
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#define PT_ZPR PT_SIZE + 8
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#define PT_TLBL0 PT_SIZE + 12
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#define PT_TLBH0 PT_SIZE + 16
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C_ENTRY(_xtmr_manager_reset):
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lwi r1, r0, xmb_manager_stackpointer
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/* Restore MSR */
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lwi r2, r1, PT_MSR
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mts rmsr, r2
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bri 4
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/* restore Special purpose registers */
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lwi r2, r1, PT_PID
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mts rpid, r2
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lwi r2, r1, PT_TLBI
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mts rtlbx, r2
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lwi r2, r1, PT_ZPR
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mts rzpr, r2
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#if CONFIG_XILINX_MICROBLAZE0_USE_FPU
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lwi r2, r1, PT_FSR
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mts rfsr, r2
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#endif
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/* restore all the tlb's */
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addik r3, r0, TOPHYS(tlb_skip)
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addik r6, r0, PT_TLBL0
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addik r7, r0, PT_TLBH0
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restore_tlb:
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add r6, r6, r1
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add r7, r7, r1
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lwi r2, r6, 0
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mts rtlblo, r2
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lwi r2, r7, 0
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mts rtlbhi, r2
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addik r6, r6, 4
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addik r7, r7, 4
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bgtid r3, restore_tlb
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addik r3, r3, -1
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lwi r5, r0, TOPHYS(xmb_manager_dev)
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lwi r8, r0, TOPHYS(xmb_manager_reset_callback)
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set_vms
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/* return from reset need -8 to adjust for rtsd r15, 8 */
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addik r15, r0, ret_from_reset - 8
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rtbd r8, 0
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nop
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ret_from_reset:
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set_bip /* Ints masked for state restore */
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VM_OFF
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/* MS: Restore all regs */
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RESTORE_REGS
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lwi r14, r1, PT_R14
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lwi r16, r1, PT_PC
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addik r1, r1, PT_SIZE + 36
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rtbd r16, 0
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nop
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/*
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* Break handler for MB Manager. Enter to _xmb_manager_break by
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* injecting fault in one of the TMR Microblaze core.
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* FIXME: This break handler supports getting
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* called from kernel space only.
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*/
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C_ENTRY(_xmb_manager_break):
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/*
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* Reserve memory in the stack for context store/restore
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* (which includes memory for storing tlbs (max two tlbs))
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*/
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addik r1, r1, -PT_SIZE - 36
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swi r1, r0, xmb_manager_stackpointer
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SAVE_REGS
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swi r14, r1, PT_R14 /* rewrite saved R14 value */
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swi r16, r1, PT_PC; /* PC and r16 are the same */
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lwi r6, r0, TOPHYS(xmb_manager_baseaddr)
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lwi r7, r0, TOPHYS(xmb_manager_crval)
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/*
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* When the break vector gets asserted because of error injection,
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* the break signal must be blocked before exiting from the
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* break handler, below code configures the tmr manager
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* control register to block break signal.
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*/
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swi r7, r6, 0
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/* Save the special purpose registers */
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mfs r2, rpid
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swi r2, r1, PT_PID
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mfs r2, rtlbx
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swi r2, r1, PT_TLBI
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mfs r2, rzpr
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swi r2, r1, PT_ZPR
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#if CONFIG_XILINX_MICROBLAZE0_USE_FPU
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mfs r2, rfsr
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swi r2, r1, PT_FSR
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#endif
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mfs r2, rmsr
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swi r2, r1, PT_MSR
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/* Save all the tlb's */
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addik r3, r0, TOPHYS(tlb_skip)
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addik r6, r0, PT_TLBL0
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addik r7, r0, PT_TLBH0
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save_tlb:
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add r6, r6, r1
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add r7, r7, r1
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mfs r2, rtlblo
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swi r2, r6, 0
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mfs r2, rtlbhi
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swi r2, r7, 0
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addik r6, r6, 4
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addik r7, r7, 4
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bgtid r3, save_tlb
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addik r3, r3, -1
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lwi r5, r0, TOPHYS(xmb_manager_dev)
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lwi r8, r0, TOPHYS(xmb_manager_callback)
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/* return from break need -8 to adjust for rtsd r15, 8 */
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addik r15, r0, ret_from_break - 8
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rtbd r8, 0
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nop
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ret_from_break:
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/* flush the d-cache */
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bralid r15, mb_flush_dcache
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nop
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/*
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* To make sure microblaze i-cache is in a proper state
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* invalidate the i-cache.
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*/
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bralid r15, mb_invalidate_icache
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nop
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set_bip; /* Ints masked for state restore */
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VM_OFF;
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mbar 1
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mbar 2
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bri 4
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suspend
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nop
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#endif
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/*
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* Debug trap for KGDB. Enter to _debug_exception by brki r16, 0x18
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* and call handling function with saved pt_regs
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@ -957,6 +1151,88 @@ ENTRY(_switch_to)
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rtsd r15, 8
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nop
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#ifdef CONFIG_MB_MANAGER
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.global xmb_inject_err
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.section .text
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.align 2
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.ent xmb_inject_err
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.type xmb_inject_err, @function
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xmb_inject_err:
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addik r1, r1, -PT_SIZE
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SAVE_REGS
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/* Switch to real mode */
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VM_OFF;
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set_bip;
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mbar 1
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mbar 2
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bralid r15, XMB_INJECT_ERR_OFFSET
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nop;
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/* enable virtual mode */
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set_vms;
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/* barrier for instructions and data accesses */
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mbar 1
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mbar 2
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/*
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* Enable Interrupts, Virtual Protected Mode, equalize
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* initial state for all possible entries.
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*/
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rtbd r0, 1f
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nop;
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1:
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RESTORE_REGS
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addik r1, r1, PT_SIZE
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rtsd r15, 8;
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nop;
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.end xmb_inject_err
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.section .data
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.global xmb_manager_dev
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.global xmb_manager_baseaddr
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.global xmb_manager_crval
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.global xmb_manager_callback
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.global xmb_manager_reset_callback
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.global xmb_manager_stackpointer
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.align 4
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xmb_manager_dev:
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.long 0
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xmb_manager_baseaddr:
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.long 0
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xmb_manager_crval:
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.long 0
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xmb_manager_callback:
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.long 0
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xmb_manager_reset_callback:
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.long 0
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xmb_manager_stackpointer:
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.long 0
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/*
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* When the break vector gets asserted because of error injection,
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* the break signal must be blocked before exiting from the
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* break handler, Below api updates the manager address and
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* control register and error count callback arguments,
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* which will be used by the break handler to block the
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* break and call the callback function.
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*/
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.global xmb_manager_register
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.section .text
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.align 2
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.ent xmb_manager_register
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.type xmb_manager_register, @function
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xmb_manager_register:
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swi r5, r0, xmb_manager_baseaddr
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swi r6, r0, xmb_manager_crval
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swi r7, r0, xmb_manager_callback
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swi r8, r0, xmb_manager_dev
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swi r9, r0, xmb_manager_reset_callback
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rtsd r15, 8;
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nop;
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.end xmb_manager_register
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#endif
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ENTRY(_reset)
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VM_OFF
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brai 0; /* Jump to reset vector */
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@ -964,19 +1240,43 @@ ENTRY(_reset)
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/* These are compiled and loaded into high memory, then
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* copied into place in mach_early_setup */
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.section .init.ivt, "ax"
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#if CONFIG_MANUAL_RESET_VECTOR
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#if CONFIG_MANUAL_RESET_VECTOR && !defined(CONFIG_MB_MANAGER)
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.org 0x0
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brai CONFIG_MANUAL_RESET_VECTOR
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#elif defined(CONFIG_MB_MANAGER)
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.org 0x0
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brai TOPHYS(_xtmr_manager_reset);
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#endif
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.org 0x8
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brai TOPHYS(_user_exception); /* syscall handler */
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.org 0x10
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brai TOPHYS(_interrupt); /* Interrupt handler */
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#ifdef CONFIG_MB_MANAGER
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.org 0x18
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brai TOPHYS(_xmb_manager_break); /* microblaze manager break handler */
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#else
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.org 0x18
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brai TOPHYS(_debug_exception); /* debug trap handler */
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#endif
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.org 0x20
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brai TOPHYS(_hw_exception_handler); /* HW exception handler */
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#ifdef CONFIG_MB_MANAGER
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/*
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* For TMR Inject API which injects the error should
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* be executed from LMB.
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* TMR Inject is programmed with address of 0x200 so that
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* when program counter matches with this address error will
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* be injected. 0x200 is expected to be next available bram
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* offset, hence used for this api.
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*/
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.org XMB_INJECT_ERR_OFFSET
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xmb_inject_error:
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nop
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rtsd r15, 8
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nop
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#endif
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.section .rodata,"a"
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#include "syscall_table.S"
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