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ravb: factor out register bit twiddling code
The driver has often repeated pattern of reading a register, AND'ing and/or OR'ing some bits and writing the value back. Factor the pattern out into ravb_modify() -- this saves 260 bytes of code with ARM gcc 4.7.3. While at it, update Cogent Embedded's copyrights. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -2,7 +2,7 @@
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*
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* Copyright (C) 2014-2015 Renesas Electronics Corporation
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* Copyright (C) 2015 Renesas Solutions Corp.
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* Copyright (C) 2015 Cogent Embedded, Inc. <source@cogentembedded.com>
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* Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
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*
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* Based on the SuperH Ethernet driver
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*
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@ -837,6 +837,8 @@ static inline void ravb_write(struct net_device *ndev, u32 data,
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iowrite32(data, priv->addr + reg);
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}
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void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
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u32 set);
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int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value);
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irqreturn_t ravb_ptp_interrupt(struct net_device *ndev);
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@ -2,7 +2,7 @@
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*
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* Copyright (C) 2014-2015 Renesas Electronics Corporation
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* Copyright (C) 2015 Renesas Solutions Corp.
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* Copyright (C) 2015 Cogent Embedded, Inc. <source@cogentembedded.com>
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* Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
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*
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* Based on the SuperH Ethernet driver
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*
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@ -42,6 +42,12 @@
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NETIF_MSG_RX_ERR | \
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NETIF_MSG_TX_ERR)
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void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
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u32 set)
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{
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ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
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}
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int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
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{
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int i;
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@ -59,8 +65,7 @@ static int ravb_config(struct net_device *ndev)
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int error;
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/* Set config mode */
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ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_CONFIG,
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CCC);
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ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
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/* Check if the operating mode is changed to the config mode */
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error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
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if (error)
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@ -72,13 +77,8 @@ static int ravb_config(struct net_device *ndev)
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static void ravb_set_duplex(struct net_device *ndev)
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{
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struct ravb_private *priv = netdev_priv(ndev);
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u32 ecmr = ravb_read(ndev, ECMR);
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if (priv->duplex) /* Full */
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ecmr |= ECMR_DM;
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else /* Half */
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ecmr &= ~ECMR_DM;
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ravb_write(ndev, ecmr, ECMR);
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ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex ? ECMR_DM : 0);
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}
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static void ravb_set_rate(struct net_device *ndev)
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@ -131,13 +131,8 @@ static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
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{
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struct ravb_private *priv = container_of(ctrl, struct ravb_private,
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mdiobb);
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u32 pir = ravb_read(priv->ndev, PIR);
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if (set)
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pir |= mask;
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else
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pir &= ~mask;
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ravb_write(priv->ndev, pir, PIR);
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ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
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}
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/* MDC pin control */
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@ -393,9 +388,9 @@ static int ravb_dmac_init(struct net_device *ndev)
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ravb_ring_format(ndev, RAVB_NC);
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#if defined(__LITTLE_ENDIAN)
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ravb_write(ndev, ravb_read(ndev, CCC) & ~CCC_BOC, CCC);
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ravb_modify(ndev, CCC, CCC_BOC, 0);
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#else
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ravb_write(ndev, ravb_read(ndev, CCC) | CCC_BOC, CCC);
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ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC);
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#endif
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/* Set AVB RX */
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@ -418,8 +413,7 @@ static int ravb_dmac_init(struct net_device *ndev)
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ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
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/* Setting the control will start the AVB-DMAC process. */
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ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_OPERATION,
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CCC);
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ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
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return 0;
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}
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@ -493,7 +487,7 @@ static void ravb_get_tx_tstamp(struct net_device *ndev)
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break;
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}
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}
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ravb_write(ndev, ravb_read(ndev, TCCR) | TCCR_TFR, TCCR);
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ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
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}
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}
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@ -613,13 +607,13 @@ static bool ravb_rx(struct net_device *ndev, int *quota, int q)
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static void ravb_rcv_snd_disable(struct net_device *ndev)
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{
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/* Disable TX and RX */
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ravb_write(ndev, ravb_read(ndev, ECMR) & ~(ECMR_RE | ECMR_TE), ECMR);
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ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
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}
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static void ravb_rcv_snd_enable(struct net_device *ndev)
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{
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/* Enable TX and RX */
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ravb_write(ndev, ravb_read(ndev, ECMR) | ECMR_RE | ECMR_TE, ECMR);
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ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
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}
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/* function for waiting dma process finished */
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@ -812,8 +806,8 @@ static int ravb_poll(struct napi_struct *napi, int budget)
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/* Re-enable RX/TX interrupts */
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spin_lock_irqsave(&priv->lock, flags);
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ravb_write(ndev, ravb_read(ndev, RIC0) | mask, RIC0);
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ravb_write(ndev, ravb_read(ndev, TIC) | mask, TIC);
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ravb_modify(ndev, RIC0, mask, mask);
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ravb_modify(ndev, TIC, mask, mask);
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mmiowb();
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spin_unlock_irqrestore(&priv->lock, flags);
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@ -852,8 +846,7 @@ static void ravb_adjust_link(struct net_device *ndev)
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ravb_set_rate(ndev);
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}
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if (!priv->link) {
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ravb_write(ndev, ravb_read(ndev, ECMR) & ~ECMR_TXF,
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ECMR);
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ravb_modify(ndev, ECMR, ECMR_TXF, 0);
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new_state = true;
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priv->link = phydev->link;
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if (priv->no_avb_link)
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@ -1393,7 +1386,7 @@ static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
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desc--;
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desc->die_dt = DT_FSTART;
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ravb_write(ndev, ravb_read(ndev, TCCR) | (TCCR_TSRQ0 << q), TCCR);
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ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
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priv->cur_tx[q] += NUM_TX_DESC;
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if (priv->cur_tx[q] - priv->dirty_tx[q] >
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@ -1468,15 +1461,10 @@ static void ravb_set_rx_mode(struct net_device *ndev)
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{
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struct ravb_private *priv = netdev_priv(ndev);
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unsigned long flags;
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u32 ecmr;
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spin_lock_irqsave(&priv->lock, flags);
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ecmr = ravb_read(ndev, ECMR);
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if (ndev->flags & IFF_PROMISC)
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ecmr |= ECMR_PRM;
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else
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ecmr &= ~ECMR_PRM;
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ravb_write(ndev, ecmr, ECMR);
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ravb_modify(ndev, ECMR, ECMR_PRM,
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ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
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mmiowb();
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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@ -1804,14 +1792,12 @@ static int ravb_probe(struct platform_device *pdev)
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/* Set AVB config mode */
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if (chip_id == RCAR_GEN2) {
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ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) |
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CCC_OPC_CONFIG, CCC);
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ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
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/* Set CSEL value */
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ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_CSEL) |
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CCC_CSEL_HPB, CCC);
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ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
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} else {
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ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) |
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CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB, CCC);
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ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
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CCC_GAC | CCC_CSEL_HPB);
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}
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/* Set CSEL value */
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@ -1824,7 +1810,7 @@ static int ravb_probe(struct platform_device *pdev)
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goto out_release;
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/* Request GTI loading */
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ravb_write(ndev, ravb_read(ndev, GCCR) | GCCR_LTI, GCCR);
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ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
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/* Allocate descriptor base address table */
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priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
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@ -2,7 +2,7 @@
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*
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* Copyright (C) 2013-2015 Renesas Electronics Corporation
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* Copyright (C) 2015 Renesas Solutions Corp.
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* Copyright (C) 2015 Cogent Embedded, Inc. <source@cogentembedded.com>
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* Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -21,7 +21,7 @@ static int ravb_ptp_tcr_request(struct ravb_private *priv, u32 request)
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if (error)
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return error;
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ravb_write(ndev, ravb_read(ndev, GCCR) | request, GCCR);
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ravb_modify(ndev, GCCR, request, request);
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return ravb_wait(ndev, GCCR, GCCR_TCR, GCCR_TCR_NOREQ);
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}
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@ -185,7 +185,6 @@ static int ravb_ptp_extts(struct ptp_clock_info *ptp,
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ptp.info);
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struct net_device *ndev = priv->ndev;
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unsigned long flags;
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u32 gic;
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if (req->index)
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return -EINVAL;
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@ -195,12 +194,7 @@ static int ravb_ptp_extts(struct ptp_clock_info *ptp,
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priv->ptp.extts[req->index] = on;
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spin_lock_irqsave(&priv->lock, flags);
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gic = ravb_read(ndev, GIC);
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if (on)
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gic |= GIC_PTCE;
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else
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gic &= ~GIC_PTCE;
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ravb_write(ndev, gic, GIC);
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ravb_modify(ndev, GIC, GIC_PTCE, on ? GIC_PTCE : 0);
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mmiowb();
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spin_unlock_irqrestore(&priv->lock, flags);
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@ -216,7 +210,6 @@ static int ravb_ptp_perout(struct ptp_clock_info *ptp,
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struct ravb_ptp_perout *perout;
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unsigned long flags;
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int error = 0;
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u32 gic;
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if (req->index)
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return -EINVAL;
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@ -248,9 +241,7 @@ static int ravb_ptp_perout(struct ptp_clock_info *ptp,
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error = ravb_ptp_update_compare(priv, (u32)start_ns);
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if (!error) {
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/* Unmask interrupt */
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gic = ravb_read(ndev, GIC);
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gic |= GIC_PTME;
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ravb_write(ndev, gic, GIC);
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ravb_modify(ndev, GIC, GIC_PTME, GIC_PTME);
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}
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} else {
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spin_lock_irqsave(&priv->lock, flags);
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@ -259,9 +250,7 @@ static int ravb_ptp_perout(struct ptp_clock_info *ptp,
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perout->period = 0;
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/* Mask interrupt */
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gic = ravb_read(ndev, GIC);
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gic &= ~GIC_PTME;
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ravb_write(ndev, gic, GIC);
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ravb_modify(ndev, GIC, GIC_PTME, 0);
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}
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mmiowb();
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spin_unlock_irqrestore(&priv->lock, flags);
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@ -331,7 +320,6 @@ void ravb_ptp_init(struct net_device *ndev, struct platform_device *pdev)
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{
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struct ravb_private *priv = netdev_priv(ndev);
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unsigned long flags;
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u32 gccr;
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priv->ptp.info = ravb_ptp_info;
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@ -340,8 +328,7 @@ void ravb_ptp_init(struct net_device *ndev, struct platform_device *pdev)
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spin_lock_irqsave(&priv->lock, flags);
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ravb_wait(ndev, GCCR, GCCR_TCR, GCCR_TCR_NOREQ);
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gccr = ravb_read(ndev, GCCR) & ~GCCR_TCSS;
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ravb_write(ndev, gccr | GCCR_TCSS_ADJGPTP, GCCR);
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ravb_modify(ndev, GCCR, GCCR_TCSS, GCCR_TCSS_ADJGPTP);
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mmiowb();
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spin_unlock_irqrestore(&priv->lock, flags);
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