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staging: rtl8192u: fix comments in r819xU_cmdpkt.h
This patch fixes the comments in r819xU_cmdpkt.h by: * removing any empty or unnecessary comments * replacing the // comments with /* */ comments * removing date and author information from comments This is done to improve code readability and to conform to linux kernel coding style. Signed-off-by: Xenia Ragiadakou <burzalodowa@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Xenia Ragiadakou
Greg Kroah-Hartman
parent
b777736b47
commit
56340097ca
@ -1,17 +1,17 @@
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#ifndef R819XUSB_CMDPKT_H
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#define R819XUSB_CMDPKT_H
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/* Different command packet have dedicated message length and definition. */
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#define CMPK_RX_TX_FB_SIZE sizeof(cmpk_txfb_t) //20
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#define CMPK_TX_SET_CONFIG_SIZE sizeof(cmpk_set_cfg_t) //16
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#define CMPK_BOTH_QUERY_CONFIG_SIZE sizeof(cmpk_set_cfg_t) //16
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#define CMPK_RX_TX_STS_SIZE sizeof(cmpk_tx_status_t)//
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#define CMPK_RX_DBG_MSG_SIZE sizeof(cmpk_rx_dbginfo_t)//
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#define CMPK_RX_TX_FB_SIZE sizeof(cmpk_txfb_t) /* 20 */
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#define CMPK_TX_SET_CONFIG_SIZE sizeof(cmpk_set_cfg_t) /* 16 */
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#define CMPK_BOTH_QUERY_CONFIG_SIZE sizeof(cmpk_set_cfg_t) /* 16 */
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#define CMPK_RX_TX_STS_SIZE sizeof(cmpk_tx_status_t)
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#define CMPK_RX_DBG_MSG_SIZE sizeof(cmpk_rx_dbginfo_t)
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#define CMPK_TX_RAHIS_SIZE sizeof(cmpk_tx_rahis_t)
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/* 2008/05/08 amy For USB constant. */
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#define ISR_TxBcnOk BIT27 // Transmit Beacon OK
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#define ISR_TxBcnErr BIT26 // Transmit Beacon Error
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#define ISR_BcnTimerIntr BIT13 // Beacon Timer Interrupt
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#define ISR_TxBcnOk BIT27 /* Transmit Beacon OK */
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#define ISR_TxBcnErr BIT26 /* Transmit Beacon Error */
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#define ISR_BcnTimerIntr BIT13 /* Beacon Timer Interrupt */
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/* Define element ID of command packet. */
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@ -20,38 +20,38 @@
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/* Define different command packet structure. */
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/* 1. RX side: TX feedback packet. */
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typedef struct tag_cmd_pkt_tx_feedback {
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// DWORD 0
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/* DWORD 0 */
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u8 element_id; /* Command packet type. */
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u8 length; /* Command packet length. */
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/* 2007/07/05 MH Change tx feedback info field. */
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/* Change tx feedback info field. */
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/*------TX Feedback Info Field */
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u8 TID:4; /* */
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u8 fail_reason:3; /* */
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u8 TID:4;
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u8 fail_reason:3;
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u8 tok:1; /* Transmit ok. */
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u8 reserve1:4; /* */
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u8 pkt_type:2; /* */
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u8 bandwidth:1; /* */
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u8 qos_pkt:1; /* */
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u8 reserve1:4;
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u8 pkt_type:2;
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u8 bandwidth:1;
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u8 qos_pkt:1;
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// DWORD 1
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u8 reserve2; /* */
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/* DWORD 1 */
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u8 reserve2;
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/*------TX Feedback Info Field */
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u8 retry_cnt; /* */
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u16 pkt_id; /* */
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u8 retry_cnt;
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u16 pkt_id;
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// DWORD 3
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u16 seq_num; /* */
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/* DWORD 3 */
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u16 seq_num;
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u8 s_rate; /* Start rate. */
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u8 f_rate; /* Final rate. */
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// DWORD 4
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u8 s_rts_rate; /* */
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u8 f_rts_rate; /* */
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u16 pkt_length; /* */
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/* DWORD 4 */
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u8 s_rts_rate;
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u8 f_rts_rate;
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u16 pkt_length;
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// DWORD 5
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u16 reserve3; /* */
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u16 duration; /* */
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/* DWORD 5 */
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u16 reserve3;
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u16 duration;
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} cmpk_txfb_t;
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/* 2. RX side: Interrupt status packet. It includes Beacon State,
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@ -68,17 +68,18 @@ typedef struct tag_cmd_pkt_interrupt_status {
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typedef struct tag_cmd_pkt_set_configuration {
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u8 element_id; /* Command packet type. */
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u8 length; /* Command packet length. */
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u16 reserve1; /* */
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u16 reserve1;
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/* Configuration info. */
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u8 cfg_reserve1:3;
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u8 cfg_size:2; /* Configuration info. */
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u8 cfg_type:2; /* Configuration info. */
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u8 cfg_action:1; /* Configuration info. */
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u8 cfg_reserve2; /* Configuration info. */
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u8 cfg_page:4; /* Configuration info. */
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u8 cfg_reserve3:4; /* Configuration info. */
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u8 cfg_offset; /* Configuration info. */
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u32 value; /* */
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u32 mask; /* */
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u8 cfg_size:2;
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u8 cfg_type:2;
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u8 cfg_action:1;
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u8 cfg_reserve2;
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u8 cfg_page:4;
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u8 cfg_reserve3:4;
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u8 cfg_offset;
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u32 value;
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u32 mask;
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} cmpk_set_cfg_t;
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/* 4. Both side : TX/RX query configuraton packet. The query structure is the
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@ -86,88 +87,78 @@ typedef struct tag_cmd_pkt_set_configuration {
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#define cmpk_query_cfg_t cmpk_set_cfg_t
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/* 5. Multi packet feedback status. */
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typedef struct tag_tx_stats_feedback { // PJ quick rxcmd 09042007
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// For endian transfer --> Driver will not the same as firmware structure.
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// DW 0
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typedef struct tag_tx_stats_feedback {
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/* For endian transfer --> Driver will not the same as
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firmware structure. */
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/* DW 0 */
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u16 reserve1;
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u8 length; // Command packet length
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u8 element_id; // Command packet type
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u8 length; /* Command packet length */
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u8 element_id; /* Command packet type */
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// DW 1
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u16 txfail; // Tx Fail count
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u16 txok; // Tx ok count
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/* DW 1 */
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u16 txfail; /* Tx fail count */
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u16 txok; /* Tx ok count */
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// DW 2
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u16 txmcok; // tx multicast
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u16 txretry; // Tx Retry count
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/* DW 2 */
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u16 txmcok; /* Tx multicast */
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u16 txretry; /* Tx retry count */
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// DW 3
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u16 txucok; // tx unicast
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u16 txbcok; // tx broadcast
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/* DW 3 */
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u16 txucok; /* Tx unicast */
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u16 txbcok; /* Tx broadcast */
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// DW 4
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u16 txbcfail; //
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u16 txmcfail; //
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/* DW 4 */
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u16 txbcfail;
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u16 txmcfail;
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// DW 5
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u16 reserve2; //
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u16 txucfail; //
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/* DW 5 */
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u16 reserve2;
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u16 txucfail;
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// DW 6-8
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/* DW 6-8 */
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u32 txmclength;
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u32 txbclength;
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u32 txuclength;
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// DW 9
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/* DW 9 */
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u16 reserve3_23;
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u8 reserve3_1;
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u8 rate;
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} __attribute__((packed)) cmpk_tx_status_t;
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/* 6. Debug feedback message. */
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/* 2007/10/23 MH Define RX debug message */
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/* Define RX debug message */
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typedef struct tag_rx_debug_message_feedback {
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// For endian transfer --> for driver
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// DW 0
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/* For endian transfer --> for driver */
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/* DW 0 */
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u16 reserve1;
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u8 length; // Command packet length
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u8 element_id; // Command packet type
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u8 length; /* Command packet length */
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u8 element_id; /* Command packet type */
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// DW 1-??
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// Variable debug message.
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/* DW 1-?? */
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/* Variable debug message. */
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} cmpk_rx_dbginfo_t;
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/* 2008/03/20 MH Define transmit rate history. For big endian format. */
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/* Define transmit rate history. For big endian format. */
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typedef struct tag_tx_rate_history {
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// For endian transfer --> for driver
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// DW 0
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u8 element_id; // Command packet type
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u8 length; // Command packet length
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/* For endian transfer --> for driver */
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/* DW 0 */
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u8 element_id; /* Command packet type */
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u8 length; /* Command packet length */
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u16 reserved1;
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// DW 1-2 CCK rate counter
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/* DW 1-2 CCK rate counter */
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u16 cck[4];
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// DW 3-6
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/* DW 3-6 */
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u16 ofdm[8];
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// DW 7-14
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//UINT16 MCS_BW0_SG0[16];
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// DW 15-22
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//UINT16 MCS_BW1_SG0[16];
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// DW 23-30
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//UINT16 MCS_BW0_SG1[16];
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// DW 31-38
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//UINT16 MCS_BW1_SG1[16];
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// DW 7-14 BW=0 SG=0
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// DW 15-22 BW=1 SG=0
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// DW 23-30 BW=0 SG=1
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// DW 31-38 BW=1 SG=1
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/* DW 7-14 BW=0 SG=0
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* DW 15-22 BW=1 SG=0
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* DW 23-30 BW=0 SG=1
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* DW 31-38 BW=1 SG=1
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*/
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u16 ht_mcs[4][16];
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} __attribute__((packed)) cmpk_tx_rahis_t;
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