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dts/ls2080a: Update DTSI to add support of various peripherals
This patch updates the LS2080a DTSI (DTS Include) file to add support for the following peripherals: - USB 3.0 Host - PMU - CCN-504 - SATA - SPI - PCIe Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Bhupesh Sharma
Arnd Bergmann
parent
736c16d37f
commit
5461597f6c
@ -71,48 +71,56 @@
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x0>;
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clocks = <&clockgen 1 0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x1>;
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clocks = <&clockgen 1 0>;
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x100>;
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clocks = <&clockgen 1 1>;
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};
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cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x101>;
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clocks = <&clockgen 1 1>;
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};
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cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x200>;
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clocks = <&clockgen 1 2>;
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};
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cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x201>;
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clocks = <&clockgen 1 2>;
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};
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cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x300>;
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clocks = <&clockgen 1 3>;
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};
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cpu@301 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x301>;
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clocks = <&clockgen 1 3>;
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};
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};
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@ -122,13 +130,32 @@
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/* DRAM space - 1, size : 2 GB DRAM */
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};
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sysclk: sysclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "sysclk";
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};
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gic: interrupt-controller@6000000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
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<0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
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<0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
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<0x0 0x0c0c0000 0 0x2000>, /* GICC */
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<0x0 0x0c0d0000 0 0x1000>, /* GICH */
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<0x0 0x0c0e0000 0 0x20000>; /* GICV */
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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interrupts = <1 9 0x4>;
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its: gic-its@6020000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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reg = <0x0 0x6020000 0 0x20000>;
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};
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};
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timer {
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@ -139,25 +166,355 @@
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<1 10 0x8>; /* Hypervisor PPI, active-low */
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};
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serial0: serial@21c0500 {
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0500 0x0 0x100>;
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clock-frequency = <0>; /* Updated by bootloader */
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interrupts = <0 32 0x1>; /* edge triggered */
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
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};
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serial1: serial@21c0600 {
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0600 0x0 0x100>;
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clock-frequency = <0>; /* Updated by bootloader */
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interrupts = <0 32 0x1>; /* edge triggered */
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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fsl_mc: fsl-mc@80c000000 {
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compatible = "fsl,qoriq-mc";
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reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
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<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
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clockgen: clocking@1300000 {
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compatible = "fsl,ls2080a-clockgen";
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reg = <0 0x1300000 0 0xa0000>;
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#clock-cells = <2>;
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clocks = <&sysclk>;
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};
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serial0: serial@21c0500 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0500 0x0 0x100>;
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clocks = <&clockgen 4 3>;
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interrupts = <0 32 0x4>; /* Level high type */
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};
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serial1: serial@21c0600 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0600 0x0 0x100>;
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clocks = <&clockgen 4 3>;
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interrupts = <0 32 0x4>; /* Level high type */
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};
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fsl_mc: fsl-mc@80c000000 {
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compatible = "fsl,qoriq-mc";
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reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
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<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
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};
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smmu: iommu@5000000 {
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compatible = "arm,mmu-500";
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reg = <0 0x5000000 0 0x800000>;
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#global-interrupts = <12>;
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interrupts = <0 13 4>, /* global secure fault */
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<0 14 4>, /* combined secure interrupt */
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<0 15 4>, /* global non-secure fault */
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<0 16 4>, /* combined non-secure interrupt */
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/* performance counter interrupts 0-7 */
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<0 211 4>, <0 212 4>,
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<0 213 4>, <0 214 4>,
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<0 215 4>, <0 216 4>,
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<0 217 4>, <0 218 4>,
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/* per context interrupt, 64 interrupts */
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<0 146 4>, <0 147 4>,
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<0 148 4>, <0 149 4>,
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<0 150 4>, <0 151 4>,
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<0 152 4>, <0 153 4>,
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<0 154 4>, <0 155 4>,
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<0 156 4>, <0 157 4>,
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<0 158 4>, <0 159 4>,
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<0 160 4>, <0 161 4>,
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<0 162 4>, <0 163 4>,
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<0 164 4>, <0 165 4>,
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<0 166 4>, <0 167 4>,
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<0 168 4>, <0 169 4>,
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<0 170 4>, <0 171 4>,
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<0 172 4>, <0 173 4>,
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<0 174 4>, <0 175 4>,
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<0 176 4>, <0 177 4>,
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<0 178 4>, <0 179 4>,
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<0 180 4>, <0 181 4>,
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<0 182 4>, <0 183 4>,
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<0 184 4>, <0 185 4>,
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<0 186 4>, <0 187 4>,
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<0 188 4>, <0 189 4>,
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<0 190 4>, <0 191 4>,
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<0 192 4>, <0 193 4>,
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<0 194 4>, <0 195 4>,
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<0 196 4>, <0 197 4>,
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<0 198 4>, <0 199 4>,
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<0 200 4>, <0 201 4>,
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<0 202 4>, <0 203 4>,
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<0 204 4>, <0 205 4>,
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<0 206 4>, <0 207 4>,
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<0 208 4>, <0 209 4>;
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mmu-masters = <&fsl_mc 0x300 0>;
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};
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dspi: dspi@2100000 {
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status = "disabled";
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compatible = "fsl,vf610-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2100000 0x0 0x10000>;
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interrupts = <0 26 0x4>; /* Level high type */
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clocks = <&clockgen 4 3>;
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clock-names = "dspi";
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spi-num-chipselects = <5>;
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bus-num = <0>;
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};
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esdhc: esdhc@2140000 {
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status = "disabled";
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compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
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reg = <0x0 0x2140000 0x0 0x10000>;
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interrupts = <0 28 0x4>; /* Level high type */
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clock-frequency = <0>; /* Updated by bootloader */
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voltage-ranges = <1800 1800 3300 3300>;
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sdhci,auto-cmd12;
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bus-width = <4>;
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};
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gpio0: gpio@2300000 {
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compatible = "fsl,qoriq-gpio";
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reg = <0x0 0x2300000 0x0 0x10000>;
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interrupts = <0 36 0x4>; /* Level high type */
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio@2310000 {
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compatible = "fsl,qoriq-gpio";
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reg = <0x0 0x2310000 0x0 0x10000>;
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interrupts = <0 36 0x4>; /* Level high type */
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@2320000 {
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compatible = "fsl,qoriq-gpio";
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reg = <0x0 0x2320000 0x0 0x10000>;
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interrupts = <0 37 0x4>; /* Level high type */
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@2330000 {
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compatible = "fsl,qoriq-gpio";
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reg = <0x0 0x2330000 0x0 0x10000>;
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interrupts = <0 37 0x4>; /* Level high type */
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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i2c0: i2c@2000000 {
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status = "disabled";
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2000000 0x0 0x10000>;
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interrupts = <0 34 0x4>; /* Level high type */
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clock-names = "i2c";
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clocks = <&clockgen 4 3>;
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};
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i2c1: i2c@2010000 {
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status = "disabled";
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2010000 0x0 0x10000>;
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interrupts = <0 34 0x4>; /* Level high type */
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clock-names = "i2c";
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clocks = <&clockgen 4 3>;
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};
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i2c2: i2c@2020000 {
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status = "disabled";
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2020000 0x0 0x10000>;
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interrupts = <0 35 0x4>; /* Level high type */
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clock-names = "i2c";
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clocks = <&clockgen 4 3>;
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};
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i2c3: i2c@2030000 {
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status = "disabled";
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2030000 0x0 0x10000>;
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interrupts = <0 35 0x4>; /* Level high type */
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clock-names = "i2c";
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clocks = <&clockgen 4 3>;
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};
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ifc: ifc@2240000 {
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compatible = "fsl,ifc", "simple-bus";
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reg = <0x0 0x2240000 0x0 0x20000>;
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interrupts = <0 21 0x4>; /* Level high type */
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little-endian;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x5 0x80000000 0x08000000
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2 0 0x5 0x30000000 0x00010000
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3 0 0x5 0x20000000 0x00010000>;
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};
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qspi: quadspi@20c0000 {
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status = "disabled";
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compatible = "fsl,vf610-qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x20c0000 0x0 0x10000>,
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<0x0 0x20000000 0x0 0x10000000>;
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reg-names = "QuadSPI", "QuadSPI-memory";
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interrupts = <0 25 0x4>; /* Level high type */
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clocks = <&clockgen 4 3>, <&clockgen 4 3>;
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clock-names = "qspi_en", "qspi";
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};
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pcie@3400000 {
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compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
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reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
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0x10 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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interrupts = <0 108 0x4>; /* Level high type */
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interrupt-names = "intr";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <4>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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msi-parent = <&its>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
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<0000 0 0 2 &gic 0 0 0 110 4>,
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<0000 0 0 3 &gic 0 0 0 111 4>,
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<0000 0 0 4 &gic 0 0 0 112 4>;
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};
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pcie@3500000 {
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compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
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reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
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0x12 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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interrupts = <0 113 0x4>; /* Level high type */
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interrupt-names = "intr";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <4>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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msi-parent = <&its>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
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<0000 0 0 2 &gic 0 0 0 115 4>,
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<0000 0 0 3 &gic 0 0 0 116 4>,
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<0000 0 0 4 &gic 0 0 0 117 4>;
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};
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pcie@3600000 {
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compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
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reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
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0x14 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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interrupts = <0 118 0x4>; /* Level high type */
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interrupt-names = "intr";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <8>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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msi-parent = <&its>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
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<0000 0 0 2 &gic 0 0 0 120 4>,
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<0000 0 0 3 &gic 0 0 0 121 4>,
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<0000 0 0 4 &gic 0 0 0 122 4>;
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};
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pcie@3700000 {
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compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
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reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
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0x16 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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interrupts = <0 123 0x4>; /* Level high type */
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interrupt-names = "intr";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <4>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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msi-parent = <&its>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
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<0000 0 0 2 &gic 0 0 0 125 4>,
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<0000 0 0 3 &gic 0 0 0 126 4>,
|
||||
<0000 0 0 4 &gic 0 0 0 127 4>;
|
||||
};
|
||||
|
||||
sata0: sata@3200000 {
|
||||
status = "disabled";
|
||||
compatible = "fsl,ls2080a-ahci";
|
||||
reg = <0x0 0x3200000 0x0 0x10000>;
|
||||
interrupts = <0 133 0x4>; /* Level high type */
|
||||
clocks = <&clockgen 4 3>;
|
||||
};
|
||||
|
||||
sata1: sata@3210000 {
|
||||
status = "disabled";
|
||||
compatible = "fsl,ls2080a-ahci";
|
||||
reg = <0x0 0x3210000 0x0 0x10000>;
|
||||
interrupts = <0 136 0x4>; /* Level high type */
|
||||
clocks = <&clockgen 4 3>;
|
||||
};
|
||||
|
||||
usb0: usb3@3100000 {
|
||||
status = "disabled";
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x3100000 0x0 0x10000>;
|
||||
interrupts = <0 80 0x4>; /* Level high type */
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb1: usb3@3110000 {
|
||||
status = "disabled";
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x3110000 0x0 0x10000>;
|
||||
interrupts = <0 81 0x4>; /* Level high type */
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
ccn@4000000 {
|
||||
compatible = "arm,ccn-504";
|
||||
reg = <0x0 0x04000000 0x0 0x01000000>;
|
||||
interrupts = <0 12 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user