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ASoC: Add initial ZL38060 driver
The ZL38060 is a "Connected Home Audio Processor" from Microsemi, which consists of a Digital Signal Processor (DSP), several Digital Audio Interfaces (DAIs), analog outputs, and a block of 14 GPIOs. This driver supports only a tiny subset of the chip's functionality and possible configurations: - bypass mode (whole dsp block is bypassed) - chip's I2S DAI routed directly to/from DACs and microphone - chip's internal clock is driven by a 12 MHz external crystal - chip's DAI connected to CPU is I2S, and bit + frame clock master - chip must be strapped for "host boot": in this mode, firmware will be provided by this driver. Signed-off-by: Sven Van Asbroeck <TheSven73@gmail.com> Link: https://lore.kernel.org/r/20200417221341.31428-2-TheSven73@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Sven Van Asbroeck
Mark Brown
parent
19f303caf6
commit
52e8a94baf
@ -272,6 +272,7 @@ config SND_SOC_ALL_CODECS
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imply SND_SOC_WM9712
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imply SND_SOC_WM9713
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imply SND_SOC_WSA881X
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imply SND_SOC_ZL38060
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help
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Normally ASoC codec drivers are only built if a machine driver which
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uses them is also built since they are only usable with a machine
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@ -1645,6 +1646,16 @@ config SND_SOC_WSA881X
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This enables support for Qualcomm WSA8810/WSA8815 Class-D
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Smart Speaker Amplifier.
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config SND_SOC_ZL38060
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tristate "Microsemi ZL38060 Connected Home Audio Processor"
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depends on SPI_MASTER
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select GPIOLIB
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select REGMAP
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help
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Support for ZL38060 Connected Home Audio Processor from Microsemi,
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which consists of a Digital Signal Processor (DSP), several Digital
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Audio Interfaces (DAIs), analog outputs, and a block of 14 GPIOs.
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config SND_SOC_ZX_AUD96P22
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tristate "ZTE ZX AUD96P22 CODEC"
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depends on I2C
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@ -288,6 +288,7 @@ snd-soc-wm9712-objs := wm9712.o
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snd-soc-wm9713-objs := wm9713.o
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snd-soc-wm-hubs-objs := wm_hubs.o
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snd-soc-wsa881x-objs := wsa881x.o
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snd-soc-zl38060-objs := zl38060.o
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snd-soc-zx-aud96p22-objs := zx_aud96p22.o
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# Amp
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snd-soc-max9877-objs := max9877.o
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@ -588,6 +589,7 @@ obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o
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obj-$(CONFIG_SND_SOC_WM_ADSP) += snd-soc-wm-adsp.o
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obj-$(CONFIG_SND_SOC_WM_HUBS) += snd-soc-wm-hubs.o
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obj-$(CONFIG_SND_SOC_WSA881X) += snd-soc-wsa881x.o
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obj-$(CONFIG_SND_SOC_ZL38060) += snd-soc-zl38060.o
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obj-$(CONFIG_SND_SOC_ZX_AUD96P22) += snd-soc-zx-aud96p22.o
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# Amp
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638
sound/soc/codecs/zl38060.c
Normal file
638
sound/soc/codecs/zl38060.c
Normal file
@ -0,0 +1,638 @@
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// SPDX-License-Identifier: GPL-2.0-only
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//
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// Codec driver for Microsemi ZL38060 Connected Home Audio Processor.
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//
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// Copyright(c) 2020 Sven Van Asbroeck
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// The ZL38060 is very flexible and configurable. This driver implements only a
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// tiny subset of the chip's possible configurations:
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//
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// - DSP block bypassed: DAI routed straight to DACs
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// microphone routed straight to DAI
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// - chip's internal clock is driven by a 12 MHz external crystal
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// - chip's DAI connected to CPU is I2S, and bit + frame clock master
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// - chip must be strapped for "host boot": in this mode, firmware will be
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// provided by this driver.
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#include <linux/gpio/consumer.h>
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#include <linux/gpio/driver.h>
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#include <linux/property.h>
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#include <linux/spi/spi.h>
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#include <linux/regmap.h>
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#include <linux/module.h>
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#include <linux/ihex.h>
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#include <sound/pcm_params.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/soc.h>
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#define DRV_NAME "zl38060"
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#define ZL38_RATES (SNDRV_PCM_RATE_8000 |\
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SNDRV_PCM_RATE_16000 |\
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SNDRV_PCM_RATE_48000)
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#define ZL38_FORMATS SNDRV_PCM_FMTBIT_S16_LE
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#define HBI_FIRMWARE_PAGE 0xFF
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#define ZL38_MAX_RAW_XFER 0x100
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#define REG_TDMA_CFG_CLK 0x0262
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#define CFG_CLK_PCLK_SHIFT 4
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#define CFG_CLK_PCLK_MASK (0x7ff << CFG_CLK_PCLK_SHIFT)
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#define CFG_CLK_PCLK(bits) ((bits - 1) << CFG_CLK_PCLK_SHIFT)
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#define CFG_CLK_MASTER BIT(15)
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#define CFG_CLK_FSRATE_MASK 0x7
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#define CFG_CLK_FSRATE_8KHZ 0x1
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#define CFG_CLK_FSRATE_16KHZ 0x2
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#define CFG_CLK_FSRATE_48KHZ 0x6
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#define REG_CLK_CFG 0x0016
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#define CLK_CFG_SOURCE_XTAL BIT(15)
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#define REG_CLK_STATUS 0x0014
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#define CLK_STATUS_HWRST BIT(0)
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#define REG_PARAM_RESULT 0x0034
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#define PARAM_RESULT_READY 0xD3D3
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#define REG_PG255_BASE_HI 0x000C
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#define REG_PG255_OFFS(addr) ((HBI_FIRMWARE_PAGE << 8) | (addr & 0xFF))
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#define REG_FWR_EXEC 0x012C
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#define REG_CMD 0x0032
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#define REG_HW_REV 0x0020
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#define REG_FW_PROD 0x0022
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#define REG_FW_REV 0x0024
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#define REG_SEMA_FLAGS 0x0006
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#define SEMA_FLAGS_BOOT_CMD BIT(0)
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#define SEMA_FLAGS_APP_REBOOT BIT(1)
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#define REG_HW_REV 0x0020
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#define REG_FW_PROD 0x0022
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#define REG_FW_REV 0x0024
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#define REG_GPIO_DIR 0x02DC
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#define REG_GPIO_DAT 0x02DA
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#define BOOTCMD_LOAD_COMPLETE 0x000D
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#define BOOTCMD_FW_GO 0x0008
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#define FIRMWARE_MAJOR 2
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#define FIRMWARE_MINOR 2
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struct zl38_codec_priv {
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struct device *dev;
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struct regmap *regmap;
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bool is_stream_in_use[2];
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struct gpio_chip *gpio_chip;
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};
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static int zl38_fw_issue_command(struct regmap *regmap, u16 cmd)
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{
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unsigned int val;
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int err;
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err = regmap_read_poll_timeout(regmap, REG_SEMA_FLAGS, val,
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!(val & SEMA_FLAGS_BOOT_CMD), 10000,
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10000 * 100);
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if (err)
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return err;
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err = regmap_write(regmap, REG_CMD, cmd);
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if (err)
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return err;
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err = regmap_update_bits(regmap, REG_SEMA_FLAGS, SEMA_FLAGS_BOOT_CMD,
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SEMA_FLAGS_BOOT_CMD);
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if (err)
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return err;
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return regmap_read_poll_timeout(regmap, REG_CMD, val, !val, 10000,
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10000 * 100);
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}
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static int zl38_fw_go(struct regmap *regmap)
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{
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int err;
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err = zl38_fw_issue_command(regmap, BOOTCMD_LOAD_COMPLETE);
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if (err)
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return err;
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return zl38_fw_issue_command(regmap, BOOTCMD_FW_GO);
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}
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static int zl38_fw_enter_boot_mode(struct regmap *regmap)
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{
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unsigned int val;
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int err;
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err = regmap_update_bits(regmap, REG_CLK_STATUS, CLK_STATUS_HWRST,
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CLK_STATUS_HWRST);
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if (err)
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return err;
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return regmap_read_poll_timeout(regmap, REG_PARAM_RESULT, val,
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val == PARAM_RESULT_READY, 1000, 50000);
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}
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static int
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zl38_fw_send_data(struct regmap *regmap, u32 addr, const void *data, u16 len)
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{
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__be32 addr_base = cpu_to_be32(addr & ~0xFF);
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int err;
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err = regmap_raw_write(regmap, REG_PG255_BASE_HI, &addr_base,
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sizeof(addr_base));
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if (err)
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return err;
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return regmap_raw_write(regmap, REG_PG255_OFFS(addr), data, len);
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}
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static int zl38_fw_send_xaddr(struct regmap *regmap, const void *data)
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{
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/* execution address from ihex: 32-bit little endian.
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* device register expects 32-bit big endian.
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*/
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u32 addr = le32_to_cpup(data);
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__be32 baddr = cpu_to_be32(addr);
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return regmap_raw_write(regmap, REG_FWR_EXEC, &baddr, sizeof(baddr));
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}
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static int zl38_load_firmware(struct device *dev, struct regmap *regmap)
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{
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const struct ihex_binrec *rec;
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const struct firmware *fw;
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u32 addr;
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u16 len;
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int err;
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/* how to get this firmware:
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* 1. request and download chip firmware from Microsemi
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* (provided by Microsemi in srec format)
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* 2. convert downloaded firmware from srec to ihex. Simple tool:
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* https://gitlab.com/TheSven73/s3-to-irec
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* 3. convert ihex to binary (.fw) using ihex2fw tool which is included
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* with the Linux kernel sources
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*/
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err = request_ihex_firmware(&fw, "zl38060.fw", dev);
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if (err)
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return err;
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err = zl38_fw_enter_boot_mode(regmap);
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if (err)
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goto out;
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rec = (const struct ihex_binrec *)fw->data;
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while (rec) {
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addr = be32_to_cpu(rec->addr);
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len = be16_to_cpu(rec->len);
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if (addr) {
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/* regular data ihex record */
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err = zl38_fw_send_data(regmap, addr, rec->data, len);
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} else if (len == 4) {
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/* execution address ihex record */
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err = zl38_fw_send_xaddr(regmap, rec->data);
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} else {
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err = -EINVAL;
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}
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if (err)
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goto out;
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/* next ! */
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rec = ihex_next_binrec(rec);
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}
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err = zl38_fw_go(regmap);
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out:
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release_firmware(fw);
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return err;
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}
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static int zl38_software_reset(struct regmap *regmap)
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{
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unsigned int val;
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int err;
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err = regmap_update_bits(regmap, REG_SEMA_FLAGS, SEMA_FLAGS_APP_REBOOT,
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SEMA_FLAGS_APP_REBOOT);
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if (err)
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return err;
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/* wait for host bus interface to settle.
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* Not sure if this is required: Microsemi's vendor driver does this,
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* but the firmware manual does not mention it. Leave it in, there's
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* little downside, apart from a slower reset.
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*/
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msleep(50);
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return regmap_read_poll_timeout(regmap, REG_SEMA_FLAGS, val,
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!(val & SEMA_FLAGS_APP_REBOOT), 10000,
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10000 * 100);
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}
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static int zl38_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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{
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struct zl38_codec_priv *priv = snd_soc_dai_get_drvdata(dai);
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int err;
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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/* firmware default is normal i2s */
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break;
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default:
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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/* firmware default is normal bitclock and frame */
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break;
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default:
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBM_CFM:
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/* always 32 bits per frame (= 16 bits/channel, 2 channels) */
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err = regmap_update_bits(priv->regmap, REG_TDMA_CFG_CLK,
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CFG_CLK_MASTER | CFG_CLK_PCLK_MASK,
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CFG_CLK_MASTER | CFG_CLK_PCLK(32));
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if (err)
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return err;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int zl38_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct zl38_codec_priv *priv = snd_soc_dai_get_drvdata(dai);
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bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
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unsigned int fsrate;
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int err;
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/* We cannot change hw_params while the dai is already in use - the
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* software reset will corrupt the audio. However, this is not required,
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* as the chip's TDM buses are fully symmetric, which mandates identical
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* rates, channels, and samplebits for record and playback.
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*/
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if (priv->is_stream_in_use[!tx])
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goto skip_setup;
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switch (params_rate(params)) {
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case 8000:
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fsrate = CFG_CLK_FSRATE_8KHZ;
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break;
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case 16000:
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fsrate = CFG_CLK_FSRATE_16KHZ;
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break;
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case 48000:
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fsrate = CFG_CLK_FSRATE_48KHZ;
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break;
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default:
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return -EINVAL;
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};
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err = regmap_update_bits(priv->regmap, REG_TDMA_CFG_CLK,
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CFG_CLK_FSRATE_MASK, fsrate);
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if (err)
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return err;
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/* chip requires a software reset to apply audio register changes */
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err = zl38_software_reset(priv->regmap);
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if (err)
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return err;
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skip_setup:
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priv->is_stream_in_use[tx] = true;
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return 0;
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}
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static int zl38_hw_free(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct zl38_codec_priv *priv = snd_soc_dai_get_drvdata(dai);
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bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
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priv->is_stream_in_use[tx] = false;
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return 0;
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}
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/* stereo bypass with no AEC */
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static const struct reg_sequence cp_config_stereo_bypass[] = {
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/* interconnects must be programmed first */
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{ 0x0210, 0x0005 }, /* DAC1 in <= I2S1-L */
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{ 0x0212, 0x0006 }, /* DAC2 in <= I2S1-R */
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{ 0x0214, 0x0001 }, /* I2S1-L in <= MIC1 */
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{ 0x0216, 0x0001 }, /* I2S1-R in <= MIC1 */
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{ 0x0224, 0x0000 }, /* AEC-S in <= n/a */
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{ 0x0226, 0x0000 }, /* AEC-R in <= n/a */
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/* output enables must be programmed next */
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{ 0x0202, 0x000F }, /* enable I2S1 + DAC */
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};
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static const struct snd_soc_dai_ops zl38_dai_ops = {
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.set_fmt = zl38_set_fmt,
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.hw_params = zl38_hw_params,
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.hw_free = zl38_hw_free,
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};
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static struct snd_soc_dai_driver zl38_dai = {
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.name = "zl38060-tdma",
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.playback = {
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.stream_name = "Playback",
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.channels_min = 2,
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.channels_max = 2,
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.rates = ZL38_RATES,
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.formats = ZL38_FORMATS,
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},
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.capture = {
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.stream_name = "Capture",
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.channels_min = 2,
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.channels_max = 2,
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.rates = ZL38_RATES,
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.formats = ZL38_FORMATS,
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},
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.ops = &zl38_dai_ops,
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.symmetric_rates = 1,
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.symmetric_samplebits = 1,
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.symmetric_channels = 1,
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};
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static const struct snd_soc_dapm_widget zl38_dapm_widgets[] = {
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SND_SOC_DAPM_OUTPUT("DAC1"),
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SND_SOC_DAPM_OUTPUT("DAC2"),
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SND_SOC_DAPM_INPUT("DMICL"),
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};
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static const struct snd_soc_dapm_route zl38_dapm_routes[] = {
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{ "DAC1", NULL, "Playback" },
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{ "DAC2", NULL, "Playback" },
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{ "Capture", NULL, "DMICL" },
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};
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static const struct snd_soc_component_driver zl38_component_dev = {
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.dapm_widgets = zl38_dapm_widgets,
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.num_dapm_widgets = ARRAY_SIZE(zl38_dapm_widgets),
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.dapm_routes = zl38_dapm_routes,
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.num_dapm_routes = ARRAY_SIZE(zl38_dapm_routes),
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.endianness = 1,
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.non_legacy_dai_naming = 1,
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};
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|
||||
static void chip_gpio_set(struct gpio_chip *c, unsigned int offset, int val)
|
||||
{
|
||||
struct regmap *regmap = gpiochip_get_data(c);
|
||||
unsigned int mask = BIT(offset);
|
||||
|
||||
regmap_update_bits(regmap, REG_GPIO_DAT, mask, val ? mask : 0);
|
||||
}
|
||||
|
||||
static int chip_gpio_get(struct gpio_chip *c, unsigned int offset)
|
||||
{
|
||||
struct regmap *regmap = gpiochip_get_data(c);
|
||||
unsigned int mask = BIT(offset);
|
||||
unsigned int val;
|
||||
int err;
|
||||
|
||||
err = regmap_read(regmap, REG_GPIO_DAT, &val);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return !!(val & mask);
|
||||
}
|
||||
|
||||
static int chip_direction_input(struct gpio_chip *c, unsigned int offset)
|
||||
{
|
||||
struct regmap *regmap = gpiochip_get_data(c);
|
||||
unsigned int mask = BIT(offset);
|
||||
|
||||
return regmap_update_bits(regmap, REG_GPIO_DIR, mask, 0);
|
||||
}
|
||||
|
||||
static int
|
||||
chip_direction_output(struct gpio_chip *c, unsigned int offset, int val)
|
||||
{
|
||||
struct regmap *regmap = gpiochip_get_data(c);
|
||||
unsigned int mask = BIT(offset);
|
||||
|
||||
chip_gpio_set(c, offset, val);
|
||||
return regmap_update_bits(regmap, REG_GPIO_DIR, mask, mask);
|
||||
}
|
||||
|
||||
static const struct gpio_chip template_chip = {
|
||||
.owner = THIS_MODULE,
|
||||
.label = DRV_NAME,
|
||||
|
||||
.base = -1,
|
||||
.ngpio = 14,
|
||||
.direction_input = chip_direction_input,
|
||||
.direction_output = chip_direction_output,
|
||||
.get = chip_gpio_get,
|
||||
.set = chip_gpio_set,
|
||||
|
||||
.can_sleep = true,
|
||||
};
|
||||
|
||||
static int zl38_check_revision(struct device *dev, struct regmap *regmap)
|
||||
{
|
||||
unsigned int hwrev, fwprod, fwrev;
|
||||
int fw_major, fw_minor, fw_micro;
|
||||
int err;
|
||||
|
||||
err = regmap_read(regmap, REG_HW_REV, &hwrev);
|
||||
if (err)
|
||||
return err;
|
||||
err = regmap_read(regmap, REG_FW_PROD, &fwprod);
|
||||
if (err)
|
||||
return err;
|
||||
err = regmap_read(regmap, REG_FW_REV, &fwrev);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
fw_major = (fwrev >> 12) & 0xF;
|
||||
fw_minor = (fwrev >> 8) & 0xF;
|
||||
fw_micro = fwrev & 0xFF;
|
||||
dev_info(dev, "hw rev 0x%x, fw product code %d, firmware rev %d.%d.%d",
|
||||
hwrev & 0x1F, fwprod, fw_major, fw_minor, fw_micro);
|
||||
|
||||
if (fw_major != FIRMWARE_MAJOR || fw_minor < FIRMWARE_MINOR) {
|
||||
dev_err(dev, "unsupported firmware. driver supports %d.%d",
|
||||
FIRMWARE_MAJOR, FIRMWARE_MINOR);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int zl38_bus_read(void *context,
|
||||
const void *reg_buf, size_t reg_size,
|
||||
void *val_buf, size_t val_size)
|
||||
{
|
||||
struct spi_device *spi = context;
|
||||
const u8 *reg_buf8 = reg_buf;
|
||||
size_t len = 0;
|
||||
u8 offs, page;
|
||||
u8 txbuf[4];
|
||||
|
||||
if (reg_size != 2 || val_size > ZL38_MAX_RAW_XFER)
|
||||
return -EINVAL;
|
||||
|
||||
offs = reg_buf8[1] >> 1;
|
||||
page = reg_buf8[0];
|
||||
|
||||
if (page) {
|
||||
txbuf[len++] = 0xFE;
|
||||
txbuf[len++] = page == HBI_FIRMWARE_PAGE ? 0xFF : page - 1;
|
||||
txbuf[len++] = offs;
|
||||
txbuf[len++] = val_size / 2 - 1;
|
||||
} else {
|
||||
txbuf[len++] = offs | 0x80;
|
||||
txbuf[len++] = val_size / 2 - 1;
|
||||
}
|
||||
|
||||
return spi_write_then_read(spi, txbuf, len, val_buf, val_size);
|
||||
}
|
||||
|
||||
static int zl38_bus_write(void *context, const void *data, size_t count)
|
||||
{
|
||||
struct spi_device *spi = context;
|
||||
u8 buf[4 + ZL38_MAX_RAW_XFER];
|
||||
size_t val_len, len = 0;
|
||||
const u8 *data8 = data;
|
||||
u8 offs, page;
|
||||
|
||||
if (count > (2 + ZL38_MAX_RAW_XFER) || count < 4)
|
||||
return -EINVAL;
|
||||
val_len = count - 2;
|
||||
offs = data8[1] >> 1;
|
||||
page = data8[0];
|
||||
|
||||
if (page) {
|
||||
buf[len++] = 0xFE;
|
||||
buf[len++] = page == HBI_FIRMWARE_PAGE ? 0xFF : page - 1;
|
||||
buf[len++] = offs;
|
||||
buf[len++] = (val_len / 2 - 1) | 0x80;
|
||||
} else {
|
||||
buf[len++] = offs | 0x80;
|
||||
buf[len++] = (val_len / 2 - 1) | 0x80;
|
||||
}
|
||||
memcpy(buf + len, data8 + 2, val_len);
|
||||
len += val_len;
|
||||
|
||||
return spi_write(spi, buf, len);
|
||||
}
|
||||
|
||||
static const struct regmap_bus zl38_regmap_bus = {
|
||||
.read = zl38_bus_read,
|
||||
.write = zl38_bus_write,
|
||||
.max_raw_write = ZL38_MAX_RAW_XFER,
|
||||
.max_raw_read = ZL38_MAX_RAW_XFER,
|
||||
};
|
||||
|
||||
static const struct regmap_config zl38_regmap_conf = {
|
||||
.reg_bits = 16,
|
||||
.val_bits = 16,
|
||||
.reg_stride = 2,
|
||||
.use_single_read = true,
|
||||
.use_single_write = true,
|
||||
};
|
||||
|
||||
static int zl38_spi_probe(struct spi_device *spi)
|
||||
{
|
||||
struct device *dev = &spi->dev;
|
||||
struct zl38_codec_priv *priv;
|
||||
struct gpio_desc *reset_gpio;
|
||||
int err;
|
||||
|
||||
/* get the chip to a known state by putting it in reset */
|
||||
reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
|
||||
if (IS_ERR(reset_gpio))
|
||||
return PTR_ERR(reset_gpio);
|
||||
if (reset_gpio) {
|
||||
/* datasheet: need > 10us for a digital + analog reset */
|
||||
usleep_range(15, 50);
|
||||
/* take the chip out of reset */
|
||||
gpiod_set_value_cansleep(reset_gpio, 0);
|
||||
/* datasheet: need > 3ms for digital section to become stable */
|
||||
usleep_range(3000, 10000);
|
||||
}
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->dev = dev;
|
||||
dev_set_drvdata(dev, priv);
|
||||
priv->regmap = devm_regmap_init(dev, &zl38_regmap_bus, spi,
|
||||
&zl38_regmap_conf);
|
||||
if (IS_ERR(priv->regmap))
|
||||
return PTR_ERR(priv->regmap);
|
||||
|
||||
err = zl38_load_firmware(dev, priv->regmap);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = zl38_check_revision(dev, priv->regmap);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
priv->gpio_chip = devm_kmemdup(dev, &template_chip,
|
||||
sizeof(template_chip), GFP_KERNEL);
|
||||
if (!priv->gpio_chip)
|
||||
return -ENOMEM;
|
||||
#ifdef CONFIG_OF_GPIO
|
||||
priv->gpio_chip->of_node = dev->of_node;
|
||||
#endif
|
||||
err = devm_gpiochip_add_data(dev, priv->gpio_chip, priv->regmap);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
/* setup the cross-point switch for stereo bypass */
|
||||
err = regmap_multi_reg_write(priv->regmap, cp_config_stereo_bypass,
|
||||
ARRAY_SIZE(cp_config_stereo_bypass));
|
||||
if (err)
|
||||
return err;
|
||||
/* setup for 12MHz crystal connected to the chip */
|
||||
err = regmap_update_bits(priv->regmap, REG_CLK_CFG, CLK_CFG_SOURCE_XTAL,
|
||||
CLK_CFG_SOURCE_XTAL);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return devm_snd_soc_register_component(dev, &zl38_component_dev,
|
||||
&zl38_dai, 1);
|
||||
}
|
||||
|
||||
static const struct of_device_id zl38_dt_ids[] = {
|
||||
{ .compatible = "mscc,zl38060", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, zl38_dt_ids);
|
||||
|
||||
static const struct spi_device_id zl38_spi_ids[] = {
|
||||
{ "zl38060", 0 },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(spi, zl38_spi_ids);
|
||||
|
||||
static struct spi_driver zl38060_spi_driver = {
|
||||
.driver = {
|
||||
.name = DRV_NAME,
|
||||
.of_match_table = of_match_ptr(zl38_dt_ids),
|
||||
},
|
||||
.probe = zl38_spi_probe,
|
||||
.id_table = zl38_spi_ids,
|
||||
};
|
||||
module_spi_driver(zl38060_spi_driver);
|
||||
|
||||
MODULE_DESCRIPTION("ASoC ZL38060 driver");
|
||||
MODULE_AUTHOR("Sven Van Asbroeck <TheSven73@gmail.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue
Block a user