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bnx2x: Change BCM54616S to BCM54618SE
Change 1G copper PHY BCM54616S to BCM54618SE since we only have HW with latter one of the two. Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -696,7 +696,7 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
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#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00
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#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00
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#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00
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#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00000e00
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#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00
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#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00
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#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
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#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
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@ -751,7 +751,7 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00000e00
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
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@ -3530,7 +3530,7 @@ static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
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vars->flow_ctrl = params->req_fc_auto_adv;
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else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
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ret = 1;
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if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616) {
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if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
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bnx2x_cl22_read(bp, phy,
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0x4, &ld_pause);
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bnx2x_cl22_read(bp, phy,
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@ -5549,7 +5549,7 @@ static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
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u16 cnt, ctrl;
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/* Wait for soft reset to get cleared up to 1 sec */
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for (cnt = 0; cnt < 1000; cnt++) {
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if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616)
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if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
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bnx2x_cl22_read(bp, phy,
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MDIO_PMA_REG_CTRL, &ctrl);
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else
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@ -9800,9 +9800,9 @@ static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
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}
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/******************************************************************/
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/* 54616S PHY SECTION */
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/* 54618SE PHY SECTION */
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/******************************************************************/
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static int bnx2x_54616s_config_init(struct bnx2x_phy *phy,
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static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
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struct link_params *params,
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struct link_vars *vars)
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{
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@ -9811,7 +9811,7 @@ static int bnx2x_54616s_config_init(struct bnx2x_phy *phy,
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u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
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u32 cfg_pin;
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DP(NETIF_MSG_LINK, "54616S cfg init\n");
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DP(NETIF_MSG_LINK, "54618SE cfg init\n");
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usleep_range(1000, 1000);
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/* This works with E3 only, no need to check the chip
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@ -9973,11 +9973,11 @@ static int bnx2x_54616s_config_init(struct bnx2x_phy *phy,
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return 0;
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}
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static void bnx2x_54616s_set_link_led(struct bnx2x_phy *phy,
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struct link_params *params, u8 mode)
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static void bnx2x_54618se_set_link_led(struct bnx2x_phy *phy,
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struct link_params *params, u8 mode)
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{
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struct bnx2x *bp = params->bp;
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DP(NETIF_MSG_LINK, "54616S set link led (mode=%x)\n", mode);
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DP(NETIF_MSG_LINK, "54618SE set link led (mode=%x)\n", mode);
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switch (mode) {
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case LED_MODE_FRONT_PANEL_OFF:
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case LED_MODE_OFF:
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@ -9989,8 +9989,8 @@ static void bnx2x_54616s_set_link_led(struct bnx2x_phy *phy,
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return;
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}
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static void bnx2x_54616s_link_reset(struct bnx2x_phy *phy,
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struct link_params *params)
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static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
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struct link_params *params)
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{
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struct bnx2x *bp = params->bp;
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u32 cfg_pin;
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@ -10009,9 +10009,9 @@ static void bnx2x_54616s_link_reset(struct bnx2x_phy *phy,
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bnx2x_set_cfg_pin(bp, cfg_pin, 0);
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}
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static u8 bnx2x_54616s_read_status(struct bnx2x_phy *phy,
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struct link_params *params,
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struct link_vars *vars)
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static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
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struct link_params *params,
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struct link_vars *vars)
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{
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struct bnx2x *bp = params->bp;
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u16 val;
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@ -10022,7 +10022,7 @@ static u8 bnx2x_54616s_read_status(struct bnx2x_phy *phy,
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bnx2x_cl22_read(bp, phy,
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0x19,
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&legacy_status);
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DP(NETIF_MSG_LINK, "54616S read_status: 0x%x\n", legacy_status);
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DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
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/* Read status to clear the PHY interrupt. */
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bnx2x_cl22_read(bp, phy,
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@ -10074,21 +10074,45 @@ static u8 bnx2x_54616s_read_status(struct bnx2x_phy *phy,
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vars->link_status |=
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LINK_STATUS_PARALLEL_DETECTION_USED;
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DP(NETIF_MSG_LINK, "BCM54616S: link speed is %d\n",
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DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
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vars->line_speed);
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/* Report whether EEE is resolved. */
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bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &val);
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if (val == MDIO_REG_GPHY_ID_54618SE) {
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if (vars->link_status &
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LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
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val = 0;
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else {
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bnx2x_cl22_write(bp, phy,
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MDIO_REG_GPHY_CL45_ADDR_REG,
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MDIO_AN_DEVAD);
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bnx2x_cl22_write(bp, phy,
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MDIO_REG_GPHY_CL45_DATA_REG,
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MDIO_REG_GPHY_EEE_RESOLVED);
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bnx2x_cl22_write(bp, phy,
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MDIO_REG_GPHY_CL45_ADDR_REG,
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(0x1 << 14) | MDIO_AN_DEVAD);
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bnx2x_cl22_read(bp, phy,
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MDIO_REG_GPHY_CL45_DATA_REG,
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&val);
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}
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DP(NETIF_MSG_LINK, "EEE resolution: 0x%x\n", val);
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}
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bnx2x_ext_phy_resolve_fc(phy, params, vars);
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}
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return link_up;
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}
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static void bnx2x_54616s_config_loopback(struct bnx2x_phy *phy,
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struct link_params *params)
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static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
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struct link_params *params)
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{
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struct bnx2x *bp = params->bp;
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u16 val;
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u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
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DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54616s\n");
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DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
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/* Enable master/slave manual mmode and set to master */
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/* mii write 9 [bits set 11 12] */
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@ -10705,8 +10729,8 @@ static struct bnx2x_phy phy_84833 = {
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.phy_specific_func = (phy_specific_func_t)NULL
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};
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static struct bnx2x_phy phy_54616s = {
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.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616,
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static struct bnx2x_phy phy_54618se = {
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.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
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.addr = 0xff,
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.def_md_devad = 0,
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.flags = FLAGS_INIT_XGXS_FIRST,
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@ -10729,13 +10753,13 @@ static struct bnx2x_phy phy_54616s = {
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.speed_cap_mask = 0,
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/* req_duplex = */0,
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/* rsrv = */0,
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.config_init = (config_init_t)bnx2x_54616s_config_init,
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.read_status = (read_status_t)bnx2x_54616s_read_status,
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.link_reset = (link_reset_t)bnx2x_54616s_link_reset,
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.config_loopback = (config_loopback_t)bnx2x_54616s_config_loopback,
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.config_init = (config_init_t)bnx2x_54618se_config_init,
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.read_status = (read_status_t)bnx2x_54618se_read_status,
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.link_reset = (link_reset_t)bnx2x_54618se_link_reset,
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.config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
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.format_fw_ver = (format_fw_ver_t)NULL,
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.hw_reset = (hw_reset_t)NULL,
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.set_link_led = (set_link_led_t)bnx2x_54616s_set_link_led,
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.set_link_led = (set_link_led_t)bnx2x_54618se_set_link_led,
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.phy_specific_func = (phy_specific_func_t)NULL
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};
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/*****************************************************************/
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@ -10978,8 +11002,8 @@ static int bnx2x_populate_ext_phy(struct bnx2x *bp,
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
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*phy = phy_84833;
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break;
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
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*phy = phy_54616s;
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
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*phy = phy_54618se;
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break;
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
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*phy = phy_7101;
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@ -6919,7 +6919,15 @@ Theotherbitsarereservedandshouldbezero*/
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#define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
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/* 54616s */
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/* 54618se */
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#define MDIO_REG_GPHY_PHYID_LSB 0x3
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#define MDIO_REG_GPHY_ID_54618SE 0x5cd5
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#define MDIO_REG_GPHY_CL45_ADDR_REG 0xd
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#define MDIO_REG_GPHY_CL45_DATA_REG 0xe
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#define MDIO_REG_GPHY_EEE_ADV 0x3c
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#define MDIO_REG_GPHY_EEE_1G (0x1 << 2)
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#define MDIO_REG_GPHY_EEE_100 (0x1 << 1)
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#define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
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#define MDIO_REG_INTR_STATUS 0x1a
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#define MDIO_REG_INTR_MASK 0x1b
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#define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
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