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riscv, bpf: Optimize sign-extention mov insns with Zbb support

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Add 8-bit and 16-bit sign-extention wraper with Zbb support to optimize
sign-extension mov instructions.

Signed-off-by: Pu Lehui <pulehui@huawei.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Tested-by: Björn Töpel <bjorn@rivosinc.com>
Acked-by: Björn Töpel <bjorn@kernel.org>
Link: https://lore.kernel.org/bpf/20240115131235.2914289-6-pulehui@huaweicloud.com
This commit is contained in:
Pu Lehui 2024-01-15 13:12:34 +00:00 committed by Daniel Borkmann
parent 647b93f65d
commit 519fb722be
2 changed files with 25 additions and 2 deletions
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22
arch/riscv/net/bpf_jit.h
View File

@ -1119,6 +1119,28 @@ static inline void emit_subw(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx)
emit(rv_subw(rd, rs1, rs2), ctx);
}
static inline void emit_sextb(u8 rd, u8 rs, struct rv_jit_context *ctx)
{
if (rvzbb_enabled()) {
emit(rvzbb_sextb(rd, rs), ctx);
return;
}
emit_slli(rd, rs, 56, ctx);
emit_srai(rd, rd, 56, ctx);
}
static inline void emit_sexth(u8 rd, u8 rs, struct rv_jit_context *ctx)
{
if (rvzbb_enabled()) {
emit(rvzbb_sexth(rd, rs), ctx);
return;
}
emit_slli(rd, rs, 48, ctx);
emit_srai(rd, rd, 48, ctx);
}
static inline void emit_sextw(u8 rd, u8 rs, struct rv_jit_context *ctx)
{
emit_addiw(rd, rs, 0, ctx);

5
arch/riscv/net/bpf_jit_comp64.c
View File

@ -1074,9 +1074,10 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
emit_mv(rd, rs, ctx);
break;
case 8:
emit_sextb(rd, rs, ctx);
break;
case 16:
emit_slli(RV_REG_T1, rs, 64 - insn->off, ctx);
emit_srai(rd, RV_REG_T1, 64 - insn->off, ctx);
emit_sexth(rd, rs, ctx);
break;
case 32:
emit_sextw(rd, rs, ctx);