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- Reserve enough fence slot for i915_vma_unbind_vsync (Nirmoy)
- Fix potential use after free (Rob Clark) - Reset engines twice in case of reset failure (Chris) - Use multi-cast registers for SVG Unit registers (Gustavo) -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEbSBwaO7dZQkcLOKj+mJfZA7rE8oFAmPAGrUACgkQ+mJfZA7r E8rPowgAv98f3wHkok+Dfv4EQsFcANfpuJiJiXmsoIhrsEevaqvV8gBdMHKpqkC3 eKIqLXnOFprfrGq0AiM/ZZL3kZtJnxWFuhTv+rsyI0CUtIMER1GAzh8yISQF2TL4 1oHIEfXZSModvFEOqYFrVd4WFZ+1WOTQOHiUOHQMvxHeLhIJfapcJfC/oucUhYaT 9ywxZPZ+Ph9mFD4dVIoVIoKAApNoTLkStCZH4eIx8SqIE/qfu/5BBXsa8eBMVyXC 4/YsY5QKlUApM63Z0c/8C3w6P6uYieraK3GsyaIt3qTHmhXXp0pYFE1YtdA0okUb YdUOgYbdTM3Q/ej5UBkllJzxr6ygGw== =r216 -----END PGP SIGNATURE----- Merge tag 'drm-intel-fixes-2023-01-12' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes - Reserve enough fence slot for i915_vma_unbind_vsync (Nirmoy) - Fix potential use after free (Rob Clark) - Reset engines twice in case of reset failure (Chris) - Use multi-cast registers for SVG Unit registers (Gustavo) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/Y8AbHelGeXc5eQ8U@intel.com
This commit is contained in:
Dave Airlie
commit
51883883ac
@ -1688,6 +1688,10 @@ void i915_gem_init__contexts(struct drm_i915_private *i915)
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init_contexts(&i915->gem.contexts);
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}
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/*
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* Note that this implicitly consumes the ctx reference, by placing
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* the ctx in the context_xa.
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*/
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static void gem_context_register(struct i915_gem_context *ctx,
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struct drm_i915_file_private *fpriv,
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u32 id)
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@ -1703,10 +1707,6 @@ static void gem_context_register(struct i915_gem_context *ctx,
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snprintf(ctx->name, sizeof(ctx->name), "%s[%d]",
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current->comm, pid_nr(ctx->pid));
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/* And finally expose ourselves to userspace via the idr */
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old = xa_store(&fpriv->context_xa, id, ctx, GFP_KERNEL);
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WARN_ON(old);
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spin_lock(&ctx->client->ctx_lock);
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list_add_tail_rcu(&ctx->client_link, &ctx->client->ctx_list);
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spin_unlock(&ctx->client->ctx_lock);
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@ -1714,6 +1714,10 @@ static void gem_context_register(struct i915_gem_context *ctx,
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spin_lock(&i915->gem.contexts.lock);
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list_add_tail(&ctx->link, &i915->gem.contexts.list);
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spin_unlock(&i915->gem.contexts.lock);
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/* And finally expose ourselves to userspace via the idr */
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old = xa_store(&fpriv->context_xa, id, ctx, GFP_KERNEL);
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WARN_ON(old);
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}
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int i915_gem_context_open(struct drm_i915_private *i915,
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@ -2199,14 +2203,22 @@ finalize_create_context_locked(struct drm_i915_file_private *file_priv,
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if (IS_ERR(ctx))
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return ctx;
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/*
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* One for the xarray and one for the caller. We need to grab
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* the reference *prior* to making the ctx visble to userspace
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* in gem_context_register(), as at any point after that
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* userspace can try to race us with another thread destroying
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* the context under our feet.
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*/
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i915_gem_context_get(ctx);
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gem_context_register(ctx, file_priv, id);
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old = xa_erase(&file_priv->proto_context_xa, id);
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GEM_BUG_ON(old != pc);
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proto_context_close(file_priv->dev_priv, pc);
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/* One for the xarray and one for the caller */
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return i915_gem_context_get(ctx);
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return ctx;
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}
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struct i915_gem_context *
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@ -406,10 +406,10 @@
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#define GEN9_WM_CHICKEN3 _MMIO(0x5588)
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#define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9)
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#define CHICKEN_RASTER_1 _MMIO(0x6204)
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#define CHICKEN_RASTER_1 MCR_REG(0x6204)
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#define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8)
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#define CHICKEN_RASTER_2 _MMIO(0x6208)
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#define CHICKEN_RASTER_2 MCR_REG(0x6208)
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#define TBIMR_FAST_CLIP REG_BIT(5)
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#define VFLSKPD MCR_REG(0x62a8)
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@ -278,6 +278,7 @@ out:
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static int gen6_hw_domain_reset(struct intel_gt *gt, u32 hw_domain_mask)
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{
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struct intel_uncore *uncore = gt->uncore;
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int loops = 2;
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int err;
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/*
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@ -285,18 +286,39 @@ static int gen6_hw_domain_reset(struct intel_gt *gt, u32 hw_domain_mask)
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* for fifo space for the write or forcewake the chip for
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* the read
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*/
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intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask);
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do {
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intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask);
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/* Wait for the device to ack the reset requests */
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err = __intel_wait_for_register_fw(uncore,
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GEN6_GDRST, hw_domain_mask, 0,
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500, 0,
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NULL);
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/*
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* Wait for the device to ack the reset requests.
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*
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* On some platforms, e.g. Jasperlake, we see that the
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* engine register state is not cleared until shortly after
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* GDRST reports completion, causing a failure as we try
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* to immediately resume while the internal state is still
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* in flux. If we immediately repeat the reset, the second
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* reset appears to serialise with the first, and since
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* it is a no-op, the registers should retain their reset
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* value. However, there is still a concern that upon
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* leaving the second reset, the internal engine state
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* is still in flux and not ready for resuming.
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*/
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err = __intel_wait_for_register_fw(uncore, GEN6_GDRST,
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hw_domain_mask, 0,
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2000, 0,
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NULL);
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} while (err == 0 && --loops);
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if (err)
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GT_TRACE(gt,
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"Wait for 0x%08x engines reset failed\n",
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hw_domain_mask);
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/*
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* As we have observed that the engine state is still volatile
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* after GDRST is acked, impose a small delay to let everything settle.
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*/
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udelay(50);
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return err;
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}
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@ -645,7 +645,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
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static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine,
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struct i915_wa_list *wal)
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{
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wa_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP);
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wa_mcr_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP);
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wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
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REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
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wa_mcr_add(wal,
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@ -775,7 +775,7 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
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wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000);
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/* Wa_15010599737:dg2 */
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wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);
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wa_mcr_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);
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}
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static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
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@ -2116,7 +2116,7 @@ int i915_vma_unbind_async(struct i915_vma *vma, bool trylock_vm)
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if (!obj->mm.rsgt)
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return -EBUSY;
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err = dma_resv_reserve_fences(obj->base.resv, 1);
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err = dma_resv_reserve_fences(obj->base.resv, 2);
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if (err)
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return -EBUSY;
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