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hwmon: (max31827) Add PEC support

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Add PEC support using the hwmon core infrastructure.

Signed-off-by: Radu Sabau <radu.sabau@analog.com>
Reviewed-by: Nuno Sa <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20240531084645.12935-2-radu.sabau@analog.com
[groeck: Adjusted subject; simplified description]
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
This commit is contained in:
Radu Sabau 2024-05-31 11:46:44 +03:00 committed by Guenter Roeck
parent fcbb583f33
commit 5124d9acf3
2 changed files with 22 additions and 9 deletions
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13
Documentation/hwmon/max31827.rst
View File

@ -131,7 +131,14 @@ The Fault Queue bits select how many consecutive temperature faults must occur
before overtemperature or undertemperature faults are indicated in the
corresponding status bits.
Notes
-----
PEC Support
-----------
PEC is not implemented.
When reading a register value, the PEC byte is computed and sent by the chip.
PEC on word data transaction respresents a signifcant increase in bandwitdh
usage (+33% for both write and reads) in normal conditions.
Since this operation implies there will be an extra delay to each
transaction, PEC can be disabled or enabled through sysfs.
Just write 1 to the "pec" file for enabling PEC and 0 for disabling it.

18
drivers/hwmon/max31827.c
View File

@ -24,6 +24,7 @@
#define MAX31827_CONFIGURATION_1SHOT_MASK BIT(0)
#define MAX31827_CONFIGURATION_CNV_RATE_MASK GENMASK(3, 1)
#define MAX31827_CONFIGURATION_PEC_EN_MASK BIT(4)
#define MAX31827_CONFIGURATION_TIMEOUT_MASK BIT(5)
#define MAX31827_CONFIGURATION_RESOLUTION_MASK GENMASK(7, 6)
#define MAX31827_CONFIGURATION_ALRM_POL_MASK BIT(8)
@ -382,7 +383,8 @@ static int max31827_write(struct device *dev, enum hwmon_sensor_types type,
}
case hwmon_chip:
if (attr == hwmon_chip_update_interval) {
switch (attr) {
case hwmon_chip_update_interval:
if (!st->enable)
return -EINVAL;
@ -410,14 +412,18 @@ static int max31827_write(struct device *dev, enum hwmon_sensor_types type,
return ret;
st->update_interval = val;
}
break;
return 0;
case hwmon_chip_pec:
return regmap_update_bits(st->regmap, MAX31827_CONFIGURATION_REG,
MAX31827_CONFIGURATION_PEC_EN_MASK,
val ? MAX31827_CONFIGURATION_PEC_EN_MASK : 0);
default:
return -EOPNOTSUPP;
}
default:
return -EOPNOTSUPP;
}
return 0;
}
static ssize_t temp1_resolution_show(struct device *dev,
@ -583,7 +589,7 @@ static const struct hwmon_channel_info *max31827_info[] = {
HWMON_T_MIN_HYST | HWMON_T_MIN_ALARM |
HWMON_T_MAX | HWMON_T_MAX_HYST |
HWMON_T_MAX_ALARM),
HWMON_CHANNEL_INFO(chip, HWMON_C_UPDATE_INTERVAL),
HWMON_CHANNEL_INFO(chip, HWMON_C_UPDATE_INTERVAL | HWMON_C_PEC),
NULL,
};