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tg3: APE heartbeat changes
In ungraceful host shutdown or driver crash case BMC connectivity is lost. APE firmware is missing the driver state in this case to keep the BMC connectivity alive. This patch has below change to address this issue. Heartbeat mechanism with APE firmware. This heartbeat mechanism is needed to notify the APE firmware about driver state. This patch also has the change in wait time for APE event from 1ms to 20ms as there can be some delay in getting response. v2: Drop inline keyword as per David suggestion. Signed-off-by: Prashant Sreedharan <prashant.sreedharan@broadcom.com> Signed-off-by: Satish Baddipadige <satish.baddipadige@broadcom.com> Signed-off-by: Siva Reddy Kallam <siva.kallam@broadcom.com> Acked-by: Michael Chan <michael.chan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -820,7 +820,7 @@ static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
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tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
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udelay(10);
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usleep_range(10, 20);
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timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
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}
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@ -922,8 +922,8 @@ static int tg3_ape_send_event(struct tg3 *tp, u32 event)
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if (!(apedata & APE_FW_STATUS_READY))
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return -EAGAIN;
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/* Wait for up to 1 millisecond for APE to service previous event. */
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err = tg3_ape_event_lock(tp, 1000);
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/* Wait for up to 20 millisecond for APE to service previous event. */
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err = tg3_ape_event_lock(tp, 20000);
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if (err)
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return err;
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@ -946,6 +946,7 @@ static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
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switch (kind) {
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case RESET_KIND_INIT:
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tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);
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tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
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APE_HOST_SEG_SIG_MAGIC);
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tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
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@ -962,13 +963,6 @@ static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
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event = APE_EVENT_STATUS_STATE_START;
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break;
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case RESET_KIND_SHUTDOWN:
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/* With the interface we are currently using,
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* APE does not track driver state. Wiping
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* out the HOST SEGMENT SIGNATURE forces
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* the APE to assume OS absent status.
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*/
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tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
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if (device_may_wakeup(&tp->pdev->dev) &&
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tg3_flag(tp, WOL_ENABLE)) {
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tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
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@ -990,6 +984,18 @@ static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
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tg3_ape_send_event(tp, event);
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}
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static void tg3_send_ape_heartbeat(struct tg3 *tp,
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unsigned long interval)
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{
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/* Check if hb interval has exceeded */
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if (!tg3_flag(tp, ENABLE_APE) ||
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time_before(jiffies, tp->ape_hb_jiffies + interval))
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return;
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tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);
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tp->ape_hb_jiffies = jiffies;
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}
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static void tg3_disable_ints(struct tg3 *tp)
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{
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int i;
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@ -7262,6 +7268,7 @@ static int tg3_poll_msix(struct napi_struct *napi, int budget)
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}
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}
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tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1);
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return work_done;
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tx_recovery:
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@ -7344,6 +7351,7 @@ static int tg3_poll(struct napi_struct *napi, int budget)
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}
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}
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tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1);
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return work_done;
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tx_recovery:
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@ -10732,7 +10740,7 @@ static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
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if (tg3_flag(tp, ENABLE_APE))
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/* Write our heartbeat update interval to APE. */
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tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
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APE_HOST_HEARTBEAT_INT_DISABLE);
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APE_HOST_HEARTBEAT_INT_5SEC);
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tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
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@ -11077,6 +11085,9 @@ static void tg3_timer(struct timer_list *t)
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tp->asf_counter = tp->asf_multiplier;
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}
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/* Update the APE heartbeat every 5 seconds.*/
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tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL);
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spin_unlock(&tp->lock);
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restart_timer:
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@ -16653,6 +16664,8 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
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pci_state_reg);
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tg3_ape_lock_init(tp);
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tp->ape_hb_interval =
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msecs_to_jiffies(APE_HOST_HEARTBEAT_INT_5SEC);
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}
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/* Set up tp->grc_local_ctrl before calling
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@ -2508,6 +2508,7 @@
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#define TG3_APE_LOCK_PHY3 5
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#define TG3_APE_LOCK_GPIO 7
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#define TG3_APE_HB_INTERVAL (tp->ape_hb_interval)
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#define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
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@ -3423,6 +3424,10 @@ struct tg3 {
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struct device *hwmon_dev;
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bool link_up;
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bool pcierr_recovery;
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u32 ape_hb;
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unsigned long ape_hb_interval;
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unsigned long ape_hb_jiffies;
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};
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/* Accessor macros for chip and asic attributes
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