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usb: gadget: remove langwell_udc
We have the chipidea driver now that supports both langwell and penwell, so there is no need for this one any more. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Alexander Shishkin
Greg Kroah-Hartman
parent
ab3999a261
commit
4fd09e8e02
@ -431,22 +431,6 @@ config USB_GOKU
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dynamically linked module called "goku_udc" and to force all
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gadget drivers to also be dynamically linked.
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config USB_LANGWELL
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tristate "Intel Langwell USB Device Controller"
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depends on PCI
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depends on !PHYS_ADDR_T_64BIT
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select USB_GADGET_DUALSPEED
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help
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Intel Langwell USB Device Controller is a High-Speed USB
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On-The-Go device controller.
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The number of programmable endpoints is different through
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controller revision.
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Say "y" to link the driver statically, or "m" to build a
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dynamically linked module called "langwell_udc" and force all
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gadget drivers to also be dynamically linked.
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config USB_EG20T
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tristate "Intel EG20T PCH/LAPIS Semiconductor IOH(ML7213/ML7831) UDC"
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depends on PCI
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@ -24,7 +24,6 @@ obj-$(CONFIG_USB_R8A66597) += r8a66597-udc.o
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obj-$(CONFIG_USB_FSL_QE) += fsl_qe_udc.o
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obj-$(CONFIG_USB_S3C_HSOTG) += s3c-hsotg.o
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obj-$(CONFIG_USB_S3C_HSUDC) += s3c-hsudc.o
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obj-$(CONFIG_USB_LANGWELL) += langwell_udc.o
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obj-$(CONFIG_USB_LPC32XX) += lpc32xx_udc.o
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obj-$(CONFIG_USB_EG20T) += pch_udc.o
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obj-$(CONFIG_USB_MV_UDC) += mv_udc.o
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File diff suppressed because it is too large
Load Diff
@ -1,223 +0,0 @@
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/*
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* Intel Langwell USB Device Controller driver
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* Copyright (C) 2008-2009, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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#include <linux/usb/langwell_udc.h>
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/*-------------------------------------------------------------------------*/
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/* driver data structures and utilities */
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/*
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* dTD: Device Endpoint Transfer Descriptor
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* describe to the device controller the location and quantity of
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* data to be send/received for given transfer
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*/
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struct langwell_dtd {
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u32 dtd_next;
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/* bits 31:5, next transfer element pointer */
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#define DTD_NEXT(d) (((d)>>5)&0x7ffffff)
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#define DTD_NEXT_MASK (0x7ffffff << 5)
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/* terminate */
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#define DTD_TERM BIT(0)
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/* bits 7:0, execution back states */
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u32 dtd_status:8;
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#define DTD_STATUS(d) (((d)>>0)&0xff)
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#define DTD_STS_ACTIVE BIT(7) /* active */
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#define DTD_STS_HALTED BIT(6) /* halted */
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#define DTD_STS_DBE BIT(5) /* data buffer error */
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#define DTD_STS_TRE BIT(3) /* transaction error */
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/* bits 9:8 */
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u32 dtd_res0:2;
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/* bits 11:10, multipier override */
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u32 dtd_multo:2;
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#define DTD_MULTO (BIT(11) | BIT(10))
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/* bits 14:12 */
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u32 dtd_res1:3;
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/* bit 15, interrupt on complete */
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u32 dtd_ioc:1;
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#define DTD_IOC BIT(15)
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/* bits 30:16, total bytes */
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u32 dtd_total:15;
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#define DTD_TOTAL(d) (((d)>>16)&0x7fff)
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#define DTD_MAX_TRANSFER_LENGTH 0x4000
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/* bit 31 */
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u32 dtd_res2:1;
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/* dTD buffer pointer page 0 to 4 */
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u32 dtd_buf[5];
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#define DTD_OFFSET_MASK 0xfff
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/* bits 31:12, buffer pointer */
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#define DTD_BUFFER(d) (((d)>>12)&0x3ff)
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/* bits 11:0, current offset */
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#define DTD_C_OFFSET(d) (((d)>>0)&0xfff)
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/* bits 10:0, frame number */
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#define DTD_FRAME(d) (((d)>>0)&0x7ff)
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/* driver-private parts */
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/* dtd dma address */
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dma_addr_t dtd_dma;
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/* next dtd virtual address */
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struct langwell_dtd *next_dtd_virt;
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};
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/*
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* dQH: Device Endpoint Queue Head
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* describe where all transfers are managed
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* 48-byte data structure, aligned on 64-byte boundary
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*
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* These are associated with dTD structure
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*/
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struct langwell_dqh {
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/* endpoint capabilities and characteristics */
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u32 dqh_res0:15; /* bits 14:0 */
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u32 dqh_ios:1; /* bit 15, interrupt on setup */
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#define DQH_IOS BIT(15)
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u32 dqh_mpl:11; /* bits 26:16, maximum packet length */
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#define DQH_MPL (0x7ff << 16)
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u32 dqh_res1:2; /* bits 28:27 */
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u32 dqh_zlt:1; /* bit 29, zero length termination */
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#define DQH_ZLT BIT(29)
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u32 dqh_mult:2; /* bits 31:30 */
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#define DQH_MULT (BIT(30) | BIT(31))
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/* current dTD pointer */
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u32 dqh_current; /* locate the transfer in progress */
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#define DQH_C_DTD(e) \
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(((e)>>5)&0x7ffffff) /* bits 31:5, current dTD pointer */
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/* transfer overlay, hardware parts of a struct langwell_dtd */
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u32 dtd_next;
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u32 dtd_status:8; /* bits 7:0, execution back states */
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u32 dtd_res0:2; /* bits 9:8 */
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u32 dtd_multo:2; /* bits 11:10, multipier override */
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u32 dtd_res1:3; /* bits 14:12 */
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u32 dtd_ioc:1; /* bit 15, interrupt on complete */
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u32 dtd_total:15; /* bits 30:16, total bytes */
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u32 dtd_res2:1; /* bit 31 */
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u32 dtd_buf[5]; /* dTD buffer pointer page 0 to 4 */
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u32 dqh_res2;
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struct usb_ctrlrequest dqh_setup; /* setup packet buffer */
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} __attribute__ ((aligned(64)));
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/* endpoint data structure */
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struct langwell_ep {
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struct usb_ep ep;
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dma_addr_t dma;
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struct langwell_udc *dev;
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unsigned long irqs;
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struct list_head queue;
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struct langwell_dqh *dqh;
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char name[14];
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unsigned stopped:1,
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ep_type:2,
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ep_num:8;
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};
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/* request data structure */
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struct langwell_request {
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struct usb_request req;
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struct langwell_dtd *dtd, *head, *tail;
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struct langwell_ep *ep;
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dma_addr_t dtd_dma;
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struct list_head queue;
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unsigned dtd_count;
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unsigned mapped:1;
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};
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/* ep0 transfer state */
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enum ep0_state {
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WAIT_FOR_SETUP,
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DATA_STATE_XMIT,
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DATA_STATE_NEED_ZLP,
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WAIT_FOR_OUT_STATUS,
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DATA_STATE_RECV,
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};
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/* device suspend state */
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enum lpm_state {
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LPM_L0, /* on */
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LPM_L1, /* LPM L1 sleep */
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LPM_L2, /* suspend */
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LPM_L3, /* off */
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};
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/* device data structure */
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struct langwell_udc {
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/* each pci device provides one gadget, several endpoints */
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struct usb_gadget gadget;
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spinlock_t lock; /* device lock */
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struct langwell_ep *ep;
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struct usb_gadget_driver *driver;
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struct usb_phy *transceiver;
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u8 dev_addr;
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u32 usb_state;
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u32 resume_state;
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u32 bus_reset;
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enum lpm_state lpm_state;
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enum ep0_state ep0_state;
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u32 ep0_dir;
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u16 dciversion;
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unsigned ep_max;
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unsigned devcap:1,
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enabled:1,
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region:1,
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got_irq:1,
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powered:1,
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remote_wakeup:1,
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rate:1,
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is_reset:1,
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softconnected:1,
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vbus_active:1,
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suspended:1,
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stopped:1,
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lpm:1, /* LPM capability */
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has_sram:1, /* SRAM caching */
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got_sram:1;
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/* pci state used to access those endpoints */
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struct pci_dev *pdev;
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/* Langwell otg transceiver */
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struct langwell_otg *lotg;
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/* control registers */
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struct langwell_cap_regs __iomem *cap_regs;
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struct langwell_op_regs __iomem *op_regs;
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struct usb_ctrlrequest local_setup_buff;
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struct langwell_dqh *ep_dqh;
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size_t ep_dqh_size;
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dma_addr_t ep_dqh_dma;
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/* ep0 status request */
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struct langwell_request *status_req;
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/* dma pool */
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struct dma_pool *dtd_pool;
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/* make sure release() is done */
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struct completion *done;
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/* for private SRAM caching */
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unsigned int sram_addr;
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unsigned int sram_size;
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/* device status data for get_status request */
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u16 dev_status;
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};
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#define gadget_to_langwell(g) container_of((g), struct langwell_udc, gadget)
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@ -1,310 +0,0 @@
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/*
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* Intel Langwell USB Device Controller driver
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* Copyright (C) 2008-2009, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#ifndef __LANGWELL_UDC_H
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#define __LANGWELL_UDC_H
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/* MACRO defines */
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#define CAP_REG_OFFSET 0x0
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#define OP_REG_OFFSET 0x28
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#define DMA_ADDR_INVALID (~(dma_addr_t)0)
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#define DQH_ALIGNMENT 2048
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#define DTD_ALIGNMENT 64
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#define DMA_BOUNDARY 4096
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#define EP0_MAX_PKT_SIZE 64
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#define EP_DIR_IN 1
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#define EP_DIR_OUT 0
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#define FLUSH_TIMEOUT 1000
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#define RESET_TIMEOUT 1000
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#define SETUPSTAT_TIMEOUT 100
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#define PRIME_TIMEOUT 100
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/* device memory space registers */
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/* Capability Registers, BAR0 + CAP_REG_OFFSET */
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struct langwell_cap_regs {
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/* offset: 0x0 */
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u8 caplength; /* offset of Operational Register */
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u8 _reserved3;
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u16 hciversion; /* H: BCD encoding of host version */
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u32 hcsparams; /* H: host port steering logic capability */
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u32 hccparams; /* H: host multiple mode control capability */
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#define HCC_LEN BIT(17) /* Link power management (LPM) capability */
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u8 _reserved4[0x20-0xc];
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/* offset: 0x20 */
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u16 dciversion; /* BCD encoding of device version */
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u8 _reserved5[0x24-0x22];
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u32 dccparams; /* overall device controller capability */
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#define HOSTCAP BIT(8) /* host capable */
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#define DEVCAP BIT(7) /* device capable */
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#define DEN(d) \
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(((d)>>0)&0x1f) /* bits 4:0, device endpoint number */
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} __attribute__ ((packed));
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/* Operational Registers, BAR0 + OP_REG_OFFSET */
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struct langwell_op_regs {
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/* offset: 0x28 */
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u32 extsts;
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#define EXTS_TI1 BIT(4) /* general purpose timer interrupt 1 */
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#define EXTS_TI1TI0 BIT(3) /* general purpose timer interrupt 0 */
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#define EXTS_TI1UPI BIT(2) /* USB host periodic interrupt */
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#define EXTS_TI1UAI BIT(1) /* USB host asynchronous interrupt */
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#define EXTS_TI1NAKI BIT(0) /* NAK interrupt */
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u32 extintr;
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#define EXTI_TIE1 BIT(4) /* general purpose timer interrupt enable 1 */
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#define EXTI_TIE0 BIT(3) /* general purpose timer interrupt enable 0 */
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#define EXTI_UPIE BIT(2) /* USB host periodic interrupt enable */
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#define EXTI_UAIE BIT(1) /* USB host asynchronous interrupt enable */
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#define EXTI_NAKE BIT(0) /* NAK interrupt enable */
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/* offset: 0x30 */
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u32 usbcmd;
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#define CMD_HIRD(u) \
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(((u)>>24)&0xf) /* bits 27:24, host init resume duration */
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#define CMD_ITC(u) \
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(((u)>>16)&0xff) /* bits 23:16, interrupt threshold control */
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#define CMD_PPE BIT(15) /* per-port change events enable */
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#define CMD_ATDTW BIT(14) /* add dTD tripwire */
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#define CMD_SUTW BIT(13) /* setup tripwire */
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#define CMD_ASPE BIT(11) /* asynchronous schedule park mode enable */
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#define CMD_FS2 BIT(10) /* frame list size */
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#define CMD_ASP1 BIT(9) /* asynchronous schedule park mode count */
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#define CMD_ASP0 BIT(8)
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#define CMD_LR BIT(7) /* light host/device controller reset */
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#define CMD_IAA BIT(6) /* interrupt on async advance doorbell */
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#define CMD_ASE BIT(5) /* asynchronous schedule enable */
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#define CMD_PSE BIT(4) /* periodic schedule enable */
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#define CMD_FS1 BIT(3)
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#define CMD_FS0 BIT(2)
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#define CMD_RST BIT(1) /* controller reset */
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#define CMD_RUNSTOP BIT(0) /* run/stop */
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u32 usbsts;
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#define STS_PPCI(u) \
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(((u)>>16)&0xffff) /* bits 31:16, port-n change detect */
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#define STS_AS BIT(15) /* asynchronous schedule status */
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#define STS_PS BIT(14) /* periodic schedule status */
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#define STS_RCL BIT(13) /* reclamation */
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#define STS_HCH BIT(12) /* HC halted */
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#define STS_ULPII BIT(10) /* ULPI interrupt */
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#define STS_SLI BIT(8) /* DC suspend */
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#define STS_SRI BIT(7) /* SOF received */
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#define STS_URI BIT(6) /* USB reset received */
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#define STS_AAI BIT(5) /* interrupt on async advance */
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#define STS_SEI BIT(4) /* system error */
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#define STS_FRI BIT(3) /* frame list rollover */
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#define STS_PCI BIT(2) /* port change detect */
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#define STS_UEI BIT(1) /* USB error interrupt */
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#define STS_UI BIT(0) /* USB interrupt */
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u32 usbintr;
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/* bits 31:16, per-port interrupt enable */
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#define INTR_PPCE(u) (((u)>>16)&0xffff)
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#define INTR_ULPIE BIT(10) /* ULPI enable */
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#define INTR_SLE BIT(8) /* DC sleep/suspend enable */
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#define INTR_SRE BIT(7) /* SOF received enable */
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#define INTR_URE BIT(6) /* USB reset enable */
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#define INTR_AAE BIT(5) /* interrupt on async advance enable */
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#define INTR_SEE BIT(4) /* system error enable */
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#define INTR_FRE BIT(3) /* frame list rollover enable */
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#define INTR_PCE BIT(2) /* port change detect enable */
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#define INTR_UEE BIT(1) /* USB error interrupt enable */
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#define INTR_UE BIT(0) /* USB interrupt enable */
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u32 frindex; /* frame index */
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#define FRINDEX_MASK (0x3fff << 0)
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u32 ctrldssegment; /* not used */
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u32 deviceaddr;
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#define USBADR_SHIFT 25
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#define USBADR(d) \
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(((d)>>25)&0x7f) /* bits 31:25, device address */
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#define USBADR_MASK (0x7f << 25)
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#define USBADRA BIT(24) /* device address advance */
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u32 endpointlistaddr;/* endpoint list top memory address */
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/* bits 31:11, endpoint list pointer */
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#define EPBASE(d) (((d)>>11)&0x1fffff)
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#define ENDPOINTLISTADDR_MASK (0x1fffff << 11)
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u32 ttctrl; /* H: TT operatin, not used */
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/* offset: 0x50 */
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u32 burstsize; /* burst size of data movement */
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#define TXPBURST(b) \
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(((b)>>8)&0xff) /* bits 15:8, TX burst length */
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#define RXPBURST(b) \
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(((b)>>0)&0xff) /* bits 7:0, RX burst length */
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u32 txfilltuning; /* TX tuning */
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u32 txttfilltuning; /* H: TX TT tuning */
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u32 ic_usb; /* control the IC_USB FS/LS transceiver */
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/* offset: 0x60 */
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u32 ulpi_viewport; /* indirect access to ULPI PHY */
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#define ULPIWU BIT(31) /* ULPI wakeup */
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#define ULPIRUN BIT(30) /* ULPI read/write run */
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#define ULPIRW BIT(29) /* ULPI read/write control */
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#define ULPISS BIT(27) /* ULPI sync state */
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#define ULPIPORT(u) \
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(((u)>>24)&7) /* bits 26:24, ULPI port number */
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#define ULPIADDR(u) \
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(((u)>>16)&0xff) /* bits 23:16, ULPI data address */
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#define ULPIDATRD(u) \
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(((u)>>8)&0xff) /* bits 15:8, ULPI data read */
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#define ULPIDATWR(u) \
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(((u)>>0)&0xff) /* bits 7:0, ULPI date write */
|
||||
u8 _reserved6[0x70-0x64];
|
||||
/* offset: 0x70 */
|
||||
u32 configflag; /* H: not used */
|
||||
u32 portsc1; /* port status */
|
||||
#define DA(p) \
|
||||
(((p)>>25)&0x7f) /* bits 31:25, device address */
|
||||
#define PORTS_SSTS (BIT(24) | BIT(23)) /* suspend status */
|
||||
#define PORTS_WKOC BIT(22) /* wake on over-current enable */
|
||||
#define PORTS_WKDS BIT(21) /* wake on disconnect enable */
|
||||
#define PORTS_WKCN BIT(20) /* wake on connect enable */
|
||||
#define PORTS_PTC(p) (((p)>>16)&0xf) /* bits 19:16, port test control */
|
||||
#define PORTS_PIC (BIT(15) | BIT(14)) /* port indicator control */
|
||||
#define PORTS_PO BIT(13) /* port owner */
|
||||
#define PORTS_PP BIT(12) /* port power */
|
||||
#define PORTS_LS (BIT(11) | BIT(10)) /* line status */
|
||||
#define PORTS_SLP BIT(9) /* suspend using L1 */
|
||||
#define PORTS_PR BIT(8) /* port reset */
|
||||
#define PORTS_SUSP BIT(7) /* suspend */
|
||||
#define PORTS_FPR BIT(6) /* force port resume */
|
||||
#define PORTS_OCC BIT(5) /* over-current change */
|
||||
#define PORTS_OCA BIT(4) /* over-current active */
|
||||
#define PORTS_PEC BIT(3) /* port enable/disable change */
|
||||
#define PORTS_PE BIT(2) /* port enable/disable */
|
||||
#define PORTS_CSC BIT(1) /* connect status change */
|
||||
#define PORTS_CCS BIT(0) /* current connect status */
|
||||
u8 _reserved7[0xb4-0x78];
|
||||
/* offset: 0xb4 */
|
||||
u32 devlc; /* control LPM and each USB port behavior */
|
||||
/* bits 31:29, parallel transceiver select */
|
||||
#define LPM_PTS(d) (((d)>>29)&7)
|
||||
#define LPM_STS BIT(28) /* serial transceiver select */
|
||||
#define LPM_PTW BIT(27) /* parallel transceiver width */
|
||||
#define LPM_PSPD(d) (((d)>>25)&3) /* bits 26:25, port speed */
|
||||
#define LPM_PSPD_MASK (BIT(26) | BIT(25))
|
||||
#define LPM_SPEED_FULL 0
|
||||
#define LPM_SPEED_LOW 1
|
||||
#define LPM_SPEED_HIGH 2
|
||||
#define LPM_SRT BIT(24) /* shorten reset time */
|
||||
#define LPM_PFSC BIT(23) /* port force full speed connect */
|
||||
#define LPM_PHCD BIT(22) /* PHY low power suspend clock disable */
|
||||
#define LPM_STL BIT(16) /* STALL reply to LPM token */
|
||||
#define LPM_BA(d) \
|
||||
(((d)>>1)&0x7ff) /* bits 11:1, BmAttributes */
|
||||
#define LPM_NYT_ACK BIT(0) /* NYET/ACK reply to LPM token */
|
||||
u8 _reserved8[0xf4-0xb8];
|
||||
/* offset: 0xf4 */
|
||||
u32 otgsc; /* On-The-Go status and control */
|
||||
#define OTGSC_DPIE BIT(30) /* data pulse interrupt enable */
|
||||
#define OTGSC_MSE BIT(29) /* 1 ms timer interrupt enable */
|
||||
#define OTGSC_BSEIE BIT(28) /* B session end interrupt enable */
|
||||
#define OTGSC_BSVIE BIT(27) /* B session valid interrupt enable */
|
||||
#define OTGSC_ASVIE BIT(26) /* A session valid interrupt enable */
|
||||
#define OTGSC_AVVIE BIT(25) /* A VBUS valid interrupt enable */
|
||||
#define OTGSC_IDIE BIT(24) /* USB ID interrupt enable */
|
||||
#define OTGSC_DPIS BIT(22) /* data pulse interrupt status */
|
||||
#define OTGSC_MSS BIT(21) /* 1 ms timer interrupt status */
|
||||
#define OTGSC_BSEIS BIT(20) /* B session end interrupt status */
|
||||
#define OTGSC_BSVIS BIT(19) /* B session valid interrupt status */
|
||||
#define OTGSC_ASVIS BIT(18) /* A session valid interrupt status */
|
||||
#define OTGSC_AVVIS BIT(17) /* A VBUS valid interrupt status */
|
||||
#define OTGSC_IDIS BIT(16) /* USB ID interrupt status */
|
||||
#define OTGSC_DPS BIT(14) /* data bus pulsing status */
|
||||
#define OTGSC_MST BIT(13) /* 1 ms timer toggle */
|
||||
#define OTGSC_BSE BIT(12) /* B session end */
|
||||
#define OTGSC_BSV BIT(11) /* B session valid */
|
||||
#define OTGSC_ASV BIT(10) /* A session valid */
|
||||
#define OTGSC_AVV BIT(9) /* A VBUS valid */
|
||||
#define OTGSC_USBID BIT(8) /* USB ID */
|
||||
#define OTGSC_HABA BIT(7) /* hw assist B-disconnect to A-connect */
|
||||
#define OTGSC_HADP BIT(6) /* hw assist data pulse */
|
||||
#define OTGSC_IDPU BIT(5) /* ID pullup */
|
||||
#define OTGSC_DP BIT(4) /* data pulsing */
|
||||
#define OTGSC_OT BIT(3) /* OTG termination */
|
||||
#define OTGSC_HAAR BIT(2) /* hw assist auto reset */
|
||||
#define OTGSC_VC BIT(1) /* VBUS charge */
|
||||
#define OTGSC_VD BIT(0) /* VBUS discharge */
|
||||
u32 usbmode;
|
||||
#define MODE_VBPS BIT(5) /* R/W VBUS power select */
|
||||
#define MODE_SDIS BIT(4) /* R/W stream disable mode */
|
||||
#define MODE_SLOM BIT(3) /* R/W setup lockout mode */
|
||||
#define MODE_ENSE BIT(2) /* endian select */
|
||||
#define MODE_CM(u) (((u)>>0)&3) /* bits 1:0, controller mode */
|
||||
#define MODE_IDLE 0
|
||||
#define MODE_DEVICE 2
|
||||
#define MODE_HOST 3
|
||||
u8 _reserved9[0x100-0xfc];
|
||||
/* offset: 0x100 */
|
||||
u32 endptnak;
|
||||
#define EPTN(e) \
|
||||
(((e)>>16)&0xffff) /* bits 31:16, TX endpoint NAK */
|
||||
#define EPRN(e) \
|
||||
(((e)>>0)&0xffff) /* bits 15:0, RX endpoint NAK */
|
||||
u32 endptnaken;
|
||||
#define EPTNE(e) \
|
||||
(((e)>>16)&0xffff) /* bits 31:16, TX endpoint NAK enable */
|
||||
#define EPRNE(e) \
|
||||
(((e)>>0)&0xffff) /* bits 15:0, RX endpoint NAK enable */
|
||||
u32 endptsetupstat;
|
||||
#define SETUPSTAT_MASK (0xffff << 0) /* bits 15:0 */
|
||||
#define EP0SETUPSTAT_MASK 1
|
||||
u32 endptprime;
|
||||
/* bits 31:16, prime endpoint transmit buffer */
|
||||
#define PETB(e) (((e)>>16)&0xffff)
|
||||
/* bits 15:0, prime endpoint receive buffer */
|
||||
#define PERB(e) (((e)>>0)&0xffff)
|
||||
/* offset: 0x110 */
|
||||
u32 endptflush;
|
||||
/* bits 31:16, flush endpoint transmit buffer */
|
||||
#define FETB(e) (((e)>>16)&0xffff)
|
||||
/* bits 15:0, flush endpoint receive buffer */
|
||||
#define FERB(e) (((e)>>0)&0xffff)
|
||||
u32 endptstat;
|
||||
/* bits 31:16, endpoint transmit buffer ready */
|
||||
#define ETBR(e) (((e)>>16)&0xffff)
|
||||
/* bits 15:0, endpoint receive buffer ready */
|
||||
#define ERBR(e) (((e)>>0)&0xffff)
|
||||
u32 endptcomplete;
|
||||
/* bits 31:16, endpoint transmit complete event */
|
||||
#define ETCE(e) (((e)>>16)&0xffff)
|
||||
/* bits 15:0, endpoint receive complete event */
|
||||
#define ERCE(e) (((e)>>0)&0xffff)
|
||||
/* offset: 0x11c */
|
||||
u32 endptctrl[16];
|
||||
#define EPCTRL_TXE BIT(23) /* TX endpoint enable */
|
||||
#define EPCTRL_TXR BIT(22) /* TX data toggle reset */
|
||||
#define EPCTRL_TXI BIT(21) /* TX data toggle inhibit */
|
||||
#define EPCTRL_TXT(e) (((e)>>18)&3) /* bits 19:18, TX endpoint type */
|
||||
#define EPCTRL_TXT_SHIFT 18
|
||||
#define EPCTRL_TXD BIT(17) /* TX endpoint data source */
|
||||
#define EPCTRL_TXS BIT(16) /* TX endpoint STALL */
|
||||
#define EPCTRL_RXE BIT(7) /* RX endpoint enable */
|
||||
#define EPCTRL_RXR BIT(6) /* RX data toggle reset */
|
||||
#define EPCTRL_RXI BIT(5) /* RX data toggle inhibit */
|
||||
#define EPCTRL_RXT(e) (((e)>>2)&3) /* bits 3:2, RX endpoint type */
|
||||
#define EPCTRL_RXT_SHIFT 2 /* bits 19:18, TX endpoint type */
|
||||
#define EPCTRL_RXD BIT(1) /* RX endpoint data sink */
|
||||
#define EPCTRL_RXS BIT(0) /* RX endpoint STALL */
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#endif /* __LANGWELL_UDC_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user