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powerpc/sstep: Add tests for Prefixed Add Immediate

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Use the existing support for testing compute type instructions to test
Prefixed Add Immediate (paddi). The R bit of the paddi instruction
controls whether current instruction address is used. Add test cases
for when R=1 and for R=0. paddi has a 34 bit immediate field formed by
concatenating si0 and si1. Add tests for the extreme values of this
field.

Skip the paddi tests if ISA v3.1 is unsupported.

Some of these test cases were added by Balamuruhan S.

Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
[mpe: Fix conflicts with ppc-opcode.h changes, squash in .balign]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200525025923.19843-5-jniethe5@gmail.com
This commit is contained in:
Jordan Niethe 2020-05-25 12:59:23 +10:00 committed by Michael Ellerman
parent 301ebf7d69
commit 4f82590078
2 changed files with 127 additions and 0 deletions
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125
arch/powerpc/lib/test_emulate_step.c
View File

@ -47,6 +47,11 @@
ppc_inst_prefix(PPC_PREFIX_MLS | __PPC_PRFX_R(pr) | IMM_H(i), \
PPC_INST_STFD | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
#define TEST_PADDI(t, a, i, pr) \
ppc_inst_prefix(PPC_PREFIX_MLS | __PPC_PRFX_R(pr) | IMM_H(i), \
PPC_RAW_ADDI(t, a, i))
static void __init init_pt_regs(struct pt_regs *regs)
{
static unsigned long msr;
@ -634,6 +639,11 @@ struct compute_test {
} subtests[MAX_SUBTESTS + 1];
};
/* Extreme values for si0||si1 (the MLS:D-form 34 bit immediate field) */
#define SI_MIN BIT(33)
#define SI_MAX (BIT(33) - 1)
#define SI_UMAX (BIT(34) - 1)
static struct compute_test compute_tests[] = {
{
.mnemonic = "nop",
@ -1006,6 +1016,121 @@ static struct compute_test compute_tests[] = {
}
}
}
},
{
.mnemonic = "paddi",
.cpu_feature = CPU_FTR_ARCH_31,
.subtests = {
{
.descr = "RA = LONG_MIN, SI = SI_MIN, R = 0",
.instr = TEST_PADDI(21, 22, SI_MIN, 0),
.regs = {
.gpr[21] = 0,
.gpr[22] = LONG_MIN,
}
},
{
.descr = "RA = LONG_MIN, SI = SI_MAX, R = 0",
.instr = TEST_PADDI(21, 22, SI_MAX, 0),
.regs = {
.gpr[21] = 0,
.gpr[22] = LONG_MIN,
}
},
{
.descr = "RA = LONG_MAX, SI = SI_MAX, R = 0",
.instr = TEST_PADDI(21, 22, SI_MAX, 0),
.regs = {
.gpr[21] = 0,
.gpr[22] = LONG_MAX,
}
},
{
.descr = "RA = ULONG_MAX, SI = SI_UMAX, R = 0",
.instr = TEST_PADDI(21, 22, SI_UMAX, 0),
.regs = {
.gpr[21] = 0,
.gpr[22] = ULONG_MAX,
}
},
{
.descr = "RA = ULONG_MAX, SI = 0x1, R = 0",
.instr = TEST_PADDI(21, 22, 0x1, 0),
.regs = {
.gpr[21] = 0,
.gpr[22] = ULONG_MAX,
}
},
{
.descr = "RA = INT_MIN, SI = SI_MIN, R = 0",
.instr = TEST_PADDI(21, 22, SI_MIN, 0),
.regs = {
.gpr[21] = 0,
.gpr[22] = INT_MIN,
}
},
{
.descr = "RA = INT_MIN, SI = SI_MAX, R = 0",
.instr = TEST_PADDI(21, 22, SI_MAX, 0),
.regs = {
.gpr[21] = 0,
.gpr[22] = INT_MIN,
}
},
{
.descr = "RA = INT_MAX, SI = SI_MAX, R = 0",
.instr = TEST_PADDI(21, 22, SI_MAX, 0),
.regs = {
.gpr[21] = 0,
.gpr[22] = INT_MAX,
}
},
{
.descr = "RA = UINT_MAX, SI = 0x1, R = 0",
.instr = TEST_PADDI(21, 22, 0x1, 0),
.regs = {
.gpr[21] = 0,
.gpr[22] = UINT_MAX,
}
},
{
.descr = "RA = UINT_MAX, SI = SI_MAX, R = 0",
.instr = TEST_PADDI(21, 22, SI_MAX, 0),
.regs = {
.gpr[21] = 0,
.gpr[22] = UINT_MAX,
}
},
{
.descr = "RA is r0, SI = SI_MIN, R = 0",
.instr = TEST_PADDI(21, 0, SI_MIN, 0),
.regs = {
.gpr[21] = 0x0,
}
},
{
.descr = "RA = 0, SI = SI_MIN, R = 0",
.instr = TEST_PADDI(21, 22, SI_MIN, 0),
.regs = {
.gpr[21] = 0x0,
.gpr[22] = 0x0,
}
},
{
.descr = "RA is r0, SI = 0, R = 1",
.instr = TEST_PADDI(21, 0, 0, 1),
.regs = {
.gpr[21] = 0,
}
},
{
.descr = "RA is r0, SI = SI_MIN, R = 1",
.instr = TEST_PADDI(21, 0, SI_MIN, 1),
.regs = {
.gpr[21] = 0,
}
}
}
}
};

2
arch/powerpc/lib/test_emulate_step_exec_instr.S
View File

@ -80,7 +80,9 @@ _GLOBAL(exec_instr)
REST_NVGPRS(r31)
/* Placeholder for the test instruction */
.balign 64
1: nop
nop
patch_site 1b patch__exec_instr
/*