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dt-bindings: display: mediatek: disp: split each block to individual yaml
1. Remove mediatek,dislpay.txt 2. Split each display function block to individual yaml file. Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
This commit is contained in:
jason-jh.lin
Chun-Kuang Hu
parent
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commit
4ed545e7d1
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/mediatek/mediatek,aal.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek display adaptive ambient light processor
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maintainers:
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- Chun-Kuang Hu <chunkuang.hu@kernel.org>
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- Philipp Zabel <p.zabel@pengutronix.de>
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description: |
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Mediatek display adaptive ambient light processor, namely AAL,
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is responsible for backlight power saving and sunlight visibility improving.
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AAL device node must be siblings to the central MMSYS_CONFIG node.
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For a description of the MMSYS_CONFIG binding, see
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Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
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for details.
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properties:
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compatible:
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oneOf:
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- items:
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- const: mediatek,mt8173-disp-aal
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- items:
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- enum:
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- mediatek,mt2712-disp-aal
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- mediatek,mt8183-disp-aal
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- mediatek,mt8192-disp-aal
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- enum:
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- mediatek,mt8173-disp-aal
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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power-domains:
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description: A phandle and PM domain specifier as defined by bindings of
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the power controller specified by phandle. See
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Documentation/devicetree/bindings/power/power-domain.yaml for details.
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clocks:
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items:
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- description: AAL Clock
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mediatek,gce-client-reg:
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description: The register of client driver can be configured by gce with
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4 arguments defined in this property, such as phandle of gce, subsys id,
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register offset and size. Each GCE subsys id is mapping to a client
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defined in the header include/dt-bindings/gce/<chip>-gce.h.
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$ref: /schemas/types.yaml#/definitions/phandle-array
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- power-domains
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- clocks
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additionalProperties: false
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examples:
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- |
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aal@14015000 {
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compatible = "mediatek,mt8173-disp-aal";
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reg = <0 0x14015000 0 0x1000>;
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interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_AAL>;
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mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
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};
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@ -0,0 +1,71 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/mediatek/mediatek,ccorr.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek display color correction
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maintainers:
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- Chun-Kuang Hu <chunkuang.hu@kernel.org>
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- Philipp Zabel <p.zabel@pengutronix.de>
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description: |
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Mediatek display color correction, namely CCORR, reproduces correct color
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on panels with different color gamut.
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CCORR device node must be siblings to the central MMSYS_CONFIG node.
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For a description of the MMSYS_CONFIG binding, see
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Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
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for details.
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properties:
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compatible:
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oneOf:
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- items:
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- const: mediatek,mt8183-disp-ccorr
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- items:
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- const: mediatek,mt8192-disp-ccorr
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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power-domains:
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description: A phandle and PM domain specifier as defined by bindings of
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the power controller specified by phandle. See
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Documentation/devicetree/bindings/power/power-domain.yaml for details.
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clocks:
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items:
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- description: CCORR Clock
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mediatek,gce-client-reg:
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description: The register of client driver can be configured by gce with
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4 arguments defined in this property, such as phandle of gce, subsys id,
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register offset and size. Each GCE subsys id is mapping to a client
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defined in the header include/dt-bindings/gce/<chip>-gce.h.
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$ref: /schemas/types.yaml#/definitions/phandle-array
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- power-domains
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- clocks
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additionalProperties: false
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examples:
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- |
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ccorr0: ccorr@1400f000 {
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compatible = "mediatek,mt8183-disp-ccorr";
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reg = <0 0x1400f000 0 0x1000>;
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interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
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clocks = <&mmsys CLK_MM_DISP_CCORR0>;
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mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
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};
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@ -0,0 +1,85 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/mediatek/mediatek,color.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek display color processor
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maintainers:
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- Chun-Kuang Hu <chunkuang.hu@kernel.org>
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- Philipp Zabel <p.zabel@pengutronix.de>
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description: |
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Mediatek display color processor, namely COLOR, provides hue, luma and
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saturation adjustments to get better picture quality and to have one panel
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resemble the other in their output characteristics.
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COLOR device node must be siblings to the central MMSYS_CONFIG node.
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For a description of the MMSYS_CONFIG binding, see
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Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
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for details.
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properties:
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compatible:
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oneOf:
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- items:
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- const: mediatek,mt2701-disp-color
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- items:
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- const: mediatek,mt8167-disp-color
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- items:
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- const: mediatek,mt8173-disp-color
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- items:
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- enum:
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- mediatek,mt7623-disp-color
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- mediatek,mt2712-disp-color
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- enum:
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- mediatek,mt2701-disp-color
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- items:
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- enum:
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- mediatek,mt8183-disp-color
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- mediatek,mt8192-disp-color
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- enum:
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- mediatek,mt8173-disp-color
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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power-domains:
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description: A phandle and PM domain specifier as defined by bindings of
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the power controller specified by phandle. See
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Documentation/devicetree/bindings/power/power-domain.yaml for details.
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clocks:
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items:
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- description: COLOR Clock
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mediatek,gce-client-reg:
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description: The register of client driver can be configured by gce with
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4 arguments defined in this property, such as phandle of gce, subsys id,
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register offset and size. Each GCE subsys id is mapping to a client
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defined in the header include/dt-bindings/gce/<chip>-gce.h.
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$ref: /schemas/types.yaml#/definitions/phandle-array
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- power-domains
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- clocks
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additionalProperties: false
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examples:
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- |
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color0: color@14013000 {
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compatible = "mediatek,mt8173-disp-color";
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reg = <0 0x14013000 0 0x1000>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_COLOR0>;
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mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
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};
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@ -1,219 +0,0 @@
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Mediatek display subsystem
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==========================
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The Mediatek display subsystem consists of various DISP function blocks in the
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MMSYS register space. The connections between them can be configured by output
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and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
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of frame signal are distributed to the other function blocks by a DISP_MUTEX
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function block.
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All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
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For a description of the MMSYS_CONFIG binding, see
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Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml.
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DISP function blocks
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====================
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A display stream starts at a source function block that reads pixel data from
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memory and ends with a sink function block that drives pixels on a display
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interface, or writes pixels back to memory. All DISP function blocks have
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their own register space, interrupt, and clock gate. The blocks that can
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access memory additionally have to list the IOMMU and local arbiter they are
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connected to.
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For a description of the display interface sink function blocks, see
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Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
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Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml.
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Required properties (all function blocks):
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- compatible: "mediatek,<chip>-disp-<function>", one of
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"mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
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"mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc)
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"mediatek,<chip>-disp-rdma" - read DMA / line buffer
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"mediatek,<chip>-disp-wdma" - write DMA
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"mediatek,<chip>-disp-ccorr" - color correction
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"mediatek,<chip>-disp-color" - color processor
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"mediatek,<chip>-disp-dither" - dither
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"mediatek,<chip>-disp-aal" - adaptive ambient light controller
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"mediatek,<chip>-disp-gamma" - gamma correction
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"mediatek,<chip>-disp-merge" - merge streams from two RDMA sources
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"mediatek,<chip>-disp-postmask" - control round corner for display frame
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"mediatek,<chip>-disp-split" - split stream to two encoders
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"mediatek,<chip>-disp-ufoe" - data compression engine
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"mediatek,<chip>-dsi" - DSI controller, see mediatek,dsi.txt
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"mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
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"mediatek,<chip>-disp-mutex" - display mutex
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"mediatek,<chip>-disp-od" - overdrive
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the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and mt8192.
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- reg: Physical base address and length of the function block register space
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- interrupts: The interrupt signal from the function block (required, except for
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merge and split function blocks).
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- clocks: device clocks
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See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
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For most function blocks this is just a single clock input. Only the DSI and
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DPI controller nodes have multiple clock inputs. These are documented in
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mediatek,dsi.txt and mediatek,dpi.txt, respectively.
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An exception is that the mt8183 mutex is always free running with no clocks property.
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Required properties (DMA function blocks):
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- compatible: Should be one of
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"mediatek,<chip>-disp-ovl"
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"mediatek,<chip>-disp-rdma"
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"mediatek,<chip>-disp-wdma"
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the supported chips are mt2701, mt8167 and mt8173.
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- larb: Should contain a phandle pointing to the local arbiter device as defined
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in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
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- iommus: Should point to the respective IOMMU block with master port as
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argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
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for details.
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Optional properties (RDMA function blocks):
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- mediatek,rdma-fifo-size: rdma fifo size may be different even in same SOC, add this
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property to the corresponding rdma
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the value is the Max value which defined in hardware data sheet.
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mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
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mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
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mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
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Examples:
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mmsys: clock-controller@14000000 {
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compatible = "mediatek,mt8173-mmsys", "syscon";
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reg = <0 0x14000000 0 0x1000>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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#clock-cells = <1>;
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};
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ovl0: ovl@1400c000 {
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compatible = "mediatek,mt8173-disp-ovl";
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reg = <0 0x1400c000 0 0x1000>;
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interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_OVL0>;
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iommus = <&iommu M4U_PORT_DISP_OVL0>;
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mediatek,larb = <&larb0>;
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};
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ovl1: ovl@1400d000 {
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compatible = "mediatek,mt8173-disp-ovl";
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reg = <0 0x1400d000 0 0x1000>;
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interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_OVL1>;
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iommus = <&iommu M4U_PORT_DISP_OVL1>;
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mediatek,larb = <&larb4>;
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};
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rdma0: rdma@1400e000 {
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compatible = "mediatek,mt8173-disp-rdma";
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reg = <0 0x1400e000 0 0x1000>;
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interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_RDMA0>;
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iommus = <&iommu M4U_PORT_DISP_RDMA0>;
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mediatek,larb = <&larb0>;
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mediatek,rdma-fifosize = <8192>;
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};
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rdma1: rdma@1400f000 {
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compatible = "mediatek,mt8173-disp-rdma";
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reg = <0 0x1400f000 0 0x1000>;
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interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_RDMA1>;
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iommus = <&iommu M4U_PORT_DISP_RDMA1>;
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mediatek,larb = <&larb4>;
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};
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rdma2: rdma@14010000 {
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compatible = "mediatek,mt8173-disp-rdma";
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reg = <0 0x14010000 0 0x1000>;
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interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_RDMA2>;
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iommus = <&iommu M4U_PORT_DISP_RDMA2>;
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mediatek,larb = <&larb4>;
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};
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wdma0: wdma@14011000 {
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compatible = "mediatek,mt8173-disp-wdma";
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reg = <0 0x14011000 0 0x1000>;
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interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_WDMA0>;
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iommus = <&iommu M4U_PORT_DISP_WDMA0>;
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mediatek,larb = <&larb0>;
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};
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wdma1: wdma@14012000 {
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compatible = "mediatek,mt8173-disp-wdma";
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reg = <0 0x14012000 0 0x1000>;
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_WDMA1>;
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iommus = <&iommu M4U_PORT_DISP_WDMA1>;
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mediatek,larb = <&larb4>;
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};
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color0: color@14013000 {
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compatible = "mediatek,mt8173-disp-color";
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reg = <0 0x14013000 0 0x1000>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_COLOR0>;
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};
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color1: color@14014000 {
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compatible = "mediatek,mt8173-disp-color";
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reg = <0 0x14014000 0 0x1000>;
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interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_COLOR1>;
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};
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aal@14015000 {
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compatible = "mediatek,mt8173-disp-aal";
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reg = <0 0x14015000 0 0x1000>;
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interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_AAL>;
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};
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gamma@14016000 {
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compatible = "mediatek,mt8173-disp-gamma";
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reg = <0 0x14016000 0 0x1000>;
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interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_GAMMA>;
|
||||
};
|
||||
|
||||
ufoe@1401a000 {
|
||||
compatible = "mediatek,mt8173-disp-ufoe";
|
||||
reg = <0 0x1401a000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_UFOE>;
|
||||
};
|
||||
|
||||
dsi0: dsi@1401b000 {
|
||||
/* See mediatek,dsi.txt for details */
|
||||
};
|
||||
|
||||
dpi0: dpi@1401d000 {
|
||||
/* See mediatek,dpi.txt for details */
|
||||
};
|
||||
|
||||
mutex: mutex@14020000 {
|
||||
compatible = "mediatek,mt8173-disp-mutex";
|
||||
reg = <0 0x14020000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_MUTEX_32K>;
|
||||
};
|
||||
|
||||
od@14023000 {
|
||||
compatible = "mediatek,mt8173-disp-od";
|
||||
reg = <0 0x14023000 0 0x1000>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OD>;
|
||||
};
|
||||
@ -0,0 +1,75 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,dither.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek display dither processor
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
Mediatek display dither processor, namely DITHER, works by approximating
|
||||
unavailable colors with available colors and by mixing and matching available
|
||||
colors to mimic unavailable ones.
|
||||
DITHER device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
|
||||
for details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt8183-disp-dither
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8192-disp-dither
|
||||
- enum:
|
||||
- mediatek,mt8183-disp-dither
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description: A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: DITHER Clock
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description: The register of client driver can be configured by gce with
|
||||
4 arguments defined in this property, such as phandle of gce, subsys id,
|
||||
register offset and size. Each GCE subsys id is mapping to a client
|
||||
defined in the header include/dt-bindings/gce/<chip>-gce.h.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- power-domains
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
dither0: dither@14012000 {
|
||||
compatible = "mediatek,mt8183-disp-dither";
|
||||
reg = <0 0x14012000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
|
||||
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
|
||||
};
|
||||
@ -0,0 +1,76 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,gamma.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek display gamma correction
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
Mediatek display gamma correction, namely GAMMA, provides a nonlinear
|
||||
operation used to adjust luminance in display system.
|
||||
GAMMA device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
|
||||
for details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt8173-disp-gamma
|
||||
- items:
|
||||
- const: mediatek,mt8183-disp-gamma
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8192-disp-gamma
|
||||
- enum:
|
||||
- mediatek,mt8183-disp-gamma
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description: A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: GAMMA Clock
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description: The register of client driver can be configured by gce with
|
||||
4 arguments defined in this property, such as phandle of gce, subsys id,
|
||||
register offset and size. Each GCE subsys id is mapping to a client
|
||||
defined in the header include/dt-bindings/gce/<chip>-gce.h.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- power-domains
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
gamma@14016000 {
|
||||
compatible = "mediatek,mt8173-disp-gamma";
|
||||
reg = <0 0x14016000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_GAMMA>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
|
||||
};
|
||||
@ -0,0 +1,66 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek display merge
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
Mediatek display merge, namely MERGE, is used to merge two slice-per-line
|
||||
inputs into one side-by-side output.
|
||||
MERGE device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
|
||||
for details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt8173-disp-merge
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description: A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: MERGE Clock
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description: The register of client driver can be configured by gce with
|
||||
4 arguments defined in this property, such as phandle of gce, subsys id,
|
||||
register offset and size. Each GCE subsys id is mapping to a client
|
||||
defined in the header include/dt-bindings/gce/<chip>-gce.h.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- power-domains
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
merge@14017000 {
|
||||
compatible = "mediatek,mt8173-disp-merge";
|
||||
reg = <0 0x14017000 0 0x1000>;
|
||||
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_MERGE>;
|
||||
};
|
||||
@ -0,0 +1,82 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek display mutex
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
Mediatek mutex, namely MUTEX, is used to send the triggers signals called
|
||||
Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
|
||||
data path or MDP data path.
|
||||
In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
|
||||
the shadow register.
|
||||
MUTEX device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
|
||||
for details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt2701-disp-mutex
|
||||
- items:
|
||||
- const: mediatek,mt2712-disp-mutex
|
||||
- items:
|
||||
- const: mediatek,mt8167-disp-mutex
|
||||
- items:
|
||||
- const: mediatek,mt8173-disp-mutex
|
||||
- items:
|
||||
- const: mediatek,mt8183-disp-mutex
|
||||
- items:
|
||||
- const: mediatek,mt8192-disp-mutex
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description: A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: MUTEX Clock
|
||||
|
||||
mediatek,gce-events:
|
||||
description:
|
||||
The event id which is mapping to the specific hardware event signal
|
||||
to gce. The event id is defined in the gce header
|
||||
include/dt-bindings/gce/<chip>-gce.h of each chips.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- power-domains
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
mutex: mutex@14020000 {
|
||||
compatible = "mediatek,mt8173-disp-mutex";
|
||||
reg = <0 0x14020000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_MUTEX_32K>;
|
||||
mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
|
||||
<CMDQ_EVENT_MUTEX1_STREAM_EOF>;
|
||||
};
|
||||
@ -0,0 +1,53 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,od.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek display overdirve
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
Mediatek display overdrive, namely OD, increases the transition values
|
||||
of pixels between consecutive frames to make LCD rotate faster.
|
||||
OD device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
|
||||
for details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt2712-disp-od
|
||||
- items:
|
||||
- const: mediatek,mt8173-disp-od
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: OD Clock
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
od@14023000 {
|
||||
compatible = "mediatek,mt8173-disp-od";
|
||||
reg = <0 0x14023000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OD>;
|
||||
};
|
||||
@ -0,0 +1,88 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl-2l.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek display overlay 2 layer
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
Mediatek display overlay 2 layer, namely OVL-2L, provides 2 more layer
|
||||
for OVL.
|
||||
OVL-2L device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
|
||||
for details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt8183-disp-ovl-2l
|
||||
- items:
|
||||
- const: mediatek,mt8192-disp-ovl-2l
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description: A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: OVL-2L Clock
|
||||
|
||||
iommus:
|
||||
description:
|
||||
This property should point to the respective IOMMU block with master port as argument,
|
||||
see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
|
||||
|
||||
mediatek,larb:
|
||||
description:
|
||||
This property should contain a phandle pointing to the local arbiter devices defined in
|
||||
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
|
||||
It must sort according to the local arbiter index, like larb0, larb1, larb2...
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description: The register of client driver can be configured by gce with
|
||||
4 arguments defined in this property, such as phandle of gce, subsys id,
|
||||
register offset and size. Each GCE subsys id is mapping to a client
|
||||
defined in the header include/dt-bindings/gce/<chip>-gce.h.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- power-domains
|
||||
- clocks
|
||||
- iommus
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
ovl_2l0: ovl@14009000 {
|
||||
compatible = "mediatek,mt8183-disp-ovl-2l";
|
||||
reg = <0 0x14009000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
|
||||
iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
|
||||
mediatek,larb = <&larb0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
|
||||
};
|
||||
@ -0,0 +1,98 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek display overlay
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
Mediatek display overlay, namely OVL, can do alpha blending from
|
||||
the memory.
|
||||
OVL device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
|
||||
for details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt2701-disp-ovl
|
||||
- items:
|
||||
- const: mediatek,mt8173-disp-ovl
|
||||
- items:
|
||||
- const: mediatek,mt8183-disp-ovl
|
||||
- items:
|
||||
- const: mediatek,mt8192-disp-ovl
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt7623-disp-ovl
|
||||
- mediatek,mt2712-disp-ovl
|
||||
- enum:
|
||||
- mediatek,mt2701-disp-ovl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description: A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: OVL Clock
|
||||
|
||||
iommus:
|
||||
description:
|
||||
This property should point to the respective IOMMU block with master port as argument,
|
||||
see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
|
||||
|
||||
mediatek,larb:
|
||||
description:
|
||||
This property should contain a phandle pointing to the local arbiter devices defined in
|
||||
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
|
||||
It must sort according to the local arbiter index, like larb0, larb1, larb2...
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description: The register of client driver can be configured by gce with
|
||||
4 arguments defined in this property, such as phandle of gce, subsys id,
|
||||
register offset and size. Each GCE subsys id is mapping to a client
|
||||
defined in the header include/dt-bindings/gce/<chip>-gce.h.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- power-domains
|
||||
- clocks
|
||||
- iommu
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
ovl0: ovl@1400c000 {
|
||||
compatible = "mediatek,mt8173-disp-ovl";
|
||||
reg = <0 0x1400c000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OVL0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_OVL0>;
|
||||
mediatek,larb = <&larb0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
|
||||
};
|
||||
@ -0,0 +1,69 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,postmask.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek display postmask
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
Mediatek display postmask, namely POSTMASK, provides round corner pattern
|
||||
generation.
|
||||
POSTMASK device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
|
||||
for details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt8192-disp-postmask
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description: A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: POSTMASK Clock
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description: The register of client driver can be configured by gce with
|
||||
4 arguments defined in this property, such as phandle of gce, subsys id,
|
||||
register offset and size. Each GCE subsys id is mapping to a client
|
||||
defined in the header include/dt-bindings/gce/<chip>-gce.h.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- power-domains
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
postmask0: postmask@1400d000 {
|
||||
compatible = "mediatek,mt8192-disp-postmask";
|
||||
reg = <0 0x1400d000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
|
||||
clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
|
||||
};
|
||||
@ -0,0 +1,115 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,rdma.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek Read Direct Memory Access
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
Mediatek Read Direct Memory Access(RDMA) component used to read the
|
||||
data into DMA. It provides real time data to the back-end panel
|
||||
driver, such as DSI, DPI and DP_INTF.
|
||||
It contains one line buffer to store the sufficient pixel data.
|
||||
RDMA device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
|
||||
for details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt2701-disp-rdma
|
||||
- items:
|
||||
- const: mediatek,mt8173-disp-rdma
|
||||
- items:
|
||||
- const: mediatek,mt8183-disp-rdma
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt7623-disp-rdma
|
||||
- mediatek,mt2712-disp-rdma
|
||||
- enum:
|
||||
- mediatek,mt2701-disp-rdma
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8192-disp-rdma
|
||||
- enum:
|
||||
- mediatek,mt8183-disp-rdma
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description: A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: RDMA Clock
|
||||
|
||||
iommus:
|
||||
description:
|
||||
This property should point to the respective IOMMU block with master port as argument,
|
||||
see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
|
||||
|
||||
mediatek,larb:
|
||||
description:
|
||||
This property should contain a phandle pointing to the local arbiter devices defined in
|
||||
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
|
||||
It must sort according to the local arbiter index, like larb0, larb1, larb2...
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
|
||||
mediatek,rdma-fifo-size:
|
||||
description:
|
||||
rdma fifo size may be different even in same SOC, add this property to the
|
||||
corresponding rdma.
|
||||
The value below is the Max value which defined in hardware data sheet
|
||||
mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
|
||||
mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
|
||||
mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [8192, 5120, 2048]
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description: The register of client driver can be configured by gce with
|
||||
4 arguments defined in this property, such as phandle of gce, subsys id,
|
||||
register offset and size. Each GCE subsys id is mapping to a client
|
||||
defined in the header include/dt-bindings/gce/<chip>-gce.h.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- power-domains
|
||||
- clocks
|
||||
- iommus
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
rdma0: rdma@1400e000 {
|
||||
compatible = "mediatek,mt8173-disp-rdma";
|
||||
reg = <0 0x1400e000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
|
||||
mediatek,larb = <&larb0>;
|
||||
mediatek,rdma-fifosize = <8192>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
|
||||
};
|
||||
@ -0,0 +1,58 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek display split
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
Mediatek display split, namely SPLIT, is used to split stream to two
|
||||
encoders.
|
||||
SPLIT device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
|
||||
for details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt8173-disp-split
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description: A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: SPLIT Clock
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- power-domains
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
split0: split@14018000 {
|
||||
compatible = "mediatek,mt8173-disp-split";
|
||||
reg = <0 0x14018000 0 0x1000>;
|
||||
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
|
||||
};
|
||||
@ -0,0 +1,61 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,ufoe.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek display UFOe
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
Mediatek display UFOe stands for Unified Frame Optimization engine.
|
||||
UFOe can cut the data rate for DSI port which may lead to reduce power
|
||||
consumption.
|
||||
UFOe device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
|
||||
for details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt8173-disp-ufoe
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description: A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: UFOe Clock
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- power-domains
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
ufoe@1401a000 {
|
||||
compatible = "mediatek,mt8173-disp-ufoe";
|
||||
reg = <0 0x1401a000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_UFOE>;
|
||||
};
|
||||
@ -0,0 +1,86 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,wdma.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek Write Direct Memory Access
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
Mediatek Write Direct Memory Access(WDMA) component used to write
|
||||
the data into DMA.
|
||||
WDMA device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
|
||||
for details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt8173-disp-wdma
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description: A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: WDMA Clock
|
||||
|
||||
iommus:
|
||||
description:
|
||||
This property should point to the respective IOMMU block with master port as argument,
|
||||
see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
|
||||
|
||||
mediatek,larb:
|
||||
description:
|
||||
This property should contain a phandle pointing to the local arbiter devices defined in
|
||||
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
|
||||
It must sort according to the local arbiter index, like larb0, larb1, larb2...
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description: The register of client driver can be configured by gce with
|
||||
4 arguments defined in this property, such as phandle of gce, subsys id,
|
||||
register offset and size. Each GCE subsys id is mapping to a client
|
||||
defined in the header include/dt-bindings/gce/<chip>-gce.h.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- power-domains
|
||||
- clocks
|
||||
- iommus
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
wdma0: wdma@14011000 {
|
||||
compatible = "mediatek,mt8173-disp-wdma";
|
||||
reg = <0 0x14011000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_WDMA0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_WDMA0>;
|
||||
mediatek,larb = <&larb0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user