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Merge branch 'sh-pfc-for-v4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

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This commit is contained in:
Linus Walleij 2015-12-10 15:41:19 +01:00
commit 4e395cf099
11 changed files with 1949 additions and 262 deletions
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136
drivers/pinctrl/sh-pfc/pfc-emev2.c
View File

@ -258,18 +258,18 @@ static const u16 pinmux_data[] = {
/* GPSR0 */
/* V9 */
PINMUX_DATA(JT_SEL_MARK, FN_JT_SEL),
PINMUX_SINGLE(JT_SEL),
/* U9 */
PINMUX_DATA(ERR_RST_REQB_MARK, FN_ERR_RST_REQB),
PINMUX_SINGLE(ERR_RST_REQB),
/* V8 */
PINMUX_DATA(REF_CLKO_MARK, FN_REF_CLKO),
PINMUX_SINGLE(REF_CLKO),
/* U8 */
PINMUX_DATA(EXT_CLKI_MARK, FN_EXT_CLKI),
PINMUX_SINGLE(EXT_CLKI),
/* B22*/
PINMUX_IPSR_NOFN(LCD3_1_0_PORT18, LCD3_PXCLK, SEL_LCD3_1_0_00),
PINMUX_IPSR_NOFN(LCD3_1_0_PORT18, YUV3_CLK_O, SEL_LCD3_1_0_01),
/* C21 */
PINMUX_DATA(LCD3_PXCLKB_MARK, FN_LCD3_PXCLKB),
PINMUX_SINGLE(LCD3_PXCLKB),
/* A21 */
PINMUX_IPSR_NOFN(LCD3_1_0_PORT20, LCD3_CLK_I, SEL_LCD3_1_0_00),
PINMUX_IPSR_NOFN(LCD3_1_0_PORT20, YUV3_CLK_I, SEL_LCD3_1_0_01),
@ -285,17 +285,17 @@ static const u16 pinmux_data[] = {
/* GPSR1 */
/* A20 */
PINMUX_DATA(LCD3_R0_MARK, FN_LCD3_R0),
PINMUX_SINGLE(LCD3_R0),
/* B20 */
PINMUX_DATA(LCD3_R1_MARK, FN_LCD3_R1),
PINMUX_SINGLE(LCD3_R1),
/* A19 */
PINMUX_DATA(LCD3_R2_MARK, FN_LCD3_R2),
PINMUX_SINGLE(LCD3_R2),
/* B19 */
PINMUX_DATA(LCD3_R3_MARK, FN_LCD3_R3),
PINMUX_SINGLE(LCD3_R3),
/* C19 */
PINMUX_DATA(LCD3_R4_MARK, FN_LCD3_R4),
PINMUX_SINGLE(LCD3_R4),
/* B18 */
PINMUX_DATA(LCD3_R5_MARK, FN_LCD3_R5),
PINMUX_SINGLE(LCD3_R5),
/* C18 */
PINMUX_IPSR_NOFN(LCD3_9_8_PORT38, LCD3_R6, SEL_LCD3_9_8_00),
PINMUX_IPSR_NOFN(LCD3_9_8_PORT38, TP33_CLK, SEL_LCD3_9_8_10),
@ -367,9 +367,9 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D15, SEL_LCD3_11_10_01),
PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA15, SEL_LCD3_11_10_10),
/* AA9 */
PINMUX_DATA(IIC0_SCL_MARK, FN_IIC0_SCL),
PINMUX_SINGLE(IIC0_SCL),
/* AA8 */
PINMUX_DATA(IIC0_SDA_MARK, FN_IIC0_SDA),
PINMUX_SINGLE(IIC0_SDA),
/* Y9 */
PINMUX_IPSR_NOFN(IIC_1_0_PORT46, IIC1_SCL, SEL_IIC_1_0_00),
PINMUX_IPSR_NOFN(IIC_1_0_PORT46, UART3_RX, SEL_IIC_1_0_01),
@ -377,51 +377,51 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_NOFN(IIC_1_0_PORT47, IIC1_SDA, SEL_IIC_1_0_00),
PINMUX_IPSR_NOFN(IIC_1_0_PORT47, UART3_TX, SEL_IIC_1_0_01),
/* AC19 */
PINMUX_DATA(SD_CKI_MARK, FN_SD_CKI),
PINMUX_SINGLE(SD_CKI),
/* AB18 */
PINMUX_DATA(SDI0_CKO_MARK, FN_SDI0_CKO),
PINMUX_SINGLE(SDI0_CKO),
/* AC18 */
PINMUX_DATA(SDI0_CKI_MARK, FN_SDI0_CKI),
PINMUX_SINGLE(SDI0_CKI),
/* Y12 */
PINMUX_DATA(SDI0_CMD_MARK, FN_SDI0_CMD),
PINMUX_SINGLE(SDI0_CMD),
/* AA13 */
PINMUX_DATA(SDI0_DATA0_MARK, FN_SDI0_DATA0),
PINMUX_SINGLE(SDI0_DATA0),
/* Y13 */
PINMUX_DATA(SDI0_DATA1_MARK, FN_SDI0_DATA1),
PINMUX_SINGLE(SDI0_DATA1),
/* AA14 */
PINMUX_DATA(SDI0_DATA2_MARK, FN_SDI0_DATA2),
PINMUX_SINGLE(SDI0_DATA2),
/* Y14 */
PINMUX_DATA(SDI0_DATA3_MARK, FN_SDI0_DATA3),
PINMUX_SINGLE(SDI0_DATA3),
/* AA15 */
PINMUX_DATA(SDI0_DATA4_MARK, FN_SDI0_DATA4),
PINMUX_SINGLE(SDI0_DATA4),
/* Y15 */
PINMUX_DATA(SDI0_DATA5_MARK, FN_SDI0_DATA5),
PINMUX_SINGLE(SDI0_DATA5),
/* AA16 */
PINMUX_DATA(SDI0_DATA6_MARK, FN_SDI0_DATA6),
PINMUX_SINGLE(SDI0_DATA6),
/* Y16 */
PINMUX_DATA(SDI0_DATA7_MARK, FN_SDI0_DATA7),
PINMUX_SINGLE(SDI0_DATA7),
/* AB22 */
PINMUX_DATA(SDI1_CKO_MARK, FN_SDI1_CKO),
PINMUX_SINGLE(SDI1_CKO),
/* AA23 */
PINMUX_DATA(SDI1_CKI_MARK, FN_SDI1_CKI),
PINMUX_SINGLE(SDI1_CKI),
/* AC21 */
PINMUX_DATA(SDI1_CMD_MARK, FN_SDI1_CMD),
PINMUX_SINGLE(SDI1_CMD),
/* GPSR2 */
/* AB21 */
PINMUX_DATA(SDI1_DATA0_MARK, FN_SDI1_DATA0),
PINMUX_SINGLE(SDI1_DATA0),
/* AB20 */
PINMUX_DATA(SDI1_DATA1_MARK, FN_SDI1_DATA1),
PINMUX_SINGLE(SDI1_DATA1),
/* AB19 */
PINMUX_DATA(SDI1_DATA2_MARK, FN_SDI1_DATA2),
PINMUX_SINGLE(SDI1_DATA2),
/* AA19 */
PINMUX_DATA(SDI1_DATA3_MARK, FN_SDI1_DATA3),
PINMUX_SINGLE(SDI1_DATA3),
/* J23 */
PINMUX_DATA(AB_CLK_MARK, FN_AB_CLK),
PINMUX_SINGLE(AB_CLK),
/* D21 */
PINMUX_DATA(AB_CSB0_MARK, FN_AB_CSB0),
PINMUX_SINGLE(AB_CSB0),
/* E21 */
PINMUX_DATA(AB_CSB1_MARK, FN_AB_CSB1),
PINMUX_SINGLE(AB_CSB1),
/* F20 */
PINMUX_IPSR_NOFN(AB_1_0_PORT71, AB_CSB2, SEL_AB_1_0_00),
PINMUX_IPSR_NOFN(AB_1_0_PORT71, CF_CSB0, SEL_AB_1_0_10),
@ -514,7 +514,7 @@ static const u16 pinmux_data[] = {
/* GPSR3 */
/* M21 */
PINMUX_DATA(AB_A20_MARK, FN_AB_A20),
PINMUX_SINGLE(AB_A20),
/* N21 */
PINMUX_IPSR_NOFN(AB_9_8_PORT97, AB_A21, SEL_AB_9_8_00),
PINMUX_IPSR_NOFN(AB_9_8_PORT97, SDI2_CKO, SEL_AB_9_8_01),
@ -541,13 +541,13 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_NOFN(AB_13_12_PORT104, AB_A28, SEL_AB_13_12_00),
PINMUX_IPSR_NOFN(AB_13_12_PORT104, AB_BEN1, SEL_AB_13_12_10),
/* B8 */
PINMUX_DATA(USI0_CS1_MARK, FN_USI0_CS1),
PINMUX_SINGLE(USI0_CS1),
/* B9 */
PINMUX_DATA(USI0_CS2_MARK, FN_USI0_CS2),
PINMUX_SINGLE(USI0_CS2),
/* C10 */
PINMUX_DATA(USI1_DI_MARK, FN_USI1_DI),
PINMUX_SINGLE(USI1_DI),
/* D10 */
PINMUX_DATA(USI1_DO_MARK, FN_USI1_DO),
PINMUX_SINGLE(USI1_DO),
/* AB5 */
PINMUX_IPSR_NOFN(USI_1_0_PORT109, USI2_CLK, SEL_USI_1_0_00),
PINMUX_IPSR_NOFN(USI_1_0_PORT109, DTV_BCLK_B, SEL_USI_1_0_01),
@ -587,49 +587,49 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_NOFN(USI_9_8_PORT121, PWM1, SEL_USI_9_8_00),
PINMUX_IPSR_NOFN(USI_9_8_PORT121, USI4_DO, SEL_USI_9_8_01),
/* V20 */
PINMUX_DATA(NTSC_CLK_MARK, FN_NTSC_CLK),
PINMUX_SINGLE(NTSC_CLK),
/* P20 */
PINMUX_DATA(NTSC_DATA0_MARK, FN_NTSC_DATA0),
PINMUX_SINGLE(NTSC_DATA0),
/* P18 */
PINMUX_DATA(NTSC_DATA1_MARK, FN_NTSC_DATA1),
PINMUX_SINGLE(NTSC_DATA1),
/* R20 */
PINMUX_DATA(NTSC_DATA2_MARK, FN_NTSC_DATA2),
PINMUX_SINGLE(NTSC_DATA2),
/* R18 */
PINMUX_DATA(NTSC_DATA3_MARK, FN_NTSC_DATA3),
PINMUX_SINGLE(NTSC_DATA3),
/* T20 */
PINMUX_DATA(NTSC_DATA4_MARK, FN_NTSC_DATA4),
PINMUX_SINGLE(NTSC_DATA4),
/* GPRS3 */
/* T18 */
PINMUX_DATA(NTSC_DATA5_MARK, FN_NTSC_DATA5),
PINMUX_SINGLE(NTSC_DATA5),
/* U20 */
PINMUX_DATA(NTSC_DATA6_MARK, FN_NTSC_DATA6),
PINMUX_SINGLE(NTSC_DATA6),
/* U18 */
PINMUX_DATA(NTSC_DATA7_MARK, FN_NTSC_DATA7),
PINMUX_SINGLE(NTSC_DATA7),
/* W23 */
PINMUX_DATA(CAM_CLKO_MARK, FN_CAM_CLKO),
PINMUX_SINGLE(CAM_CLKO),
/* Y23 */
PINMUX_DATA(CAM_CLKI_MARK, FN_CAM_CLKI),
PINMUX_SINGLE(CAM_CLKI),
/* W22 */
PINMUX_DATA(CAM_VS_MARK, FN_CAM_VS),
PINMUX_SINGLE(CAM_VS),
/* V21 */
PINMUX_DATA(CAM_HS_MARK, FN_CAM_HS),
PINMUX_SINGLE(CAM_HS),
/* T21 */
PINMUX_DATA(CAM_YUV0_MARK, FN_CAM_YUV0),
PINMUX_SINGLE(CAM_YUV0),
/* T22 */
PINMUX_DATA(CAM_YUV1_MARK, FN_CAM_YUV1),
PINMUX_SINGLE(CAM_YUV1),
/* T23 */
PINMUX_DATA(CAM_YUV2_MARK, FN_CAM_YUV2),
PINMUX_SINGLE(CAM_YUV2),
/* U21 */
PINMUX_DATA(CAM_YUV3_MARK, FN_CAM_YUV3),
PINMUX_SINGLE(CAM_YUV3),
/* U22 */
PINMUX_DATA(CAM_YUV4_MARK, FN_CAM_YUV4),
PINMUX_SINGLE(CAM_YUV4),
/* U23 */
PINMUX_DATA(CAM_YUV5_MARK, FN_CAM_YUV5),
PINMUX_SINGLE(CAM_YUV5),
/* V22 */
PINMUX_DATA(CAM_YUV6_MARK, FN_CAM_YUV6),
PINMUX_SINGLE(CAM_YUV6),
/* V23 */
PINMUX_DATA(CAM_YUV7_MARK, FN_CAM_YUV7),
PINMUX_SINGLE(CAM_YUV7),
/* K22 */
PINMUX_IPSR_NOFN(HSI_1_0_PORT143, USI5_CLK_B, SEL_HSI_1_0_01),
/* K23 */
@ -647,17 +647,17 @@ static const u16 pinmux_data[] = {
/* M22 */
PINMUX_IPSR_NOFN(HSI_1_0_PORT150, USI5_DI_B, SEL_HSI_1_0_01),
/* D13 */
PINMUX_DATA(JT_TDO_MARK, FN_JT_TDO),
PINMUX_SINGLE(JT_TDO),
/* F13 */
PINMUX_DATA(JT_TDOEN_MARK, FN_JT_TDOEN),
PINMUX_SINGLE(JT_TDOEN),
/* AA12 */
PINMUX_DATA(USB_VBUS_MARK, FN_USB_VBUS),
PINMUX_SINGLE(USB_VBUS),
/* A12 */
PINMUX_DATA(LOWPWR_MARK, FN_LOWPWR),
PINMUX_SINGLE(LOWPWR),
/* Y11 */
PINMUX_DATA(UART1_RX_MARK, FN_UART1_RX),
PINMUX_SINGLE(UART1_RX),
/* Y10 */
PINMUX_DATA(UART1_TX_MARK, FN_UART1_TX),
PINMUX_SINGLE(UART1_TX),
/* AA10 */
PINMUX_IPSR_NOFN(UART_1_0_PORT157, UART1_CTSB, SEL_UART_1_0_00),
PINMUX_IPSR_NOFN(UART_1_0_PORT157, UART2_RX, SEL_UART_1_0_01),
@ -749,7 +749,7 @@ static const unsigned int cf_ctrl_mux[] = {
};
static const unsigned int cf_data8_pins[] = {
/* CF_D[0:8] */
/* CF_D[0:7] */
77, 78, 79, 80,
81, 82, 83, 84,
};

2
drivers/pinctrl/sh-pfc/pfc-r8a7740.c
View File

@ -2214,7 +2214,7 @@ static const unsigned int lcd1_data9_mux[] = {
LCD1_D8_MARK,
};
static const unsigned int lcd1_data12_pins[] = {
/* D[0:12] */
/* D[0:11] */
4, 3, 2, 1, 0, 91, 92, 23,
93, 94, 21, 201,
};

22
drivers/pinctrl/sh-pfc/pfc-r8a7778.c
View File

@ -548,17 +548,17 @@ enum {
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_DATA(PENC0_MARK, FN_PENC0),
PINMUX_DATA(PENC1_MARK, FN_PENC1),
PINMUX_DATA(A1_MARK, FN_A1),
PINMUX_DATA(A2_MARK, FN_A2),
PINMUX_DATA(A3_MARK, FN_A3),
PINMUX_DATA(WE0_MARK, FN_WE0),
PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA),
PINMUX_DATA(AUDIO_CLKB_MARK, FN_AUDIO_CLKB),
PINMUX_DATA(SSI_SCK34_MARK, FN_SSI_SCK34),
PINMUX_DATA(AVS1_MARK, FN_AVS1),
PINMUX_DATA(AVS2_MARK, FN_AVS2),
PINMUX_SINGLE(PENC0),
PINMUX_SINGLE(PENC1),
PINMUX_SINGLE(A1),
PINMUX_SINGLE(A2),
PINMUX_SINGLE(A3),
PINMUX_SINGLE(WE0),
PINMUX_SINGLE(AUDIO_CLKA),
PINMUX_SINGLE(AUDIO_CLKB),
PINMUX_SINGLE(SSI_SCK34),
PINMUX_SINGLE(AVS1),
PINMUX_SINGLE(AVS2),
/* IPSR0 */
PINMUX_IPSR_DATA(IP0_1_0, PRESETOUT),

21
drivers/pinctrl/sh-pfc/pfc-r8a7779.c
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@ -23,13 +23,6 @@
#include "sh_pfc.h"
#define PORT_GP_9(bank, fn, sfx) \
PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
PORT_GP_1(bank, 8, fn, sfx)
#define CPU_ALL_PORT(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_32(1, fn, sfx), \
@ -609,14 +602,14 @@ enum {
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_DATA(AVS1_MARK, FN_AVS1),
PINMUX_DATA(AVS1_MARK, FN_AVS1),
PINMUX_DATA(A17_MARK, FN_A17),
PINMUX_DATA(A18_MARK, FN_A18),
PINMUX_DATA(A19_MARK, FN_A19),
PINMUX_SINGLE(AVS1),
PINMUX_SINGLE(AVS1),
PINMUX_SINGLE(A17),
PINMUX_SINGLE(A18),
PINMUX_SINGLE(A19),
PINMUX_DATA(USB_PENC0_MARK, FN_USB_PENC0),
PINMUX_DATA(USB_PENC1_MARK, FN_USB_PENC1),
PINMUX_SINGLE(USB_PENC0),
PINMUX_SINGLE(USB_PENC1),
PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
PINMUX_IPSR_MSEL(IP0_2_0, SCK0, SEL_SCIF0_0),

35
drivers/pinctrl/sh-pfc/pfc-r8a7790.c
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@ -26,23 +26,6 @@
#include "core.h"
#include "sh_pfc.h"
#define PORT_GP_30(bank, fn, sfx) \
PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx)
#define CPU_ALL_PORT(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_30(1, fn, sfx), \
@ -806,15 +789,15 @@ enum {
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7),
PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS),
PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN),
PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC),
PINMUX_DATA(AVS1_MARK, FN_AVS1),
PINMUX_DATA(AVS2_MARK, FN_AVS2),
PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0),
PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2),
PINMUX_SINGLE(VI1_DATA7_VI1_B7),
PINMUX_SINGLE(USB0_PWEN),
PINMUX_SINGLE(USB0_OVC_VBUS),
PINMUX_SINGLE(USB2_PWEN),
PINMUX_SINGLE(USB2_OVC),
PINMUX_SINGLE(AVS1),
PINMUX_SINGLE(AVS2),
PINMUX_SINGLE(DU_DOTCLKIN0),
PINMUX_SINGLE(DU_DOTCLKIN2),
PINMUX_IPSR_DATA(IP0_2_0, D0),
PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),

74
drivers/pinctrl/sh-pfc/pfc-r8a7791.c
View File

@ -13,21 +13,6 @@
#include "core.h"
#include "sh_pfc.h"
#define PORT_GP_26(bank, fn, sfx) \
PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx)
#define CPU_ALL_PORT(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_26(1, fn, sfx), \
@ -787,23 +772,23 @@ enum {
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_DATA(EX_CS0_N_MARK, FN_EX_CS0_N),
PINMUX_DATA(RD_N_MARK, FN_RD_N),
PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA),
PINMUX_DATA(VI0_CLK_MARK, FN_VI0_CLK),
PINMUX_DATA(VI0_DATA0_VI0_B0_MARK, FN_VI0_DATA0_VI0_B0),
PINMUX_DATA(VI0_DATA1_VI0_B1_MARK, FN_VI0_DATA1_VI0_B1),
PINMUX_DATA(VI0_DATA2_VI0_B2_MARK, FN_VI0_DATA2_VI0_B2),
PINMUX_DATA(VI0_DATA4_VI0_B4_MARK, FN_VI0_DATA4_VI0_B4),
PINMUX_DATA(VI0_DATA5_VI0_B5_MARK, FN_VI0_DATA5_VI0_B5),
PINMUX_DATA(VI0_DATA6_VI0_B6_MARK, FN_VI0_DATA6_VI0_B6),
PINMUX_DATA(VI0_DATA7_VI0_B7_MARK, FN_VI0_DATA7_VI0_B7),
PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
PINMUX_DATA(DU0_DOTCLKIN_MARK, FN_DU0_DOTCLKIN),
PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK),
PINMUX_SINGLE(EX_CS0_N),
PINMUX_SINGLE(RD_N),
PINMUX_SINGLE(AUDIO_CLKA),
PINMUX_SINGLE(VI0_CLK),
PINMUX_SINGLE(VI0_DATA0_VI0_B0),
PINMUX_SINGLE(VI0_DATA1_VI0_B1),
PINMUX_SINGLE(VI0_DATA2_VI0_B2),
PINMUX_SINGLE(VI0_DATA4_VI0_B4),
PINMUX_SINGLE(VI0_DATA5_VI0_B5),
PINMUX_SINGLE(VI0_DATA6_VI0_B6),
PINMUX_SINGLE(VI0_DATA7_VI0_B7),
PINMUX_SINGLE(USB0_PWEN),
PINMUX_SINGLE(USB0_OVC),
PINMUX_SINGLE(USB1_PWEN),
PINMUX_SINGLE(USB1_OVC),
PINMUX_SINGLE(DU0_DOTCLKIN),
PINMUX_SINGLE(SD1_CLK),
/* IPSR0 */
PINMUX_IPSR_DATA(IP0_0, D0),
@ -3602,6 +3587,23 @@ static const unsigned int scifb2_data_d_pins[] = {
static const unsigned int scifb2_data_d_mux[] = {
SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
};
/* - SCIF Clock ------------------------------------------------------------- */
static const unsigned int scif_clk_pins[] = {
/* SCIF_CLK */
RCAR_GP_PIN(2, 29),
};
static const unsigned int scif_clk_mux[] = {
SCIF_CLK_MARK,
};
static const unsigned int scif_clk_b_pins[] = {
/* SCIF_CLK */
RCAR_GP_PIN(7, 19),
};
static const unsigned int scif_clk_b_mux[] = {
SCIF_CLK_B_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
@ -4510,6 +4512,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scifb2_data_c),
SH_PFC_PIN_GROUP(scifb2_clk_c),
SH_PFC_PIN_GROUP(scifb2_data_d),
SH_PFC_PIN_GROUP(scif_clk),
SH_PFC_PIN_GROUP(scif_clk_b),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
@ -4976,6 +4980,11 @@ static const char * const scifb2_groups[] = {
"scifb2_data_d",
};
static const char * const scif_clk_groups[] = {
"scif_clk",
"scif_clk_b",
};
static const char * const sdhi0_groups[] = {
"sdhi0_data1",
"sdhi0_data4",
@ -5126,6 +5135,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(scifb0),
SH_PFC_FUNCTION(scifb1),
SH_PFC_FUNCTION(scifb2),
SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(sdhi0),
SH_PFC_FUNCTION(sdhi1),
SH_PFC_FUNCTION(sdhi2),

63
drivers/pinctrl/sh-pfc/pfc-r8a7794.c
View File

@ -15,25 +15,6 @@
#include "core.h"
#include "sh_pfc.h"
#define PORT_GP_26(bank, fn, sfx) \
PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx)
#define PORT_GP_28(bank, fn, sfx) \
PORT_GP_26(bank, fn, sfx), \
PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx)
#define CPU_ALL_PORT(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_26(1, fn, sfx), \
@ -618,28 +599,28 @@ enum {
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_DATA(A2_MARK, FN_A2),
PINMUX_DATA(WE0_N_MARK, FN_WE0_N),
PINMUX_DATA(WE1_N_MARK, FN_WE1_N),
PINMUX_DATA(DACK0_MARK, FN_DACK0),
PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
PINMUX_DATA(SD0_CLK_MARK, FN_SD0_CLK),
PINMUX_DATA(SD0_CMD_MARK, FN_SD0_CMD),
PINMUX_DATA(SD0_DATA0_MARK, FN_SD0_DATA0),
PINMUX_DATA(SD0_DATA1_MARK, FN_SD0_DATA1),
PINMUX_DATA(SD0_DATA2_MARK, FN_SD0_DATA2),
PINMUX_DATA(SD0_DATA3_MARK, FN_SD0_DATA3),
PINMUX_DATA(SD0_CD_MARK, FN_SD0_CD),
PINMUX_DATA(SD0_WP_MARK, FN_SD0_WP),
PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK),
PINMUX_DATA(SD1_CMD_MARK, FN_SD1_CMD),
PINMUX_DATA(SD1_DATA0_MARK, FN_SD1_DATA0),
PINMUX_DATA(SD1_DATA1_MARK, FN_SD1_DATA1),
PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2),
PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3),
PINMUX_SINGLE(A2),
PINMUX_SINGLE(WE0_N),
PINMUX_SINGLE(WE1_N),
PINMUX_SINGLE(DACK0),
PINMUX_SINGLE(USB0_PWEN),
PINMUX_SINGLE(USB0_OVC),
PINMUX_SINGLE(USB1_PWEN),
PINMUX_SINGLE(USB1_OVC),
PINMUX_SINGLE(SD0_CLK),
PINMUX_SINGLE(SD0_CMD),
PINMUX_SINGLE(SD0_DATA0),
PINMUX_SINGLE(SD0_DATA1),
PINMUX_SINGLE(SD0_DATA2),
PINMUX_SINGLE(SD0_DATA3),
PINMUX_SINGLE(SD0_CD),
PINMUX_SINGLE(SD0_WP),
PINMUX_SINGLE(SD1_CLK),
PINMUX_SINGLE(SD1_CMD),
PINMUX_SINGLE(SD1_DATA0),
PINMUX_SINGLE(SD1_DATA1),
PINMUX_SINGLE(SD1_DATA2),
PINMUX_SINGLE(SD1_DATA3),
/* IPSR0 */
PINMUX_IPSR_DATA(IP0_0, SD1_CD),

1207
drivers/pinctrl/sh-pfc/pfc-r8a7795.c
View File

File diff suppressed because it is too large Load Diff

548
drivers/pinctrl/sh-pfc/pfc-sh73a0.c
View File

@ -2059,7 +2059,7 @@ static const unsigned int lcd2_data9_mux[] = {
LCD2D8_MARK,
};
static const unsigned int lcd2_data12_pins[] = {
/* D[0:12] */
/* D[0:11] */
128, 129, 142, 143, 144, 145, 138, 139,
140, 141, 130, 131,
};
@ -2198,6 +2198,420 @@ static const unsigned int mmc0_ctrl_1_pins[] = {
static const unsigned int mmc0_ctrl_1_mux[] = {
MMCCMD1_MARK, MMCCLK1_MARK,
};
/* - MSIOF0 ----------------------------------------------------------------- */
static const unsigned int msiof0_rsck_pins[] = {
/* RSCK */
66,
};
static const unsigned int msiof0_rsck_mux[] = {
MSIOF0_RSCK_MARK,
};
static const unsigned int msiof0_tsck_pins[] = {
/* TSCK */
64,
};
static const unsigned int msiof0_tsck_mux[] = {
MSIOF0_TSCK_MARK,
};
static const unsigned int msiof0_rsync_pins[] = {
/* RSYNC */
67,
};
static const unsigned int msiof0_rsync_mux[] = {
MSIOF0_RSYNC_MARK,
};
static const unsigned int msiof0_tsync_pins[] = {
/* TSYNC */
63,
};
static const unsigned int msiof0_tsync_mux[] = {
MSIOF0_TSYNC_MARK,
};
static const unsigned int msiof0_ss1_pins[] = {
/* SS1 */
62,
};
static const unsigned int msiof0_ss1_mux[] = {
MSIOF0_SS1_MARK,
};
static const unsigned int msiof0_ss2_pins[] = {
/* SS2 */
71,
};
static const unsigned int msiof0_ss2_mux[] = {
MSIOF0_SS2_MARK,
};
static const unsigned int msiof0_rxd_pins[] = {
/* RXD */
70,
};
static const unsigned int msiof0_rxd_mux[] = {
MSIOF0_RXD_MARK,
};
static const unsigned int msiof0_txd_pins[] = {
/* TXD */
65,
};
static const unsigned int msiof0_txd_mux[] = {
MSIOF0_TXD_MARK,
};
static const unsigned int msiof0_mck0_pins[] = {
/* MSCK0 */
68,
};
static const unsigned int msiof0_mck0_mux[] = {
MSIOF0_MCK0_MARK,
};
static const unsigned int msiof0_mck1_pins[] = {
/* MSCK1 */
69,
};
static const unsigned int msiof0_mck1_mux[] = {
MSIOF0_MCK1_MARK,
};
static const unsigned int msiof0l_rsck_pins[] = {
/* RSCK */
214,
};
static const unsigned int msiof0l_rsck_mux[] = {
MSIOF0L_RSCK_MARK,
};
static const unsigned int msiof0l_tsck_pins[] = {
/* TSCK */
219,
};
static const unsigned int msiof0l_tsck_mux[] = {
MSIOF0L_TSCK_MARK,
};
static const unsigned int msiof0l_rsync_pins[] = {
/* RSYNC */
215,
};
static const unsigned int msiof0l_rsync_mux[] = {
MSIOF0L_RSYNC_MARK,
};
static const unsigned int msiof0l_tsync_pins[] = {
/* TSYNC */
217,
};
static const unsigned int msiof0l_tsync_mux[] = {
MSIOF0L_TSYNC_MARK,
};
static const unsigned int msiof0l_ss1_a_pins[] = {
/* SS1 */
207,
};
static const unsigned int msiof0l_ss1_a_mux[] = {
PORT207_MSIOF0L_SS1_MARK,
};
static const unsigned int msiof0l_ss1_b_pins[] = {
/* SS1 */
210,
};
static const unsigned int msiof0l_ss1_b_mux[] = {
PORT210_MSIOF0L_SS1_MARK,
};
static const unsigned int msiof0l_ss2_a_pins[] = {
/* SS2 */
208,
};
static const unsigned int msiof0l_ss2_a_mux[] = {
PORT208_MSIOF0L_SS2_MARK,
};
static const unsigned int msiof0l_ss2_b_pins[] = {
/* SS2 */
211,
};
static const unsigned int msiof0l_ss2_b_mux[] = {
PORT211_MSIOF0L_SS2_MARK,
};
static const unsigned int msiof0l_rxd_pins[] = {
/* RXD */
221,
};
static const unsigned int msiof0l_rxd_mux[] = {
MSIOF0L_RXD_MARK,
};
static const unsigned int msiof0l_txd_pins[] = {
/* TXD */
222,
};
static const unsigned int msiof0l_txd_mux[] = {
MSIOF0L_TXD_MARK,
};
static const unsigned int msiof0l_mck0_pins[] = {
/* MSCK0 */
212,
};
static const unsigned int msiof0l_mck0_mux[] = {
MSIOF0L_MCK0_MARK,
};
static const unsigned int msiof0l_mck1_pins[] = {
/* MSCK1 */
213,
};
static const unsigned int msiof0l_mck1_mux[] = {
MSIOF0L_MCK1_MARK,
};
/* - MSIOF1 ----------------------------------------------------------------- */
static const unsigned int msiof1_rsck_pins[] = {
/* RSCK */
234,
};
static const unsigned int msiof1_rsck_mux[] = {
MSIOF1_RSCK_MARK,
};
static const unsigned int msiof1_tsck_pins[] = {
/* TSCK */
232,
};
static const unsigned int msiof1_tsck_mux[] = {
MSIOF1_TSCK_MARK,
};
static const unsigned int msiof1_rsync_pins[] = {
/* RSYNC */
235,
};
static const unsigned int msiof1_rsync_mux[] = {
MSIOF1_RSYNC_MARK,
};
static const unsigned int msiof1_tsync_pins[] = {
/* TSYNC */
231,
};
static const unsigned int msiof1_tsync_mux[] = {
MSIOF1_TSYNC_MARK,
};
static const unsigned int msiof1_ss1_pins[] = {
/* SS1 */
238,
};
static const unsigned int msiof1_ss1_mux[] = {
MSIOF1_SS1_MARK,
};
static const unsigned int msiof1_ss2_pins[] = {
/* SS2 */
239,
};
static const unsigned int msiof1_ss2_mux[] = {
MSIOF1_SS2_MARK,
};
static const unsigned int msiof1_rxd_pins[] = {
/* RXD */
233,
};
static const unsigned int msiof1_rxd_mux[] = {
MSIOF1_RXD_MARK,
};
static const unsigned int msiof1_txd_pins[] = {
/* TXD */
230,
};
static const unsigned int msiof1_txd_mux[] = {
MSIOF1_TXD_MARK,
};
static const unsigned int msiof1_mck0_pins[] = {
/* MSCK0 */
236,
};
static const unsigned int msiof1_mck0_mux[] = {
MSIOF1_MCK0_MARK,
};
static const unsigned int msiof1_mck1_pins[] = {
/* MSCK1 */
237,
};
static const unsigned int msiof1_mck1_mux[] = {
MSIOF1_MCK1_MARK,
};
/* - MSIOF2 ----------------------------------------------------------------- */
static const unsigned int msiof2_rsck_pins[] = {
/* RSCK */
151,
};
static const unsigned int msiof2_rsck_mux[] = {
MSIOF2_RSCK_MARK,
};
static const unsigned int msiof2_tsck_pins[] = {
/* TSCK */
135,
};
static const unsigned int msiof2_tsck_mux[] = {
MSIOF2_TSCK_MARK,
};
static const unsigned int msiof2_rsync_pins[] = {
/* RSYNC */
152,
};
static const unsigned int msiof2_rsync_mux[] = {
MSIOF2_RSYNC_MARK,
};
static const unsigned int msiof2_tsync_pins[] = {
/* TSYNC */
133,
};
static const unsigned int msiof2_tsync_mux[] = {
MSIOF2_TSYNC_MARK,
};
static const unsigned int msiof2_ss1_a_pins[] = {
/* SS1 */
131,
};
static const unsigned int msiof2_ss1_a_mux[] = {
PORT131_MSIOF2_SS1_MARK,
};
static const unsigned int msiof2_ss1_b_pins[] = {
/* SS1 */
153,
};
static const unsigned int msiof2_ss1_b_mux[] = {
PORT153_MSIOF2_SS1_MARK,
};
static const unsigned int msiof2_ss2_a_pins[] = {
/* SS2 */
132,
};
static const unsigned int msiof2_ss2_a_mux[] = {
PORT132_MSIOF2_SS2_MARK,
};
static const unsigned int msiof2_ss2_b_pins[] = {
/* SS2 */
156,
};
static const unsigned int msiof2_ss2_b_mux[] = {
PORT156_MSIOF2_SS2_MARK,
};
static const unsigned int msiof2_rxd_a_pins[] = {
/* RXD */
130,
};
static const unsigned int msiof2_rxd_a_mux[] = {
PORT130_MSIOF2_RXD_MARK,
};
static const unsigned int msiof2_rxd_b_pins[] = {
/* RXD */
157,
};
static const unsigned int msiof2_rxd_b_mux[] = {
PORT157_MSIOF2_RXD_MARK,
};
static const unsigned int msiof2_txd_pins[] = {
/* TXD */
134,
};
static const unsigned int msiof2_txd_mux[] = {
MSIOF2_TXD_MARK,
};
static const unsigned int msiof2_mck0_pins[] = {
/* MSCK0 */
154,
};
static const unsigned int msiof2_mck0_mux[] = {
MSIOF2_MCK0_MARK,
};
static const unsigned int msiof2_mck1_pins[] = {
/* MSCK1 */
155,
};
static const unsigned int msiof2_mck1_mux[] = {
MSIOF2_MCK1_MARK,
};
static const unsigned int msiof2r_tsck_pins[] = {
/* TSCK */
248,
};
static const unsigned int msiof2r_tsck_mux[] = {
MSIOF2R_TSCK_MARK,
};
static const unsigned int msiof2r_tsync_pins[] = {
/* TSYNC */
249,
};
static const unsigned int msiof2r_tsync_mux[] = {
MSIOF2R_TSYNC_MARK,
};
static const unsigned int msiof2r_rxd_pins[] = {
/* RXD */
244,
};
static const unsigned int msiof2r_rxd_mux[] = {
MSIOF2R_RXD_MARK,
};
static const unsigned int msiof2r_txd_pins[] = {
/* TXD */
245,
};
static const unsigned int msiof2r_txd_mux[] = {
MSIOF2R_TXD_MARK,
};
/* - MSIOF3 (Pin function name of MSIOF3 is named BBIF1) -------------------- */
static const unsigned int msiof3_rsck_pins[] = {
/* RSCK */
115,
};
static const unsigned int msiof3_rsck_mux[] = {
BBIF1_RSCK_MARK,
};
static const unsigned int msiof3_tsck_pins[] = {
/* TSCK */
112,
};
static const unsigned int msiof3_tsck_mux[] = {
BBIF1_TSCK_MARK,
};
static const unsigned int msiof3_rsync_pins[] = {
/* RSYNC */
116,
};
static const unsigned int msiof3_rsync_mux[] = {
BBIF1_RSYNC_MARK,
};
static const unsigned int msiof3_tsync_pins[] = {
/* TSYNC */
113,
};
static const unsigned int msiof3_tsync_mux[] = {
BBIF1_TSYNC_MARK,
};
static const unsigned int msiof3_ss1_pins[] = {
/* SS1 */
117,
};
static const unsigned int msiof3_ss1_mux[] = {
BBIF1_SS1_MARK,
};
static const unsigned int msiof3_ss2_pins[] = {
/* SS2 */
109,
};
static const unsigned int msiof3_ss2_mux[] = {
BBIF1_SS2_MARK,
};
static const unsigned int msiof3_rxd_pins[] = {
/* RXD */
111,
};
static const unsigned int msiof3_rxd_mux[] = {
BBIF1_RXD_MARK,
};
static const unsigned int msiof3_txd_pins[] = {
/* TXD */
114,
};
static const unsigned int msiof3_txd_mux[] = {
BBIF1_TXD_MARK,
};
static const unsigned int msiof3_flow_pins[] = {
/* FLOW */
117,
};
static const unsigned int msiof3_flow_mux[] = {
BBIF1_FLOW_MARK,
};
/* - SCIFA0 ----------------------------------------------------------------- */
static const unsigned int scifa0_data_pins[] = {
/* RXD, TXD */
@ -2782,6 +3196,64 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(mmc0_data4_1),
SH_PFC_PIN_GROUP(mmc0_data8_1),
SH_PFC_PIN_GROUP(mmc0_ctrl_1),
SH_PFC_PIN_GROUP(msiof0_rsck),
SH_PFC_PIN_GROUP(msiof0_tsck),
SH_PFC_PIN_GROUP(msiof0_rsync),
SH_PFC_PIN_GROUP(msiof0_tsync),
SH_PFC_PIN_GROUP(msiof0_ss1),
SH_PFC_PIN_GROUP(msiof0_ss2),
SH_PFC_PIN_GROUP(msiof0_rxd),
SH_PFC_PIN_GROUP(msiof0_txd),
SH_PFC_PIN_GROUP(msiof0_mck0),
SH_PFC_PIN_GROUP(msiof0_mck1),
SH_PFC_PIN_GROUP(msiof0l_rsck),
SH_PFC_PIN_GROUP(msiof0l_tsck),
SH_PFC_PIN_GROUP(msiof0l_rsync),
SH_PFC_PIN_GROUP(msiof0l_tsync),
SH_PFC_PIN_GROUP(msiof0l_ss1_a),
SH_PFC_PIN_GROUP(msiof0l_ss1_b),
SH_PFC_PIN_GROUP(msiof0l_ss2_a),
SH_PFC_PIN_GROUP(msiof0l_ss2_b),
SH_PFC_PIN_GROUP(msiof0l_rxd),
SH_PFC_PIN_GROUP(msiof0l_txd),
SH_PFC_PIN_GROUP(msiof0l_mck0),
SH_PFC_PIN_GROUP(msiof0l_mck1),
SH_PFC_PIN_GROUP(msiof1_rsck),
SH_PFC_PIN_GROUP(msiof1_tsck),
SH_PFC_PIN_GROUP(msiof1_rsync),
SH_PFC_PIN_GROUP(msiof1_tsync),
SH_PFC_PIN_GROUP(msiof1_ss1),
SH_PFC_PIN_GROUP(msiof1_ss2),
SH_PFC_PIN_GROUP(msiof1_rxd),
SH_PFC_PIN_GROUP(msiof1_txd),
SH_PFC_PIN_GROUP(msiof1_mck0),
SH_PFC_PIN_GROUP(msiof1_mck1),
SH_PFC_PIN_GROUP(msiof2_rsck),
SH_PFC_PIN_GROUP(msiof2_tsck),
SH_PFC_PIN_GROUP(msiof2_rsync),
SH_PFC_PIN_GROUP(msiof2_tsync),
SH_PFC_PIN_GROUP(msiof2_ss1_a),
SH_PFC_PIN_GROUP(msiof2_ss1_b),
SH_PFC_PIN_GROUP(msiof2_ss2_a),
SH_PFC_PIN_GROUP(msiof2_ss2_b),
SH_PFC_PIN_GROUP(msiof2_rxd_a),
SH_PFC_PIN_GROUP(msiof2_rxd_b),
SH_PFC_PIN_GROUP(msiof2_txd),
SH_PFC_PIN_GROUP(msiof2_mck0),
SH_PFC_PIN_GROUP(msiof2_mck1),
SH_PFC_PIN_GROUP(msiof2r_tsck),
SH_PFC_PIN_GROUP(msiof2r_tsync),
SH_PFC_PIN_GROUP(msiof2r_rxd),
SH_PFC_PIN_GROUP(msiof2r_txd),
SH_PFC_PIN_GROUP(msiof3_rsck),
SH_PFC_PIN_GROUP(msiof3_tsck),
SH_PFC_PIN_GROUP(msiof3_rsync),
SH_PFC_PIN_GROUP(msiof3_tsync),
SH_PFC_PIN_GROUP(msiof3_ss1),
SH_PFC_PIN_GROUP(msiof3_ss2),
SH_PFC_PIN_GROUP(msiof3_rxd),
SH_PFC_PIN_GROUP(msiof3_txd),
SH_PFC_PIN_GROUP(msiof3_flow),
SH_PFC_PIN_GROUP(scifa0_data),
SH_PFC_PIN_GROUP(scifa0_clk),
SH_PFC_PIN_GROUP(scifa0_ctrl),
@ -2982,6 +3454,76 @@ static const char * const mmc0_groups[] = {
"mmc0_ctrl_1",
};
static const char * const msiof0_groups[] = {
"msiof0_rsck",
"msiof0_tsck",
"msiof0_rsync",
"msiof0_tsync",
"msiof0_ss1",
"msiof0_ss2",
"msiof0_rxd",
"msiof0_txd",
"msiof0_mck0",
"msiof0_mck1",
"msiof0l_rsck",
"msiof0l_tsck",
"msiof0l_rsync",
"msiof0l_tsync",
"msiof0l_ss1_a",
"msiof0l_ss1_b",
"msiof0l_ss2_a",
"msiof0l_ss2_b",
"msiof0l_rxd",
"msiof0l_txd",
"msiof0l_mck0",
"msiof0l_mck1",
};
static const char * const msiof1_groups[] = {
"msiof1_rsck",
"msiof1_tsck",
"msiof1_rsync",
"msiof1_tsync",
"msiof1_ss1",
"msiof1_ss2",
"msiof1_rxd",
"msiof1_txd",
"msiof1_mck0",
"msiof1_mck1",
};
static const char * const msiof2_groups[] = {
"msiof2_rsck",
"msiof2_tsck",
"msiof2_rsync",
"msiof2_tsync",
"msiof2_ss1_a",
"msiof2_ss1_b",
"msiof2_ss2_a",
"msiof2_ss2_b",
"msiof2_rxd_a",
"msiof2_rxd_b",
"msiof2_txd",
"msiof2_mck0",
"msiof2_mck1",
"msiof2r_tsck",
"msiof2r_tsync",
"msiof2r_rxd",
"msiof2r_txd",
};
static const char * const msiof3_groups[] = {
"msiof3_rsck",
"msiof3_tsck",
"msiof3_rsync",
"msiof3_tsync",
"msiof3_ss1",
"msiof3_ss2",
"msiof3_rxd",
"msiof3_txd",
"msiof3_flow",
};
static const char * const scifa0_groups[] = {
"scifa0_data",
"scifa0_clk",
@ -3116,6 +3658,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(lcd),
SH_PFC_FUNCTION(lcd2),
SH_PFC_FUNCTION(mmc0),
SH_PFC_FUNCTION(msiof0),
SH_PFC_FUNCTION(msiof1),
SH_PFC_FUNCTION(msiof2),
SH_PFC_FUNCTION(msiof3),
SH_PFC_FUNCTION(scifa0),
SH_PFC_FUNCTION(scifa1),
SH_PFC_FUNCTION(scifa2),

29
drivers/pinctrl/sh-pfc/pfc-sh7734.c
View File

@ -14,14 +14,6 @@
#include "sh_pfc.h"
#define PORT_GP_12(bank, fn, sfx) \
PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx)
#define CPU_ALL_PORT(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_32(1, fn, sfx), \
@ -585,15 +577,18 @@ enum {
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_DATA(CLKOUT_MARK, FN_CLKOUT),
PINMUX_DATA(BS_MARK, FN_BS), PINMUX_DATA(CS0_MARK, FN_CS0),
PINMUX_DATA(EX_CS0_MARK, FN_EX_CS0),
PINMUX_DATA(RD_MARK, FN_RD), PINMUX_DATA(WE0_MARK, FN_WE0),
PINMUX_DATA(WE1_MARK, FN_WE1),
PINMUX_DATA(SCL0_MARK, FN_SCL0), PINMUX_DATA(PENC0_MARK, FN_PENC0),
PINMUX_DATA(USB_OVC0_MARK, FN_USB_OVC0),
PINMUX_DATA(IRQ2_B_MARK, FN_IRQ2_B),
PINMUX_DATA(IRQ3_B_MARK, FN_IRQ3_B),
PINMUX_SINGLE(CLKOUT),
PINMUX_SINGLE(BS),
PINMUX_SINGLE(CS0),
PINMUX_SINGLE(EX_CS0),
PINMUX_SINGLE(RD),
PINMUX_SINGLE(WE0),
PINMUX_SINGLE(WE1),
PINMUX_SINGLE(SCL0),
PINMUX_SINGLE(PENC0),
PINMUX_SINGLE(USB_OVC0),
PINMUX_SINGLE(IRQ2_B),
PINMUX_SINGLE(IRQ3_B),
/* IPSR0 */
PINMUX_IPSR_DATA(IP0_1_0, A0),

74
drivers/pinctrl/sh-pfc/sh_pfc.h
View File

@ -198,6 +198,14 @@ struct sh_pfc_soc_info {
#define PINMUX_IPSR_MSEL(ipsr, fn, ms) \
PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn)
/*
* Describe a pinmux configuration for a single-function pin with GPIO
* capability.
* - fn: Function name
*/
#define PINMUX_SINGLE(fn) \
PINMUX_DATA(fn##_MARK, FN_##fn)
/*
* GP port style (32 ports banks)
*/
@ -205,22 +213,68 @@ struct sh_pfc_soc_info {
#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), PORT_GP_CFG_1(bank, 3, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
PORT_GP_CFG_4(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), PORT_GP_CFG_1(bank, 7, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
#define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
#define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
PORT_GP_CFG_8(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
#define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
PORT_GP_CFG_8(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 8, fn, sfx, cfg), PORT_GP_CFG_1(bank, 9, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), PORT_GP_CFG_1(bank, 11, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), PORT_GP_CFG_1(bank, 13, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 14, fn, sfx, cfg), PORT_GP_CFG_1(bank, 15, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 16, fn, sfx, cfg), PORT_GP_CFG_1(bank, 17, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
PORT_GP_CFG_12(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
#define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
#define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
PORT_GP_CFG_14(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
#define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
#define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
PORT_GP_CFG_14(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 14, fn, sfx, cfg), PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
#define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
#define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
PORT_GP_CFG_16(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 16, fn, sfx, cfg), PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
#define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
PORT_GP_CFG_18(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 22, fn, sfx, cfg), PORT_GP_CFG_1(bank, 23, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), PORT_GP_CFG_1(bank, 25, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), PORT_GP_CFG_1(bank, 27, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 28, fn, sfx, cfg), PORT_GP_CFG_1(bank, 29, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
PORT_GP_CFG_26(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
#define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
#define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
PORT_GP_CFG_28(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 28, fn, sfx, cfg), PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
#define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
PORT_GP_CFG_30(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)