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clk: mvebu: armada-37xx-periph: add PCIe gated clock

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The PCIe clock is a gated clock which has the same source as GbE0
(both IPs share a set of registers). This source clock is called
'gbe_core' in the driver.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190627125245.26788-2-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Miquel Raynal 2019-06-27 14:52:42 +02:00 committed by Stephen Boyd
parent 54ecb8f702
commit 4d8fb49484
1 changed files with 2 additions and 0 deletions
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2
drivers/clk/mvebu/armada-37xx-periph.c
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@ -303,6 +303,7 @@ PERIPH_CLK_GATE_DIV(gbe_bm, 12, DIV_SEL1, 0, clk_table1);
PERIPH_CLK_FULL_DD(sdio, 11, 14, DIV_SEL0, DIV_SEL0, 3, 6);
PERIPH_CLK_FULL_DD(usb32_usb2_sys, 16, 16, DIV_SEL0, DIV_SEL0, 9, 12);
PERIPH_CLK_FULL_DD(usb32_ss_sys, 17, 18, DIV_SEL0, DIV_SEL0, 15, 18);
static PERIPH_GATE(pcie, 14);
static struct clk_periph_data data_sb[] = {
REF_CLK_MUX_DD(gbe_50),
@ -318,6 +319,7 @@ static struct clk_periph_data data_sb[] = {
REF_CLK_FULL_DD(sdio),
REF_CLK_FULL_DD(usb32_usb2_sys),
REF_CLK_FULL_DD(usb32_ss_sys),
REF_CLK_GATE(pcie, "gbe_core"),
{ },
};