Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-12-04 18:13:04 +00:00
Code Issues Packages Projects Releases Wiki Activity

clk: mediatek: mt8192: Add support for frequency hopping through FHCTL

Browse Source 
Add FHCTL parameters and register PLLs through FHCTL to add support
for frequency hopping and SSC. FHCTL will be enabled only on PLLs
specified in devicetree.

This commit brings functional changes only upon addition of
devicetree configuration.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230206100105.861720-7-angelogioacchino.delregno@collabora.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
AngeloGioacchino Del Regno 2023-02-06 11:01:04 +01:00 committed by Stephen Boyd
parent 45a5cbe05d
commit 4d586e10c4
1 changed files with 65 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

67
drivers/clk/mediatek/clk-mt8192.c
View File

@ -12,10 +12,12 @@
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "clk-fhctl.h"
#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-mux.h"
#include "clk-pll.h"
#include "clk-pllfh.h"
#include <dt-bindings/clock/mt8192-clk.h>
#include <dt-bindings/reset/mt8192-resets.h>
@ -1042,6 +1044,57 @@ static const struct mtk_pll_data plls[] = {
0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0),
};
enum fh_pll_id {
FH_ARMPLL_LL,
FH_ARMPLL_BL0,
FH_ARMPLL_BL1,
FH_ARMPLL_BL2,
FH_ARMPLL_BL3,
FH_CCIPLL,
FH_MFGPLL,
FH_MEMPLL,
FH_MPLL,
FH_MMPLL,
FH_MAINPLL,
FH_MSDCPLL,
FH_ADSPPLL,
FH_APUPLL,
FH_TVDPLL,
FH_NR_FH,
};
#define FH(_pllid, _fhid, _offset) { \
.data = { \
.pll_id = _pllid, \
.fh_id = _fhid, \
.fh_ver = FHCTL_PLLFH_V2, \
.fhx_offset = _offset, \
.dds_mask = GENMASK(21, 0), \
.slope0_value = 0x6003c97, \
.slope1_value = 0x6003c97, \
.sfstrx_en = BIT(2), \
.frddsx_en = BIT(1), \
.fhctlx_en = BIT(0), \
.tgl_org = BIT(31), \
.dvfs_tri = BIT(31), \
.pcwchg = BIT(31), \
.dt_val = 0x0, \
.df_val = 0x9, \
.updnlmt_shft = 16, \
.msk_frddsx_dys = GENMASK(23, 20), \
.msk_frddsx_dts = GENMASK(19, 16), \
}, \
}
static struct mtk_pllfh_data pllfhs[] = {
FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4),
FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0),
FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104),
FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118),
FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x12c),
FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x154),
};
/* Register mux notifier for MFG mux */
static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
{
@ -1068,17 +1121,24 @@ static int clk_mt8192_apmixed_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
const u8 *fhctl_node = "mediatek,mt8192-fhctl";
int r;
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
if (!clk_data)
return -ENOMEM;
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
pllfhs, ARRAY_SIZE(pllfhs), clk_data);
if (r)
goto free_clk_data;
r = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
ARRAY_SIZE(apmixed_clks), clk_data);
if (r)
goto free_clk_data;
goto unregister_plls;
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
@ -1088,6 +1148,9 @@ static int clk_mt8192_apmixed_probe(struct platform_device *pdev)
unregister_gates:
mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
unregister_plls:
mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
ARRAY_SIZE(pllfhs), clk_data);
free_clk_data:
mtk_free_clk_data(clk_data);
return r;