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Blackfin EMAC driver: Add phy abstraction layer supporting in bfin_emac driver
- add MDIO functions and register mdio bus - add phy abstraction layer (PAL) functions and use PAL API - test on STAMP537 board Signed-off-by: Bryan Wu <bryan.wu@analog.com> Acked-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Bryan Wu
David S. Miller
parent
496a34c224
commit
4ae5a3ad5a
@ -47,6 +47,7 @@
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#include <linux/spinlock.h>
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#include <linux/ethtool.h>
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#include <linux/mii.h>
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#include <linux/phy.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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@ -94,6 +95,9 @@ static struct net_dma_desc_tx *current_tx_ptr;
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static struct net_dma_desc_tx *tx_desc;
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static struct net_dma_desc_rx *rx_desc;
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static void bf537mac_disable(void);
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static void bf537mac_enable(void);
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static void desc_list_free(void)
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{
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struct net_dma_desc_rx *r;
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@ -282,8 +286,11 @@ static int setup_pin_mux(int action)
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return 0;
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}
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/*
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* MII operations
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*/
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/* Wait until the previous MDC/MDIO transaction has completed */
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static void poll_mdc_done(void)
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static void mdio_poll(void)
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{
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int timeout_cnt = MAX_TIMEOUT_CNT;
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@ -299,154 +306,201 @@ static void poll_mdc_done(void)
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}
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/* Read an off-chip register in a PHY through the MDC/MDIO port */
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static u16 read_phy_reg(u16 PHYAddr, u16 RegAddr)
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static int mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
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{
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poll_mdc_done();
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/* read mode */
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bfin_write_EMAC_STAADD(SET_PHYAD(PHYAddr) |
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SET_REGAD(RegAddr) |
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STABUSY);
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poll_mdc_done();
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mdio_poll();
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return (u16) bfin_read_EMAC_STADAT();
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/* read mode */
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bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
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SET_REGAD((u16) regnum) |
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STABUSY);
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mdio_poll();
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return (int) bfin_read_EMAC_STADAT();
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}
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/* Write an off-chip register in a PHY through the MDC/MDIO port */
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static void raw_write_phy_reg(u16 PHYAddr, u16 RegAddr, u32 Data)
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static int mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
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u16 value)
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{
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bfin_write_EMAC_STADAT(Data);
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mdio_poll();
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bfin_write_EMAC_STADAT((u32) value);
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/* write mode */
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bfin_write_EMAC_STAADD(SET_PHYAD(PHYAddr) |
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SET_REGAD(RegAddr) |
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bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
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SET_REGAD((u16) regnum) |
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STAOP |
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STABUSY);
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poll_mdc_done();
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mdio_poll();
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return 0;
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}
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static void write_phy_reg(u16 PHYAddr, u16 RegAddr, u32 Data)
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static int mdiobus_reset(struct mii_bus *bus)
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{
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poll_mdc_done();
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raw_write_phy_reg(PHYAddr, RegAddr, Data);
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return 0;
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}
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/* set up the phy */
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static void bf537mac_setphy(struct net_device *dev)
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static void bf537_adjust_link(struct net_device *dev)
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{
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u16 phydat;
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struct bf537mac_local *lp = netdev_priv(dev);
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struct phy_device *phydev = lp->phydev;
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unsigned long flags;
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int new_state = 0;
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/* Program PHY registers */
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pr_debug("start setting up phy\n");
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spin_lock_irqsave(&lp->lock, flags);
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if (phydev->link) {
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/* Now we make sure that we can be in full duplex mode.
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* If not, we operate in half-duplex mode. */
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if (phydev->duplex != lp->old_duplex) {
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u32 opmode = bfin_read_EMAC_OPMODE();
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new_state = 1;
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/* issue a reset */
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raw_write_phy_reg(lp->PhyAddr, PHYREG_MODECTL, 0x8000);
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if (phydev->duplex)
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opmode |= FDMODE;
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else
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opmode &= ~(FDMODE);
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/* wait half a second */
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msleep(500);
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bfin_write_EMAC_OPMODE(opmode);
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lp->old_duplex = phydev->duplex;
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}
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phydat = read_phy_reg(lp->PhyAddr, PHYREG_MODECTL);
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if (phydev->speed != lp->old_speed) {
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#if defined(CONFIG_BFIN_MAC_RMII)
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u32 opmode = bfin_read_EMAC_OPMODE();
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bf537mac_disable();
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switch (phydev->speed) {
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case 10:
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opmode |= RMII_10;
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break;
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case 100:
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opmode &= ~(RMII_10);
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break;
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default:
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printk(KERN_WARNING
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"%s: Ack! Speed (%d) is not 10/100!\n",
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DRV_NAME, phydev->speed);
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break;
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}
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bfin_write_EMAC_OPMODE(opmode);
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bf537mac_enable();
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#endif
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/* advertise flow control supported */
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phydat = read_phy_reg(lp->PhyAddr, PHYREG_ANAR);
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phydat |= (1 << 10);
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write_phy_reg(lp->PhyAddr, PHYREG_ANAR, phydat);
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new_state = 1;
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lp->old_speed = phydev->speed;
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}
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phydat = 0;
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if (lp->Negotiate)
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phydat |= 0x1000; /* enable auto negotiation */
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else {
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if (lp->FullDuplex)
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phydat |= (1 << 8); /* full duplex */
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else
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phydat &= (~(1 << 8)); /* half duplex */
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if (!lp->Port10)
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phydat |= (1 << 13); /* 100 Mbps */
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else
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phydat &= (~(1 << 13)); /* 10 Mbps */
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if (!lp->old_link) {
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new_state = 1;
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lp->old_link = 1;
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netif_schedule(dev);
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}
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} else if (lp->old_link) {
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new_state = 1;
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lp->old_link = 0;
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lp->old_speed = 0;
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lp->old_duplex = -1;
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}
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if (lp->Loopback)
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phydat |= (1 << 14); /* enable TX->RX loopback */
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write_phy_reg(lp->PhyAddr, PHYREG_MODECTL, phydat);
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msleep(500);
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phydat = read_phy_reg(lp->PhyAddr, PHYREG_MODECTL);
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/* check for SMSC PHY */
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if ((read_phy_reg(lp->PhyAddr, PHYREG_PHYID1) == 0x7) &&
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((read_phy_reg(lp->PhyAddr, PHYREG_PHYID2) & 0xfff0) == 0xC0A0)) {
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/*
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* we have SMSC PHY so reqest interrupt
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* on link down condition
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*/
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/* enable interrupts */
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write_phy_reg(lp->PhyAddr, 30, 0x0ff);
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if (new_state) {
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u32 opmode = bfin_read_EMAC_OPMODE();
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phy_print_status(phydev);
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pr_debug("EMAC_OPMODE = 0x%08x\n", opmode);
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}
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spin_unlock_irqrestore(&lp->lock, flags);
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}
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static int mii_probe(struct net_device *dev)
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{
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struct bf537mac_local *lp = netdev_priv(dev);
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struct phy_device *phydev = NULL;
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unsigned short sysctl;
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int i;
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/* Enable PHY output early */
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if (!(bfin_read_VR_CTL() & PHYCLKOE))
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bfin_write_VR_CTL(bfin_read_VR_CTL() | PHYCLKOE);
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/* MDC = 2.5 MHz */
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sysctl = bfin_read_EMAC_SYSCTL();
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sysctl |= SET_MDCDIV(24);
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bfin_write_EMAC_SYSCTL(sysctl);
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/* search for connect PHY device */
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for (i = 0; i < PHY_MAX_ADDR; i++) {
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struct phy_device *const tmp_phydev = lp->mii_bus.phy_map[i];
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if (!tmp_phydev)
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continue; /* no PHY here... */
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phydev = tmp_phydev;
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break; /* found it */
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}
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/* now we are supposed to have a proper phydev, to attach to... */
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if (!phydev) {
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printk(KERN_INFO "%s: Don't found any phy device at all\n",
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dev->name);
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return -ENODEV;
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}
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#if defined(CONFIG_BFIN_MAC_RMII)
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phydev = phy_connect(dev, phydev->dev.bus_id, &bf537_adjust_link, 0,
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PHY_INTERFACE_MODE_RMII);
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#else
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phydev = phy_connect(dev, phydev->dev.bus_id, &bf537_adjust_link, 0,
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PHY_INTERFACE_MODE_MII);
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#endif
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if (IS_ERR(phydev)) {
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printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
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return PTR_ERR(phydev);
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}
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/* mask with MAC supported features */
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phydev->supported &= (SUPPORTED_10baseT_Half
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| SUPPORTED_10baseT_Full
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| SUPPORTED_100baseT_Half
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| SUPPORTED_100baseT_Full
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| SUPPORTED_Autoneg
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| SUPPORTED_Pause | SUPPORTED_Asym_Pause
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| SUPPORTED_MII
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| SUPPORTED_TP);
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phydev->advertising = phydev->supported;
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lp->old_link = 0;
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lp->old_speed = 0;
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lp->old_duplex = -1;
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lp->phydev = phydev;
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printk(KERN_INFO "%s: attached PHY driver [%s] "
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"(mii_bus:phy_addr=%s, irq=%d)\n",
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DRV_NAME, phydev->drv->name, phydev->dev.bus_id, phydev->irq);
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return 0;
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}
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/**************************************************************************/
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void setup_system_regs(struct net_device *dev)
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{
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int phyaddr;
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unsigned short sysctl, phydat;
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u32 opmode;
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struct bf537mac_local *lp = netdev_priv(dev);
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int count = 0;
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unsigned short sysctl;
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phyaddr = lp->PhyAddr;
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/* Enable PHY output */
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if (!(bfin_read_VR_CTL() & PHYCLKOE))
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bfin_write_VR_CTL(bfin_read_VR_CTL() | PHYCLKOE);
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/* MDC = 2.5 MHz */
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sysctl = SET_MDCDIV(24);
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/* Odd word alignment for Receive Frame DMA word */
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/* Configure checksum support and rcve frame word alignment */
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/*
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* Odd word alignment for Receive Frame DMA word
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* Configure checksum support and rcve frame word alignment
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*/
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sysctl = bfin_read_EMAC_SYSCTL();
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#if defined(BFIN_MAC_CSUM_OFFLOAD)
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sysctl |= RXDWA | RXCKS;
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#else
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sysctl |= RXDWA;
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#endif
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bfin_write_EMAC_SYSCTL(sysctl);
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/* auto negotiation on */
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/* full duplex */
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/* 100 Mbps */
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phydat = PHY_ANEG_EN | PHY_DUPLEX | PHY_SPD_SET;
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write_phy_reg(phyaddr, PHYREG_MODECTL, phydat);
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/* test if full duplex supported */
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do {
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msleep(100);
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phydat = read_phy_reg(phyaddr, PHYREG_MODESTAT);
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if (count > 30) {
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printk(KERN_NOTICE DRV_NAME ": Link is down\n");
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printk(KERN_NOTICE DRV_NAME
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"please check your network connection\n");
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break;
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}
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count++;
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} while (!(phydat & 0x0004));
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phydat = read_phy_reg(phyaddr, PHYREG_ANLPAR);
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if ((phydat & 0x0100) || (phydat & 0x0040)) {
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opmode = FDMODE;
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} else {
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opmode = 0;
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printk(KERN_INFO DRV_NAME
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": Network is set to half duplex\n");
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}
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#if defined(CONFIG_BFIN_MAC_RMII)
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opmode |= RMII; /* For Now only 100MBit are supported */
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#endif
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bfin_write_EMAC_OPMODE(opmode);
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bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
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@ -686,18 +740,18 @@ static void bf537mac_disable(void)
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/*
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* Enable Interrupts, Receive, and Transmit
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*/
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static int bf537mac_enable(struct net_device *dev)
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static void bf537mac_enable(void)
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{
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u32 opmode;
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pr_debug("%s: %s\n", dev->name, __FUNCTION__);
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pr_debug("%s: %s\n", DRV_NAME, __FUNCTION__);
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/* Set RX DMA */
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bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a));
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bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config);
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/* Wait MII done */
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poll_mdc_done();
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mdio_poll();
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/* We enable only RX here */
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/* ASTP : Enable Automatic Pad Stripping
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@ -721,8 +775,6 @@ static int bf537mac_enable(struct net_device *dev)
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#endif
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/* Turn on the EMAC rx */
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bfin_write_EMAC_OPMODE(opmode);
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return 0;
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}
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/* Our watchdog timed out. Called by the networking layer */
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@ -735,7 +787,7 @@ static void bf537mac_timeout(struct net_device *dev)
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/* reset tx queue */
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tx_list_tail = tx_list_head->next;
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bf537mac_enable(dev);
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bf537mac_enable();
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/* We can accept TX packets again */
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dev->trans_start = jiffies;
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@ -789,6 +841,7 @@ static void bf537mac_shutdown(struct net_device *dev)
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*/
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static int bf537mac_open(struct net_device *dev)
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{
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struct bf537mac_local *lp = netdev_priv(dev);
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int retval;
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pr_debug("%s: %s\n", dev->name, __FUNCTION__);
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@ -808,10 +861,10 @@ static int bf537mac_open(struct net_device *dev)
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if (retval)
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return retval;
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bf537mac_setphy(dev);
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phy_start(lp->phydev);
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setup_system_regs(dev);
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bf537mac_disable();
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bf537mac_enable(dev);
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bf537mac_enable();
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pr_debug("hardware init finished\n");
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netif_start_queue(dev);
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@ -828,11 +881,14 @@ static int bf537mac_open(struct net_device *dev)
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*/
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static int bf537mac_close(struct net_device *dev)
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{
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struct bf537mac_local *lp = netdev_priv(dev);
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pr_debug("%s: %s\n", dev->name, __FUNCTION__);
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netif_stop_queue(dev);
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netif_carrier_off(dev);
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phy_stop(lp->phydev);
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/* clear everything */
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bf537mac_shutdown(dev);
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@ -846,6 +902,7 @@ static int __init bf537mac_probe(struct net_device *dev)
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{
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struct bf537mac_local *lp = netdev_priv(dev);
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int retval;
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int i;
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/* Grab the MAC address in the MAC */
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*(__le32 *) (&(dev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO());
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@ -862,7 +919,6 @@ static int __init bf537mac_probe(struct net_device *dev)
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/* set the GPIO pins to Ethernet mode */
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retval = setup_pin_mux(1);
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if (retval)
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return retval;
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@ -880,6 +936,23 @@ static int __init bf537mac_probe(struct net_device *dev)
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setup_mac_addr(dev->dev_addr);
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/* MDIO bus initial */
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lp->mii_bus.priv = dev;
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lp->mii_bus.read = mdiobus_read;
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lp->mii_bus.write = mdiobus_write;
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lp->mii_bus.reset = mdiobus_reset;
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lp->mii_bus.name = "bfin_mac_mdio";
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lp->mii_bus.id = 0;
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lp->mii_bus.irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
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for (i = 0; i < PHY_MAX_ADDR; ++i)
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lp->mii_bus.irq[i] = PHY_POLL;
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mdiobus_register(&lp->mii_bus);
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retval = mii_probe(dev);
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if (retval)
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return retval;
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/* Fill in the fields of the device structure with ethernet values. */
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ether_setup(dev);
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@ -893,13 +966,6 @@ static int __init bf537mac_probe(struct net_device *dev)
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dev->poll_controller = bf537mac_poll;
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#endif
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/* fill in some of the fields */
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lp->version = 1;
|
||||
lp->PhyAddr = 0x01;
|
||||
lp->CLKIN = 25;
|
||||
lp->FullDuplex = 0;
|
||||
lp->Negotiate = 1;
|
||||
lp->FlowControl = 0;
|
||||
spin_lock_init(&lp->lock);
|
||||
|
||||
/* now, enable interrupts */
|
||||
@ -912,9 +978,6 @@ static int __init bf537mac_probe(struct net_device *dev)
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
/* Enable PHY output early */
|
||||
if (!(bfin_read_VR_CTL() & PHYCLKOE))
|
||||
bfin_write_VR_CTL(bfin_read_VR_CTL() | PHYCLKOE);
|
||||
|
||||
retval = register_netdev(dev);
|
||||
if (retval == 0) {
|
||||
|
||||
@ -31,32 +31,6 @@
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
/*
|
||||
* PHY REGISTER NAMES
|
||||
*/
|
||||
#define PHYREG_MODECTL 0x0000
|
||||
#define PHYREG_MODESTAT 0x0001
|
||||
#define PHYREG_PHYID1 0x0002
|
||||
#define PHYREG_PHYID2 0x0003
|
||||
#define PHYREG_ANAR 0x0004
|
||||
#define PHYREG_ANLPAR 0x0005
|
||||
#define PHYREG_ANER 0x0006
|
||||
#define PHYREG_NSR 0x0010
|
||||
#define PHYREG_LBREMR 0x0011
|
||||
#define PHYREG_REC 0x0012
|
||||
#define PHYREG_10CFG 0x0013
|
||||
#define PHYREG_PHY1_1 0x0014
|
||||
#define PHYREG_PHY1_2 0x0015
|
||||
#define PHYREG_PHY2 0x0016
|
||||
#define PHYREG_TW_1 0x0017
|
||||
#define PHYREG_TW_2 0x0018
|
||||
#define PHYREG_TEST 0x0019
|
||||
|
||||
#define PHY_RESET 0x8000
|
||||
#define PHY_ANEG_EN 0x1000
|
||||
#define PHY_DUPLEX 0x0100
|
||||
#define PHY_SPD_SET 0x2000
|
||||
|
||||
#define BFIN_MAC_CSUM_OFFLOAD
|
||||
|
||||
struct dma_descriptor {
|
||||
@ -104,27 +78,18 @@ struct bf537mac_local {
|
||||
* can find out semi-useless statistics of how well the card is
|
||||
* performing
|
||||
*/
|
||||
int version;
|
||||
struct net_device_stats stats;
|
||||
|
||||
int FlowEnabled; /* record if data flow is active */
|
||||
int EtherIntIVG; /* IVG for the ethernet interrupt */
|
||||
int RXIVG; /* IVG for the RX completion */
|
||||
int TXIVG; /* IVG for the TX completion */
|
||||
int PhyAddr; /* PHY address */
|
||||
int OpMode; /* set these bits n the OPMODE regs */
|
||||
int Port10; /* set port speed to 10 Mbit/s */
|
||||
int GenChksums; /* IP checksums to be calculated */
|
||||
int NoRcveLnth; /* dont insert recv length at start of buffer */
|
||||
int StripPads; /* remove trailing pad bytes */
|
||||
int FullDuplex; /* set full duplex mode */
|
||||
int Negotiate; /* enable auto negotiation */
|
||||
int Loopback; /* loopback at the PHY */
|
||||
int Cache; /* Buffers may be cached */
|
||||
int FlowControl; /* flow control active */
|
||||
int CLKIN; /* clock in value in MHZ */
|
||||
unsigned short IntMask; /* interrupt mask */
|
||||
unsigned char Mac[6]; /* MAC address of the board */
|
||||
spinlock_t lock;
|
||||
|
||||
/* MII and PHY stuffs */
|
||||
int old_link; /* used by bf537_adjust_link */
|
||||
int old_speed;
|
||||
int old_duplex;
|
||||
|
||||
struct phy_device *phydev;
|
||||
struct mii_bus mii_bus;
|
||||
};
|
||||
|
||||
extern void get_bf537_ether_addr(char *addr);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user