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ARM: Fix wrong register in proc-arm6_7.S data abort handler
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -41,7 +41,7 @@ ENTRY(cpu_arm7_dcache_clean_area)
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ENTRY(cpu_arm7_data_abort)
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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ldr r8, [r0] @ read arm instruction
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ldr r8, [r2] @ read arm instruction
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tst r8, #1 << 20 @ L = 0 -> write?
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orreq r1, r1, #1 << 11 @ yes.
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and r7, r8, #15 << 24
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