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arm64: socfpga: merge Agilex and N5X into ARCH_INTEL_SOCFPGA
Agilex, N5X and Stratix 10 share all quite similar arm64 hard cores and SoC-part. Up to a point that N5X uses the same DTSI as Agilex. From the Linux kernel point of view these are flavors of the same architecture so there is no need for three top-level arm64 architectures. Simplify this by merging all three architectures into ARCH_INTEL_SOCFPGA and dropping the other ARCH* arm64 Kconfig entries. The side effect is that the INTEL_STRATIX10_SERVICE will now be available for both 32-bit and 64-bit Intel SoCFPGA, even though it is used only for 64-bit. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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@ -8,16 +8,6 @@ config ARCH_ACTIONS
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help
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This enables support for the Actions Semiconductor S900 SoC family.
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config ARCH_AGILEX
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bool "Intel's Agilex SoCFPGA Family"
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help
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This enables support for Intel's Agilex SoCFPGA Family.
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config ARCH_N5X
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bool "Intel's eASIC N5X SoCFPGA Family"
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help
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This enables support for Intel's eASIC N5X SoCFPGA Family.
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config ARCH_SUNXI
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bool "Allwinner sunxi 64-bit SoC Family"
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select ARCH_HAS_RESET_CONTROLLER
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@ -254,14 +244,11 @@ config ARCH_SEATTLE
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help
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This enables support for AMD Seattle SOC Family
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config ARCH_STRATIX10
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bool "Altera's Stratix 10 SoCFPGA Family"
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select ARCH_INTEL_SOCFPGA
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help
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This enables support for Altera's Stratix 10 SoCFPGA Family.
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config ARCH_INTEL_SOCFPGA
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bool
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bool "Intel's SoCFPGA ARMv8 Families"
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help
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This enables support for Intel's SoCFPGA ARMv8 families:
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Stratix 10 (ex. Altera), Agilex and eASIC N5X.
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config ARCH_SYNQUACER
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bool "Socionext SynQuacer SoC Family"
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@ -1,5 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0-only
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dtb-$(CONFIG_ARCH_AGILEX) += socfpga_agilex_socdk.dtb \
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socfpga_agilex_socdk_nand.dtb
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dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_socdk.dtb \
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socfpga_agilex_socdk_nand.dtb \
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socfpga_n5x_socdk.dtb
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dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
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dtb-$(CONFIG_ARCH_N5X) += socfpga_n5x_socdk.dtb
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@ -50,7 +50,7 @@ CONFIG_ARCH_RENESAS=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_ARCH_S32=y
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CONFIG_ARCH_SEATTLE=y
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CONFIG_ARCH_STRATIX10=y
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CONFIG_ARCH_INTEL_SOCFPGA=y
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CONFIG_ARCH_SYNQUACER=y
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CONFIG_ARCH_TEGRA=y
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CONFIG_ARCH_SPRD=y
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@ -105,8 +105,6 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
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obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
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obj-$(CONFIG_CLK_SIFIVE) += sifive/
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obj-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga/
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obj-$(CONFIG_ARCH_AGILEX) += socfpga/
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obj-$(CONFIG_ARCH_N5X) += socfpga/
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obj-$(CONFIG_PLAT_SPEAR) += spear/
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obj-y += sprd/
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obj-$(CONFIG_ARCH_STI) += st/
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@ -2,5 +2,5 @@
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config CLK_INTEL_SOCFPGA64
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bool
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# Intel Stratix / Agilex / N5X clock controller support
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default (ARCH_AGILEX || ARCH_N5X || ARCH_STRATIX10)
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depends on ARCH_AGILEX || ARCH_N5X || ARCH_STRATIX10
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default ARM64 && ARCH_INTEL_SOCFPGA
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depends on ARM64 && ARCH_INTEL_SOCFPGA
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@ -206,7 +206,7 @@ config FW_CFG_SYSFS_CMDLINE
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config INTEL_STRATIX10_SERVICE
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tristate "Intel Stratix10 Service Layer"
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depends on (ARCH_STRATIX10 || ARCH_AGILEX) && HAVE_ARM_SMCCC
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depends on ARCH_INTEL_SOCFPGA && HAVE_ARM_SMCCC
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default n
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help
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Intel Stratix10 service layer runs at privileged exception level,
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@ -60,7 +60,7 @@ config FPGA_MGR_ZYNQ_FPGA
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config FPGA_MGR_STRATIX10_SOC
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tristate "Intel Stratix10 SoC FPGA Manager"
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depends on (ARCH_STRATIX10 && INTEL_STRATIX10_SERVICE)
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depends on (ARCH_INTEL_SOCFPGA && INTEL_STRATIX10_SERVICE)
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help
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FPGA manager driver support for the Intel Stratix10 SoC.
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@ -183,7 +183,7 @@ config RESET_SCMI
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config RESET_SIMPLE
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bool "Simple Reset Controller Driver" if COMPILE_TEST
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default ARCH_AGILEX || ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARC
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default ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
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help
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This enables a simple reset controller driver for reset lines that
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that can be asserted and deasserted by toggling bits in a contiguous,
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