Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-11-28 23:21:31 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'next/misc' into for-next

Browse Source
This commit is contained in:
Paul Walmsley 2019-11-22 18:58:34 -08:00
commit 4a979862dd
18 changed files with 63 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/riscv/boot/Makefile
View File

@ -24,6 +24,18 @@ $(obj)/Image: vmlinux FORCE
$(obj)/Image.gz: $(obj)/Image FORCE
$(call if_changed,gzip)
$(obj)/Image.bz2: $(obj)/Image FORCE
$(call if_changed,bzip2)
$(obj)/Image.lz4: $(obj)/Image FORCE
$(call if_changed,lz4)
$(obj)/Image.lzma: $(obj)/Image FORCE
$(call if_changed,lzma)
$(obj)/Image.lzo: $(obj)/Image FORCE
$(call if_changed,lzo)
install:
$(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
$(obj)/Image System.map "$(INSTALL_PATH)"

7
arch/riscv/boot/dts/sifive/fu540-c000.dtsi
View File

@ -162,6 +162,13 @@
clocks = <&prci PRCI_CLK_TLCLK>;
status = "disabled";
};
dma: dma@3000000 {
compatible = "sifive,fu540-c000-pdma";
reg = <0x0 0x3000000 0x0 0x8000>;
interrupt-parent = <&plic0>;
interrupts = <23 24 25 26 27 28 29 30>;
#dma-cells = <1>;
};
uart1: serial@10011000 {
compatible = "sifive,fu540-c000-uart", "sifive,uart0";
reg = <0x0 0x10011000 0x0 0x1000>;

1
arch/riscv/include/asm/asm-prototypes.h
View File

@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_RISCV_PROTOTYPES_H
#define _ASM_RISCV_PROTOTYPES_H
#include <linux/ftrace.h>
#include <asm-generic/asm-prototypes.h>

6
arch/riscv/include/asm/current.h
View File

@ -7,8 +7,8 @@
*/
#ifndef __ASM_CURRENT_H
#define __ASM_CURRENT_H
#ifndef _ASM_RISCV_CURRENT_H
#define _ASM_RISCV_CURRENT_H
#include <linux/bug.h>
#include <linux/compiler.h>
@ -34,4 +34,4 @@ static __always_inline struct task_struct *get_current(void)
#endif /* __ASSEMBLY__ */
#endif /* __ASM_CURRENT_H */
#endif /* _ASM_RISCV_CURRENT_H */

5
arch/riscv/include/asm/ftrace.h
View File

@ -1,6 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (C) 2017 Andes Technology Corporation */
#ifndef _ASM_RISCV_FTRACE_H
#define _ASM_RISCV_FTRACE_H
/*
* The graph frame test is not possible if CONFIG_FRAME_POINTER is not enabled.
* Check arch/riscv/kernel/mcount.S for detail.
@ -64,3 +67,5 @@ do { \
*/
#define MCOUNT_INSN_SIZE 8
#endif
#endif /* _ASM_RISCV_FTRACE_H */

6
arch/riscv/include/asm/futex.h
View File

@ -4,8 +4,8 @@
* Copyright (c) 2018 Jim Wilson (jimw@sifive.com)
*/
#ifndef _ASM_FUTEX_H
#define _ASM_FUTEX_H
#ifndef _ASM_RISCV_FUTEX_H
#define _ASM_RISCV_FUTEX_H
#include <linux/futex.h>
#include <linux/uaccess.h>
@ -112,4 +112,4 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
return ret;
}
#endif /* _ASM_FUTEX_H */
#endif /* _ASM_RISCV_FUTEX_H */

7
arch/riscv/include/asm/hwcap.h
View File

@ -5,8 +5,8 @@
* Copyright (C) 2012 ARM Ltd.
* Copyright (C) 2017 SiFive
*/
#ifndef __ASM_HWCAP_H
#define __ASM_HWCAP_H
#ifndef _ASM_RISCV_HWCAP_H
#define _ASM_RISCV_HWCAP_H
#include <uapi/asm/hwcap.h>
@ -23,4 +23,5 @@ enum {
extern unsigned long elf_hwcap;
#endif
#endif
#endif /* _ASM_RISCV_HWCAP_H */

6
arch/riscv/include/asm/image.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_IMAGE_H
#define __ASM_IMAGE_H
#ifndef _ASM_RISCV_IMAGE_H
#define _ASM_RISCV_IMAGE_H
#define RISCV_IMAGE_MAGIC "RISCV\0\0\0"
#define RISCV_IMAGE_MAGIC2 "RSC\x05"
@ -62,4 +62,4 @@ struct riscv_image_header {
u32 res4;
};
#endif /* __ASSEMBLY__ */
#endif /* __ASM_IMAGE_H */
#endif /* _ASM_RISCV_IMAGE_H */

6
arch/riscv/include/asm/kprobes.h
View File

@ -6,9 +6,9 @@
* Copyright (C) 2017 SiFive
*/
#ifndef _RISCV_KPROBES_H
#define _RISCV_KPROBES_H
#ifndef _ASM_RISCV_KPROBES_H
#define _ASM_RISCV_KPROBES_H
#include <asm-generic/kprobes.h>
#endif /* _RISCV_KPROBES_H */
#endif /* _ASM_RISCV_KPROBES_H */

2
arch/riscv/include/asm/mmiowb.h
View File

@ -11,4 +11,4 @@
#include <asm-generic/mmiowb.h>
#endif /* ASM_RISCV_MMIOWB_H */
#endif /* _ASM_RISCV_MMIOWB_H */

6
arch/riscv/include/asm/pci.h
View File

@ -3,8 +3,8 @@
* Copyright (C) 2016 SiFive
*/
#ifndef __ASM_RISCV_PCI_H
#define __ASM_RISCV_PCI_H
#ifndef _ASM_RISCV_PCI_H
#define _ASM_RISCV_PCI_H
#include <linux/types.h>
#include <linux/slab.h>
@ -34,4 +34,4 @@ static inline int pci_proc_domain(struct pci_bus *bus)
}
#endif /* CONFIG_PCI */
#endif /* __ASM_PCI_H */
#endif /* _ASM_RISCV_PCI_H */

2
arch/riscv/include/asm/sbi.h
View File

@ -94,4 +94,4 @@ static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid);
}
#endif
#endif /* _ASM_RISCV_SBI_H */

6
arch/riscv/include/asm/sparsemem.h
View File

@ -1,11 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_SPARSEMEM_H
#define __ASM_SPARSEMEM_H
#ifndef _ASM_RISCV_SPARSEMEM_H
#define _ASM_RISCV_SPARSEMEM_H
#ifdef CONFIG_SPARSEMEM
#define MAX_PHYSMEM_BITS CONFIG_PA_BITS
#define SECTION_SIZE_BITS 27
#endif /* CONFIG_SPARSEMEM */
#endif /* __ASM_SPARSEMEM_H */
#endif /* _ASM_RISCV_SPARSEMEM_H */

2
arch/riscv/include/asm/spinlock_types.h
View File

@ -22,4 +22,4 @@ typedef struct {
#define __ARCH_RW_LOCK_UNLOCKED { 0 }
#endif
#endif /* _ASM_RISCV_SPINLOCK_TYPES_H */

6
arch/riscv/include/uapi/asm/elf.h
View File

@ -9,8 +9,8 @@
* (at your option) any later version.
*/
#ifndef _UAPI_ASM_ELF_H
#define _UAPI_ASM_ELF_H
#ifndef _UAPI_ASM_RISCV_ELF_H
#define _UAPI_ASM_RISCV_ELF_H
#include <asm/ptrace.h>
@ -95,4 +95,4 @@ typedef union __riscv_fp_state elf_fpregset_t;
#define R_RISCV_32_PCREL 57
#endif /* _UAPI_ASM_ELF_H */
#endif /* _UAPI_ASM_RISCV_ELF_H */

6
arch/riscv/include/uapi/asm/hwcap.h
View File

@ -5,8 +5,8 @@
* Copyright (C) 2012 ARM Ltd.
* Copyright (C) 2017 SiFive
*/
#ifndef __UAPI_ASM_HWCAP_H
#define __UAPI_ASM_HWCAP_H
#ifndef _UAPI_ASM_RISCV_HWCAP_H
#define _UAPI_ASM_RISCV_HWCAP_H
/*
* Linux saves the floating-point registers according to the ISA Linux is
@ -22,4 +22,4 @@
#define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A'))
#define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A'))
#endif
#endif /* _UAPI_ASM_RISCV_HWCAP_H */

6
arch/riscv/include/uapi/asm/ucontext.h
View File

@ -5,8 +5,8 @@
*
* This file was copied from arch/arm64/include/uapi/asm/ucontext.h
*/
#ifndef _UAPI__ASM_UCONTEXT_H
#define _UAPI__ASM_UCONTEXT_H
#ifndef _UAPI_ASM_RISCV_UCONTEXT_H
#define _UAPI_ASM_RISCV_UCONTEXT_H
#include <linux/types.h>
@ -31,4 +31,4 @@ struct ucontext {
struct sigcontext uc_mcontext;
};
#endif /* _UAPI__ASM_UCONTEXT_H */
#endif /* _UAPI_ASM_RISCV_UCONTEXT_H */

13
arch/riscv/mm/init.c
View File

@ -273,7 +273,6 @@ static void __init create_pmd_mapping(pmd_t *pmdp,
#define get_pgd_next_virt(__pa) get_pmd_virt(__pa)
#define create_pgd_next_mapping(__nextp, __va, __pa, __sz, __prot) \
create_pmd_mapping(__nextp, __va, __pa, __sz, __prot)
#define PTE_PARENT_SIZE PMD_SIZE
#define fixmap_pgd_next fixmap_pmd
#else
#define pgd_next_t pte_t
@ -281,7 +280,6 @@ static void __init create_pmd_mapping(pmd_t *pmdp,
#define get_pgd_next_virt(__pa) get_pte_virt(__pa)
#define create_pgd_next_mapping(__nextp, __va, __pa, __sz, __prot) \
create_pte_mapping(__nextp, __va, __pa, __sz, __prot)
#define PTE_PARENT_SIZE PGDIR_SIZE
#define fixmap_pgd_next fixmap_pte
#endif
@ -314,14 +312,11 @@ static void __init create_pgd_mapping(pgd_t *pgdp,
static uintptr_t __init best_map_size(phys_addr_t base, phys_addr_t size)
{
uintptr_t map_size = PAGE_SIZE;
/* Upgrade to PMD_SIZE mappings whenever possible */
if ((base & (PMD_SIZE - 1)) || (size & (PMD_SIZE - 1)))
return PAGE_SIZE;
/* Upgrade to PMD/PGDIR mappings whenever possible */
if (!(base & (PTE_PARENT_SIZE - 1)) &&
!(size & (PTE_PARENT_SIZE - 1)))
map_size = PTE_PARENT_SIZE;
return map_size;
return PMD_SIZE;
}
/*