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Merge branches 'clk-ofnode', 'clk-bindings', 'clk-cleanup', 'clk-zynq' and 'clk-xilinx' into clk-next

Browse Source 
- Miscellaneous of_node_put() fixes
 - Nuke dt-bindings/clk path (again) by moving headers to dt-bindings/clock
 - Convert gpio-clk-gate binding to YAML
 - Various fixes to AMD/Xilinx Zynqmp clk driver
 - Graduate AMD/Xilinx "clocking wizard" driver from staging

* clk-ofnode:
  clk: ti: Balance of_node_get() calls for of_find_node_by_name()
  clk: tegra20: Fix refcount leak in tegra20_clock_init
  clk: tegra: Fix refcount leak in tegra114_clock_init
  clk: tegra: Fix refcount leak in tegra210_clock_init
  clk: sprd: Hold reference returned by of_get_parent()
  clk: berlin: Add of_node_put() for of_get_parent()
  clk: at91: dt-compat: Hold reference returned by of_get_parent()
  clk: qoriq: Hold reference returned by of_get_parent()
  clk: oxnas: Hold reference returned by of_get_parent()
  clk: st: Hold reference returned by of_get_parent()
  clk: tegra: Add missing of_node_put()
  clk: meson: Hold reference returned by of_get_parent()
  clk: nomadik: Add missing of_node_put()

* clk-bindings:
  dt-bindings: clock: drop minItems equal to maxItems
  dt-bindings: clock: gpio-gate-clock: Convert to json-schema
  dt-bindings: clock: Move versaclock.h to dt-bindings/clock
  dt-bindings: clock: Move lochnagar.h to dt-bindings/clock

* clk-cleanup:
  clk: allow building lan966x as a module
  clk: clk-xgene: simplify if-if to if-else
  clk: nxp: fix typo in comment
  clk: mvebu: armada-37xx-tbg: Remove the unneeded result variable
  clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probe
  clkdev: Simplify devm_clk_hw_register_clkdev() function
  clkdev: Remove never used devm_clk_release_clkdev()
  clk: Remove never used devm_of_clk_del_provider()
  clk: pistachio: Fix initconst confusion
  clk: clk-npcm7xx: Remove unused struct npcm7xx_clk_gate_data and npcm7xx_clk_div_fixed_data
  clk: do not initialize ret
  clk: remove extra empty line
  clk: Fix comment typo
  clk: move from strlcpy with unused retval to strscpy

* clk-zynq:
  clk: zynqmp: pll: rectify rate rounding in zynqmp_pll_round_rate
  clk: zynqmp: Check the return type zynqmp_pm_query_data
  clk: zynqmp: Add a check for NULL pointer
  clk: zynqmp: Replaced strncpy() with strscpy()
  clk: zynqmp: Fix stack-out-of-bounds in strncpy`
  clk: zynqmp: make bestdiv unsigned

* clk-xilinx:
  clk: clocking-wizard: Depend on HAS_IOMEM
  clk: clocking-wizard: Use dev_err_probe() helper
  clk: clocking-wizard: Update the compatible
  clk: clocking-wizard: Fix the reconfig for 5.2
  clk: clocking-wizard: Rename nr-outputs to xlnx,nr-outputs
  clk: clocking-wizard: Move clocking-wizard out
  dt-bindings: add documentation of xilinx clocking wizard
This commit is contained in:
Stephen Boyd 2022-10-04 10:53:04 -07:00
commit 49f4c2d101
61 changed files with 371 additions and 299 deletions
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1
Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml
View File

@ -23,7 +23,6 @@ properties:
clocks:
description:
Common clock binding for CLK_IN, XTI/REF_CLK
minItems: 2
maxItems: 2
clock-names:

21
Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
View File

@ -1,21 +0,0 @@
Binding for simple gpio gated clock.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be "gpio-gate-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- enable-gpios : GPIO reference for enabling and disabling the clock.
Optional properties:
- clocks: Maximum of one parent clock is supported.
Example:
clock {
compatible = "gpio-gate-clock";
clocks = <&parentclk>;
#clock-cells = <0>;
enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
};

42
Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml Normal file
View File

@ -0,0 +1,42 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/gpio-gate-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Simple GPIO clock gate
maintainers:
- Jyri Sarha <jsarha@ti.com>
properties:
compatible:
const: gpio-gate-clock
clocks:
maxItems: 1
'#clock-cells':
const: 0
enable-gpios:
description: GPIO reference for enabling and disabling the clock.
maxItems: 1
required:
- compatible
- '#clock-cells'
- enable-gpios
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
clock {
compatible = "gpio-gate-clock";
clocks = <&parentclk>;
#clock-cells = <0>;
enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
};

4
Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
View File

@ -108,7 +108,7 @@ patternProperties:
properties:
idt,mode:
description:
The output drive mode. Values defined in dt-bindings/clk/versaclock.h
The output drive mode. Values defined in dt-bindings/clock/versaclock.h
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 6
@ -151,7 +151,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clk/versaclock.h>
#include <dt-bindings/clock/versaclock.h>
/* 25MHz reference crystal */
ref25: ref25m {

2
Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.yaml
View File

@ -47,7 +47,6 @@ properties:
maxItems: 1
clocks:
minItems: 4
maxItems: 4
clock-names:
@ -64,7 +63,6 @@ properties:
maxItems: 1
resets:
minItems: 2
maxItems: 2
reset-names:

1
Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml
View File

@ -34,7 +34,6 @@ properties:
const: 1
clock-output-names:
minItems: 3
maxItems: 3
description: Names for AP, CP and BT clocks.

2
Documentation/devicetree/bindings/clock/ti/gate.txt
View File

@ -10,7 +10,7 @@ will be controlled instead and the corresponding hw-ops for
that is used.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
Required properties:

2
Documentation/devicetree/bindings/clock/ti/interface.txt
View File

@ -9,7 +9,7 @@ companion clock finding (match corresponding functional gate
clock) and hardware autoidle enable / disable.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
Required properties:
- compatible : shall be one of:

77
Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml Normal file
View File

@ -0,0 +1,77 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Xilinx clocking wizard
maintainers:
- Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
description:
The clocking wizard is a soft ip clocking block of Xilinx versal. It
reads required input clock frequencies from the devicetree and acts as clock
clock output.
properties:
compatible:
enum:
- xlnx,clocking-wizard
- xlnx,clocking-wizard-v5.2
- xlnx,clocking-wizard-v6.0
reg:
maxItems: 1
"#clock-cells":
const: 1
clocks:
items:
- description: clock input
- description: axi clock
clock-names:
items:
- const: clk_in1
- const: s_axi_aclk
xlnx,speed-grade:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 3]
description:
Speed grade of the device. Higher the speed grade faster is the FPGA device.
xlnx,nr-outputs:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
maximum: 8
description:
Number of outputs.
required:
- compatible
- reg
- "#clock-cells"
- clocks
- clock-names
- xlnx,speed-grade
- xlnx,nr-outputs
additionalProperties: false
examples:
- |
clock-controller@b0000000 {
compatible = "xlnx,clocking-wizard";
reg = <0xb0000000 0x10000>;
#clock-cells = <1>;
xlnx,speed-grade = <1>;
xlnx,nr-outputs = <6>;
clock-names = "clk_in1", "s_axi_aclk";
clocks = <&clkc 15>, <&clkc 15>;
};
...

2
Documentation/devicetree/bindings/mfd/cirrus,lochnagar.yaml
View File

@ -261,7 +261,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clk/lochnagar.h>
#include <dt-bindings/clock/lochnagar.h>
#include <dt-bindings/pinctrl/lochnagar.h>
i2c@e0004000 {
#address-cells = <1>;

2
MAINTAINERS
View File

@ -4957,7 +4957,7 @@ F: drivers/hwmon/lochnagar-hwmon.c
F: drivers/mfd/lochnagar-i2c.c
F: drivers/pinctrl/cirrus/pinctrl-lochnagar.c
F: drivers/regulator/lochnagar-regulator.c
F: include/dt-bindings/clk/lochnagar.h
F: include/dt-bindings/clock/lochnagar.h
F: include/dt-bindings/pinctrl/lochnagar.h
F: include/linux/mfd/lochnagar*
F: sound/soc/codecs/lochnagar-sc.c

2
arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
View File

@ -5,7 +5,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/clk/versaclock.h>
#include <dt-bindings/clock/versaclock.h>
/ {
backlight_lvds: backlight-lvds {

2
arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
View File

@ -4,7 +4,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/versaclock.h>
#include <dt-bindings/clock/versaclock.h>
/ {
memory@48000000 {

2
drivers/clk/Kconfig
View File

@ -249,7 +249,7 @@ config COMMON_CLK_GEMINI
platform, also known as SL3516 or CS3516.
config COMMON_CLK_LAN966X
bool "Generic Clock Controller driver for LAN966X SoC"
tristate "Generic Clock Controller driver for LAN966X SoC"
depends on HAS_IOMEM
depends on OF
depends on SOC_LAN966 || COMPILE_TEST

108
drivers/clk/at91/dt-compat.c
View File

@ -33,8 +33,11 @@ static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np)
const char *name = np->name;
const char *parent_name;
struct regmap *regmap;
struct device_node *parent_np;
regmap = syscon_node_to_regmap(of_get_parent(np));
parent_np = of_get_parent(np);
regmap = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap))
return;
@ -56,8 +59,11 @@ static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np)
const char *name = np->name;
const char *parent_name;
struct regmap *regmap;
struct device_node *parent_np;
regmap = syscon_node_to_regmap(of_get_parent(np));
parent_np = of_get_parent(np);
regmap = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap))
return;
@ -79,8 +85,11 @@ static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np)
const char *name = np->name;
const char *parent_name;
struct regmap *regmap;
struct device_node *parent_np;
regmap = syscon_node_to_regmap(of_get_parent(np));
parent_np = of_get_parent(np);
regmap = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap))
return;
@ -120,7 +129,7 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
struct clk_hw *hw;
unsigned int num_parents;
const char *parent_names[GENERATED_SOURCE_MAX];
struct device_node *gcknp;
struct device_node *gcknp, *parent_np;
struct clk_range range = CLK_RANGE(0, 0);
struct regmap *regmap;
@ -134,7 +143,9 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
if (!num || num > PERIPHERAL_MAX)
return;
regmap = syscon_node_to_regmap(of_get_parent(np));
parent_np = of_get_parent(np);
regmap = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap))
return;
@ -180,8 +191,11 @@ static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np)
const char *name = np->name;
const char *parent_name;
struct regmap *regmap;
struct device_node *parent_np;
regmap = syscon_node_to_regmap(of_get_parent(np));
parent_np = of_get_parent(np);
regmap = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap))
return;
@ -243,12 +257,15 @@ static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np)
const char *parent_name;
struct regmap *regmap;
bool bypass;
struct device_node *parent_np;
of_property_read_string(np, "clock-output-names", &name);
bypass = of_property_read_bool(np, "atmel,osc-bypass");
parent_name = of_clk_get_parent_name(np, 0);
regmap = syscon_node_to_regmap(of_get_parent(np));
parent_np = of_get_parent(np);
regmap = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap))
return;
@ -268,12 +285,15 @@ static void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np)
u32 accuracy = 0;
const char *name = np->name;
struct regmap *regmap;
struct device_node *parent_np;
of_property_read_string(np, "clock-output-names", &name);
of_property_read_u32(np, "clock-frequency", &frequency);
of_property_read_u32(np, "clock-accuracy", &accuracy);
regmap = syscon_node_to_regmap(of_get_parent(np));
parent_np = of_get_parent(np);
regmap = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap))
return;
@ -292,11 +312,14 @@ static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
const char *parent_name;
const char *name = np->name;
struct regmap *regmap;
struct device_node *parent_np;
parent_name = of_clk_get_parent_name(np, 0);
of_property_read_string(np, "clock-output-names", &name);
regmap = syscon_node_to_regmap(of_get_parent(np));
parent_np = of_get_parent(np);
regmap = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap))
return;
@ -316,13 +339,16 @@ static void __init of_at91sam9x5_clk_main_setup(struct device_node *np)
unsigned int num_parents;
const char *name = np->name;
struct regmap *regmap;
struct device_node *parent_np;
num_parents = of_clk_get_parent_count(np);
if (num_parents == 0 || num_parents > 2)
return;
of_clk_parent_fill(np, parent_names, num_parents);
regmap = syscon_node_to_regmap(of_get_parent(np));
parent_np = of_get_parent(np);
regmap = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap))
return;
@ -373,6 +399,7 @@ of_at91_clk_master_setup(struct device_node *np,
const char *name = np->name;
struct clk_master_characteristics *characteristics;
struct regmap *regmap;
struct device_node *parent_np;
num_parents = of_clk_get_parent_count(np);
if (num_parents == 0 || num_parents > MASTER_SOURCE_MAX)
@ -386,7 +413,9 @@ of_at91_clk_master_setup(struct device_node *np,
if (!characteristics)
return;
regmap = syscon_node_to_regmap(of_get_parent(np));
parent_np = of_get_parent(np);
regmap = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap))
return;
@ -433,6 +462,7 @@ of_at91_clk_periph_setup(struct device_node *np, u8 type)
const char *name;
struct device_node *periphclknp;
struct regmap *regmap;
struct device_node *parent_np;
parent_name = of_clk_get_parent_name(np, 0);
if (!parent_name)
@ -442,7 +472,9 @@ of_at91_clk_periph_setup(struct device_node *np, u8 type)
if (!num || num > PERIPHERAL_MAX)
return;
regmap = syscon_node_to_regmap(of_get_parent(np));
parent_np = of_get_parent(np);
regmap = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap))
return;
@ -601,6 +633,7 @@ of_at91_clk_pll_setup(struct device_node *np,
struct regmap *regmap;
const char *parent_name;
const char *name = np->name;
struct device_node *parent_np;
struct clk_pll_characteristics *characteristics;
if (of_property_read_u32(np, "reg", &id))
@ -610,7 +643,9 @@ of_at91_clk_pll_setup(struct device_node *np,
of_property_read_string(np, "clock-output-names", &name);
regmap = syscon_node_to_regmap(of_get_parent(np));
parent_np = of_get_parent(np);
regmap = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap))
return;
@ -665,12 +700,15 @@ of_at91sam9x5_clk_plldiv_setup(struct device_node *np)
const char *parent_name;
const char *name = np->name;
struct regmap *regmap;
struct device_node *parent_np;
parent_name = of_clk_get_parent_name(np, 0);
of_property_read_string(np, "clock-output-names", &name);
regmap = syscon_node_to_regmap(of_get_parent(np));
parent_np = of_get_parent(np);
regmap = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap))
return;
@ -694,7 +732,7 @@ of_at91_clk_prog_setup(struct device_node *np,
unsigned int num_parents;
const char *parent_names[PROG_SOURCE_MAX];
const char *name;
struct device_node *progclknp;
struct device_node *progclknp, *parent_np;
struct regmap *regmap;
num_parents = of_clk_get_parent_count(np);
@ -707,7 +745,9 @@ of_at91_clk_prog_setup(struct device_node *np,
if (!num || num > (PROG_ID_MAX + 1))
return;
regmap = syscon_node_to_regmap(of_get_parent(np));
parent_np = of_get_parent(np);
regmap = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap))
return;
@ -756,13 +796,16 @@ static void __init of_at91sam9260_clk_slow_setup(struct device_node *np)
unsigned int num_parents;
const char *name = np->name;
struct regmap *regmap;
struct device_node *parent_np;
num_parents = of_clk_get_parent_count(np);
if (num_parents != 2)
return;
of_clk_parent_fill(np, parent_names, num_parents);
regmap = syscon_node_to_regmap(of_get_parent(np));
parent_np = of_get_parent(np);
regmap = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap))
return;
@ -788,6 +831,7 @@ static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np)
const char *parent_names[SMD_SOURCE_MAX];
const char *name = np->name;
struct regmap *regmap;
struct device_node *parent_np;
num_parents = of_clk_get_parent_count(np);
if (num_parents == 0 || num_parents > SMD_SOURCE_MAX)
@ -797,7 +841,9 @@ static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np)
of_property_read_string(np, "clock-output-names", &name);
regmap = syscon_node_to_regmap(of_get_parent(np));
parent_np = of_get_parent(np);
regmap = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap))
return;
@ -818,7 +864,7 @@ static void __init of_at91rm9200_clk_sys_setup(struct device_node *np)
u32 id;
struct clk_hw *hw;
const char *name;
struct device_node *sysclknp;
struct device_node *sysclknp, *parent_np;
const char *parent_name;
struct regmap *regmap;
@ -826,7 +872,9 @@ static void __init of_at91rm9200_clk_sys_setup(struct device_node *np)
if (num > (SYSTEM_MAX_ID + 1))
return;
regmap = syscon_node_to_regmap(of_get_parent(np));
parent_np = of_get_parent(np);
regmap = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap))
return;
@ -859,6 +907,7 @@ static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np)
const char *parent_names[USB_SOURCE_MAX];
const char *name = np->name;
struct regmap *regmap;
struct device_node *parent_np;
num_parents = of_clk_get_parent_count(np);
if (num_parents == 0 || num_parents > USB_SOURCE_MAX)
@ -868,7 +917,9 @@ static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np)
of_property_read_string(np, "clock-output-names", &name);
regmap = syscon_node_to_regmap(of_get_parent(np));
parent_np = of_get_parent(np);
regmap = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap))
return;
@ -888,6 +939,7 @@ static void __init of_at91sam9n12_clk_usb_setup(struct device_node *np)
const char *parent_name;
const char *name = np->name;
struct regmap *regmap;
struct device_node *parent_np;
parent_name = of_clk_get_parent_name(np, 0);
if (!parent_name)
@ -895,7 +947,9 @@ static void __init of_at91sam9n12_clk_usb_setup(struct device_node *np)
of_property_read_string(np, "clock-output-names", &name);
regmap = syscon_node_to_regmap(of_get_parent(np));
parent_np = of_get_parent(np);
regmap = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap))
return;
@ -915,6 +969,7 @@ static void __init of_at91rm9200_clk_usb_setup(struct device_node *np)
const char *name = np->name;
u32 divisors[4] = {0, 0, 0, 0};
struct regmap *regmap;
struct device_node *parent_np;
parent_name = of_clk_get_parent_name(np, 0);
if (!parent_name)
@ -926,7 +981,9 @@ static void __init of_at91rm9200_clk_usb_setup(struct device_node *np)
of_property_read_string(np, "clock-output-names", &name);
regmap = syscon_node_to_regmap(of_get_parent(np));
parent_np = of_get_parent(np);
regmap = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap))
return;
hw = at91rm9200_clk_register_usb(regmap, name, parent_name, divisors);
@ -946,12 +1003,15 @@ static void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np)
const char *parent_name;
const char *name = np->name;
struct regmap *regmap_pmc, *regmap_sfr;
struct device_node *parent_np;
parent_name = of_clk_get_parent_name(np, 0);
of_property_read_string(np, "clock-output-names", &name);
regmap_pmc = syscon_node_to_regmap(of_get_parent(np));
parent_np = of_get_parent(np);
regmap_pmc = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap_pmc))
return;

5
drivers/clk/berlin/bg2.c
View File

@ -500,12 +500,15 @@ static void __init berlin2_clock_setup(struct device_node *np)
int n, ret;
clk_data = kzalloc(struct_size(clk_data, hws, MAX_CLKS), GFP_KERNEL);
if (!clk_data)
if (!clk_data) {
of_node_put(parent_np);
return;
}
clk_data->num = MAX_CLKS;
hws = clk_data->hws;
gbase = of_iomap(parent_np, 0);
of_node_put(parent_np);
if (!gbase)
return;

6
drivers/clk/berlin/bg2q.c
View File

@ -286,19 +286,23 @@ static void __init berlin2q_clock_setup(struct device_node *np)
int n, ret;
clk_data = kzalloc(struct_size(clk_data, hws, MAX_CLKS), GFP_KERNEL);
if (!clk_data)
if (!clk_data) {
of_node_put(parent_np);
return;
}
clk_data->num = MAX_CLKS;
hws = clk_data->hws;
gbase = of_iomap(parent_np, 0);
if (!gbase) {
of_node_put(parent_np);
pr_err("%pOF: Unable to map global base\n", np);
return;
}
/* BG2Q CPU PLL is not part of global registers */
cpupll_base = of_iomap(parent_np, 1);
of_node_put(parent_np);
if (!cpupll_base) {
pr_err("%pOF: Unable to map cpupll base\n", np);
iounmap(gbase);

2
drivers/clk/clk-lan966x.c
View File

@ -286,7 +286,7 @@ static struct platform_driver lan966x_clk_driver = {
.of_match_table = lan966x_clk_dt_ids,
},
};
builtin_platform_driver(lan966x_clk_driver);
module_platform_driver(lan966x_clk_driver);
MODULE_AUTHOR("Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>");
MODULE_DESCRIPTION("LAN966X clock driver");

2
drivers/clk/clk-lochnagar.c
View File

@ -19,7 +19,7 @@
#include <linux/mfd/lochnagar1_regs.h>
#include <linux/mfd/lochnagar2_regs.h>
#include <dt-bindings/clk/lochnagar.h>
#include <dt-bindings/clock/lochnagar.h>
#define LOCHNAGAR_NUM_CLOCKS (LOCHNAGAR_SPDIF_CLKOUT + 1)

5
drivers/clk/clk-nomadik.c
View File

@ -99,7 +99,7 @@ static void __init nomadik_src_init(void)
if (!src_base) {
pr_err("%s: must have src parent node with REGS (%pOFn)\n",
__func__, np);
return;
goto out_put;
}
/* Set all timers to use the 2.4 MHz TIMCLK */
@ -132,6 +132,9 @@ static void __init nomadik_src_init(void)
}
writel(val, src_base + SRC_XTALCR);
register_reboot_notifier(&nomadik_clk_reboot_notifier);
out_put:
of_node_put(np);
}
/**

29
drivers/clk/clk-npcm7xx.c
View File

@ -129,20 +129,6 @@ npcm7xx_clk_register_pll(void __iomem *pllcon, const char *name,
#define NPCM7XX_SECCNT (0x68)
#define NPCM7XX_CNTR25M (0x6C)
struct npcm7xx_clk_gate_data {
u32 reg;
u8 bit_idx;
const char *name;
const char *parent_name;
unsigned long flags;
/*
* If this clock is exported via DT, set onecell_idx to constant
* defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
* this specific clock. Otherwise, set to -1.
*/
int onecell_idx;
};
struct npcm7xx_clk_mux_data {
u8 shift;
u8 mask;
@ -160,21 +146,6 @@ struct npcm7xx_clk_mux_data {
};
struct npcm7xx_clk_div_fixed_data {
u8 mult;
u8 div;
const char *name;
const char *parent_name;
u8 clk_divider_flags;
/*
* If this clock is exported via DT, set onecell_idx to constant
* defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
* this specific clock. Otherwise, set to -1.
*/
int onecell_idx;
};
struct npcm7xx_clk_div_data {
u32 reg;
u8 shift;

6
drivers/clk/clk-oxnas.c
View File

@ -207,7 +207,7 @@ static const struct of_device_id oxnas_stdclk_dt_ids[] = {
static int oxnas_stdclk_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct device_node *np = pdev->dev.of_node, *parent_np;
const struct oxnas_stdclk_data *data;
struct regmap *regmap;
int ret;
@ -215,7 +215,9 @@ static int oxnas_stdclk_probe(struct platform_device *pdev)
data = of_device_get_match_data(&pdev->dev);
regmap = syscon_node_to_regmap(of_get_parent(np));
parent_np = of_get_parent(np);
regmap = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap)) {
dev_err(&pdev->dev, "failed to have parent regmap\n");
return PTR_ERR(regmap);

10
drivers/clk/clk-qoriq.c
View File

@ -1063,8 +1063,13 @@ static void __init _clockgen_init(struct device_node *np, bool legacy);
*/
static void __init legacy_init_clockgen(struct device_node *np)
{
if (!clockgen.node)
_clockgen_init(of_get_parent(np), true);
if (!clockgen.node) {
struct device_node *parent_np;
parent_np = of_get_parent(np);
_clockgen_init(parent_np, true);
of_node_put(parent_np);
}
}
/* Legacy node */
@ -1159,6 +1164,7 @@ static struct clk * __init create_sysclk(const char *name)
sysclk = of_get_child_by_name(clockgen.node, "sysclk");
if (sysclk) {
clk = sysclk_from_fixed(sysclk, name);
of_node_put(sysclk);
if (!IS_ERR(clk))
return clk;
}

2
drivers/clk/clk-versaclock5.c
View File

@ -24,7 +24,7 @@
#include <linux/regmap.h>
#include <linux/slab.h>
#include <dt-bindings/clk/versaclock.h>
#include <dt-bindings/clock/versaclock.h>
/* VersaClock5 registers */
#define VC5_OTP_CONTROL 0x00

4
drivers/clk/clk-xgene.c
View File

@ -522,10 +522,10 @@ static int xgene_clk_is_enabled(struct clk_hw *hw)
pr_debug("%s clock is %s\n", clk_hw_get_name(hw),
data & pclk->param.reg_clk_mask ? "enabled" :
"disabled");
} else {
return 1;
}
if (!pclk->param.csr_reg)
return 1;
return data & pclk->param.reg_clk_mask ? 1 : 0;
}

31
drivers/clk/clk.c
View File

@ -2189,7 +2189,7 @@ static int clk_core_set_rate_nolock(struct clk_core *core,
{
struct clk_core *top, *fail_clk;
unsigned long rate;
int ret = 0;
int ret;
if (!core)
return 0;
@ -3462,7 +3462,7 @@ static void clk_core_reparent_orphans_nolock(void)
/*
* We need to use __clk_set_parent_before() and _after() to
* to properly migrate any prepare/enable count of the orphan
* properly migrate any prepare/enable count of the orphan
* clock. This is important for CLK_IS_CRITICAL clocks, which
* are enabled during init but might not have a parent yet.
*/
@ -3672,7 +3672,6 @@ static int __clk_core_init(struct clk_core *core)
clk_core_reparent_orphans_nolock();
kref_init(&core->ref);
out:
clk_pm_runtime_put(core);
@ -4751,32 +4750,6 @@ void of_clk_del_provider(struct device_node *np)
}
EXPORT_SYMBOL_GPL(of_clk_del_provider);
static int devm_clk_provider_match(struct device *dev, void *res, void *data)
{
struct device_node **np = res;
if (WARN_ON(!np || !*np))
return 0;
return *np == data;
}
/**
* devm_of_clk_del_provider() - Remove clock provider registered using devm
* @dev: Device to whose lifetime the clock provider was bound
*/
void devm_of_clk_del_provider(struct device *dev)
{
int ret;
struct device_node *np = get_clk_provider_node(dev);
ret = devres_release(dev, devm_of_clk_release_provider,
devm_clk_provider_match, np);
WARN_ON(ret);
}
EXPORT_SYMBOL(devm_of_clk_del_provider);
/**
* of_parse_clkspec() - Parse a DT clock specifier for a given device node
* @np: device node to parse clock specifier from

58
drivers/clk/clkdev.c
View File

@ -165,7 +165,7 @@ vclkdev_alloc(struct clk_hw *hw, const char *con_id, const char *dev_fmt,
cla->cl.clk_hw = hw;
if (con_id) {
strlcpy(cla->con_id, con_id, sizeof(cla->con_id));
strscpy(cla->con_id, con_id, sizeof(cla->con_id));
cla->cl.con_id = cla->con_id;
}
@ -346,45 +346,11 @@ int clk_hw_register_clkdev(struct clk_hw *hw, const char *con_id,
}
EXPORT_SYMBOL(clk_hw_register_clkdev);
static void devm_clkdev_release(struct device *dev, void *res)
static void devm_clkdev_release(void *res)
{
clkdev_drop(*(struct clk_lookup **)res);
clkdev_drop(res);
}
static int devm_clk_match_clkdev(struct device *dev, void *res, void *data)
{
struct clk_lookup **l = res;
return *l == data;
}
/**
* devm_clk_release_clkdev - Resource managed clkdev lookup release
* @dev: device this lookup is bound
* @con_id: connection ID string on device
* @dev_id: format string describing device name
*
* Drop the clkdev lookup created with devm_clk_hw_register_clkdev.
* Normally this function will not need to be called and the resource
* management code will ensure that the resource is freed.
*/
void devm_clk_release_clkdev(struct device *dev, const char *con_id,
const char *dev_id)
{
struct clk_lookup *cl;
int rval;
mutex_lock(&clocks_mutex);
cl = clk_find(dev_id, con_id);
mutex_unlock(&clocks_mutex);
WARN_ON(!cl);
rval = devres_release(dev, devm_clkdev_release,
devm_clk_match_clkdev, cl);
WARN_ON(rval);
}
EXPORT_SYMBOL(devm_clk_release_clkdev);
/**
* devm_clk_hw_register_clkdev - managed clk lookup registration for clk_hw
* @dev: device this lookup is bound
@ -403,17 +369,13 @@ EXPORT_SYMBOL(devm_clk_release_clkdev);
int devm_clk_hw_register_clkdev(struct device *dev, struct clk_hw *hw,
const char *con_id, const char *dev_id)
{
int rval = -ENOMEM;
struct clk_lookup **cl;
struct clk_lookup *cl;
int rval;
cl = devres_alloc(devm_clkdev_release, sizeof(*cl), GFP_KERNEL);
if (cl) {
rval = do_clk_register_clkdev(hw, cl, con_id, dev_id);
if (!rval)
devres_add(dev, cl);
else
devres_free(cl);
}
return rval;
rval = do_clk_register_clkdev(hw, &cl, con_id, dev_id);
if (rval)
return rval;
return devm_add_action_or_reset(dev, devm_clkdev_release, cl);
}
EXPORT_SYMBOL(devm_clk_hw_register_clkdev);

5
drivers/clk/meson/meson-aoclk.c
View File

@ -38,6 +38,7 @@ int meson_aoclkc_probe(struct platform_device *pdev)
struct meson_aoclk_reset_controller *rstc;
struct meson_aoclk_data *data;
struct device *dev = &pdev->dev;
struct device_node *np;
struct regmap *regmap;
int ret, clkid;
@ -49,7 +50,9 @@ int meson_aoclkc_probe(struct platform_device *pdev)
if (!rstc)
return -ENOMEM;
regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
np = of_get_parent(dev->of_node);
regmap = syscon_node_to_regmap(np);
of_node_put(np);
if (IS_ERR(regmap)) {
dev_err(dev, "failed to get regmap\n");
return PTR_ERR(regmap);

5
drivers/clk/meson/meson-eeclk.c
View File

@ -18,6 +18,7 @@ int meson_eeclkc_probe(struct platform_device *pdev)
{
const struct meson_eeclkc_data *data;
struct device *dev = &pdev->dev;
struct device_node *np;
struct regmap *map;
int ret, i;
@ -26,7 +27,9 @@ int meson_eeclkc_probe(struct platform_device *pdev)
return -EINVAL;
/* Get the hhi system controller node */
map = syscon_node_to_regmap(of_get_parent(dev->of_node));
np = of_get_parent(dev->of_node);
map = syscon_node_to_regmap(np);
of_node_put(np);
if (IS_ERR(map)) {
dev_err(dev,
"failed to get HHI regmap\n");

5
drivers/clk/meson/meson8b.c
View File

@ -3792,12 +3792,15 @@ static void __init meson8b_clkc_init_common(struct device_node *np,
struct clk_hw_onecell_data *clk_hw_onecell_data)
{
struct meson8b_clk_reset *rstc;
struct device_node *parent_np;
const char *notifier_clk_name;
struct clk *notifier_clk;
struct regmap *map;
int i, ret;
map = syscon_node_to_regmap(of_get_parent(np));
parent_np = of_get_parent(np);
map = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(map)) {
pr_err("failed to get HHI regmap - Trying obsolete regs\n");
return;

6
drivers/clk/mvebu/armada-37xx-tbg.c
View File

@ -87,7 +87,7 @@ static int armada_3700_tbg_clock_probe(struct platform_device *pdev)
struct resource *res;
struct clk *parent;
void __iomem *reg;
int i, ret;
int i;
hw_tbg_data = devm_kzalloc(&pdev->dev,
struct_size(hw_tbg_data, hws, NUM_TBG),
@ -123,9 +123,7 @@ static int armada_3700_tbg_clock_probe(struct platform_device *pdev)
dev_err(dev, "Can't register TBG clock %s\n", name);
}
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, hw_tbg_data);
return ret;
return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, hw_tbg_data);
}
static int armada_3700_tbg_clock_remove(struct platform_device *pdev)

2
drivers/clk/mvebu/dove-divider.c
View File

@ -170,7 +170,7 @@ static struct clk *clk_register_dove_divider(struct device *dev,
.num_parents = num_parents,
};
strlcpy(name, dc->name, sizeof(name));
strscpy(name, dc->name, sizeof(name));
dc->hw.init = &init;
dc->base = base;

2
drivers/clk/nxp/clk-lpc18xx-cgu.c
View File

@ -606,7 +606,7 @@ static void __init lpc18xx_cgu_register_source_clks(struct device_node *np,
if (IS_ERR(clk))
pr_warn("%s: failed to register irc clk\n", __func__);
/* Register crystal oscillator controlller */
/* Register crystal oscillator controller */
parents[0] = of_clk_get_parent_name(np, 0);
clk = clk_register_gate(NULL, clk_src_names[CLK_SRC_OSC], parents[0],
0, base + LPC18XX_CGU_XTAL_OSC_CTRL,

4
drivers/clk/pistachio/clk.h
View File

@ -31,10 +31,10 @@ struct pistachio_mux {
unsigned int shift;
unsigned int num_parents;
const char *name;
const char **parents;
const char *const *parents;
};
#define PNAME(x) static const char *x[] __initconst
#define PNAME(x) static const char *const x[] __initconst
#define MUX(_id, _name, _pnames, _reg, _shift) \
{ \

9
drivers/clk/sprd/common.c
View File

@ -41,7 +41,7 @@ int sprd_clk_regmap_init(struct platform_device *pdev,
{
void __iomem *base;
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
struct device_node *node = dev->of_node, *np;
struct regmap *regmap;
if (of_find_property(node, "sprd,syscon", NULL)) {
@ -50,9 +50,10 @@ int sprd_clk_regmap_init(struct platform_device *pdev,
pr_err("%s: failed to get syscon regmap\n", __func__);
return PTR_ERR(regmap);
}
} else if (of_device_is_compatible(of_get_parent(dev->of_node),
"syscon")) {
regmap = device_node_to_regmap(of_get_parent(dev->of_node));
} else if (of_device_is_compatible(np = of_get_parent(node), "syscon") ||
(of_node_put(np), 0)) {
regmap = device_node_to_regmap(np);
of_node_put(np);
if (IS_ERR(regmap)) {
dev_err(dev, "failed to get regmap from its parent.\n");
return PTR_ERR(regmap);

5
drivers/clk/st/clkgen-fsyn.c
View File

@ -987,6 +987,7 @@ static void __init st_of_quadfs_setup(struct device_node *np,
const char *pll_name, *clk_parent_name;
void __iomem *reg;
spinlock_t *lock;
struct device_node *parent_np;
/*
* First check for reg property within the node to keep backward
@ -994,7 +995,9 @@ static void __init st_of_quadfs_setup(struct device_node *np,
*/
reg = of_iomap(np, 0);
if (!reg) {
reg = of_iomap(of_get_parent(np), 0);
parent_np = of_get_parent(np);
reg = of_iomap(parent_np, 0);
of_node_put(parent_np);
if (!reg) {
pr_err("%s: Failed to get base address\n", __func__);
return;

5
drivers/clk/st/clkgen-mux.c
View File

@ -56,6 +56,7 @@ static void __init st_of_clkgen_mux_setup(struct device_node *np,
void __iomem *reg;
const char **parents;
int num_parents = 0;
struct device_node *parent_np;
/*
* First check for reg property within the node to keep backward
@ -63,7 +64,9 @@ static void __init st_of_clkgen_mux_setup(struct device_node *np,
*/
reg = of_iomap(np, 0);
if (!reg) {
reg = of_iomap(of_get_parent(np), 0);
parent_np = of_get_parent(np);
reg = of_iomap(parent_np, 0);
of_node_put(parent_np);
if (!reg) {
pr_err("%s: Failed to get base address\n", __func__);
return;

2
drivers/clk/tegra/clk-bpmp.c
View File

@ -349,7 +349,7 @@ static int tegra_bpmp_clk_get_info(struct tegra_bpmp *bpmp, unsigned int id,
if (err < 0)
return err;
strlcpy(info->name, response.name, MRQ_CLK_NAME_MAXLEN);
strscpy(info->name, response.name, MRQ_CLK_NAME_MAXLEN);
info->num_parents = response.num_parents;
for (i = 0; i < info->num_parents; i++)

1
drivers/clk/tegra/clk-tegra114.c
View File

@ -1317,6 +1317,7 @@ static void __init tegra114_clock_init(struct device_node *np)
}
pmc_base = of_iomap(node, 0);
of_node_put(node);
if (!pmc_base) {
pr_err("Can't map pmc registers\n");
WARN_ON(1);

1
drivers/clk/tegra/clk-tegra124.c
View File

@ -1471,6 +1471,7 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
}
pmc_base = of_iomap(node, 0);
of_node_put(node);
if (!pmc_base) {
pr_err("Can't map pmc registers\n");
WARN_ON(1);

1
drivers/clk/tegra/clk-tegra20.c
View File

@ -1131,6 +1131,7 @@ static void __init tegra20_clock_init(struct device_node *np)
}
pmc_base = of_iomap(node, 0);
of_node_put(node);
if (!pmc_base) {
pr_err("Can't map pmc registers\n");
BUG();

1
drivers/clk/tegra/clk-tegra210.c
View File

@ -3748,6 +3748,7 @@ static void __init tegra210_clock_init(struct device_node *np)
}
pmc_base = of_iomap(node, 0);
of_node_put(node);
if (!pmc_base) {
pr_err("Can't map pmc registers\n");
WARN_ON(1);

1
drivers/clk/tegra/clk-tegra30.c
View File

@ -1320,6 +1320,7 @@ static void __init tegra30_clock_init(struct device_node *np)
}
pmc_base = of_iomap(node, 0);
of_node_put(node);
if (!pmc_base) {
pr_err("Can't map pmc registers\n");
BUG();

9
drivers/clk/ti/clk-dra7-atl.c
View File

@ -245,14 +245,16 @@ static int of_dra7_atl_clk_probe(struct platform_device *pdev)
if (rc) {
pr_err("%s: failed to lookup atl clock %d\n", __func__,
i);
return -EINVAL;
ret = -EINVAL;
goto pm_put;
}
clk = of_clk_get_from_provider(&clkspec);
if (IS_ERR(clk)) {
pr_err("%s: failed to get atl clock %d from provider\n",
__func__, i);
return PTR_ERR(clk);
ret = PTR_ERR(clk);
goto pm_put;
}
cdesc = to_atl_desc(__clk_get_hw(clk));
@ -285,8 +287,9 @@ static int of_dra7_atl_clk_probe(struct platform_device *pdev)
if (cdesc->enabled)
atl_clk_enable(__clk_get_hw(clk));
}
pm_runtime_put_sync(cinfo->dev);
pm_put:
pm_runtime_put_sync(cinfo->dev);
return ret;
}

5
drivers/clk/ti/clk.c
View File

@ -139,11 +139,12 @@ static struct device_node *ti_find_clock_provider(struct device_node *from,
break;
}
}
of_node_put(from);
kfree(tmp);
if (found)
if (found) {
of_node_put(from);
return np;
}
/* Fall back to using old node name base provider name */
return of_find_node_by_name(from, name);

12
drivers/clk/xilinx/Kconfig
View File

@ -17,3 +17,15 @@ config XILINX_VCU
To compile this driver as a module, choose M here: the
module will be called xlnx_vcu.
config COMMON_CLK_XLNX_CLKWZRD
tristate "Xilinx Clocking Wizard"
depends on COMMON_CLK && OF
depends on HAS_IOMEM
help
Support for the Xilinx Clocking Wizard IP core clock generator.
Adds support for clocking wizard and compatible.
This driver supports the Xilinx clocking wizard programmable clock
synthesizer. The number of output is configurable in the design.
If unsure, say N.

1
drivers/clk/xilinx/Makefile
View File

@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_XILINX_VCU) += xlnx_vcu.o
obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o

35
drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c → drivers/clk/xilinx/clk-xlnx-clock-wizard.c
View File

@ -2,9 +2,10 @@
/*
* Xilinx 'Clocking Wizard' driver
*
* Copyright (C) 2013 - 2014 Xilinx
* Copyright (C) 2013 - 2021 Xilinx
*
* Sören Brinkmann <soren.brinkmann@xilinx.com>
*
*/
#include <linux/platform_device.h>
@ -43,6 +44,8 @@
#define WZRD_DR_INIT_REG_OFFSET 0x25C
#define WZRD_DR_DIV_TO_PHASE_OFFSET 4
#define WZRD_DR_BEGIN_DYNA_RECONF 0x03
#define WZRD_DR_BEGIN_DYNA_RECONF_5_2 0x07
#define WZRD_DR_BEGIN_DYNA_RECONF1_5_2 0x02
#define WZRD_USEC_POLL 10
#define WZRD_TIMEOUT_POLL 1000
@ -164,7 +167,9 @@ static int clk_wzrd_dynamic_reconfig(struct clk_hw *hw, unsigned long rate,
goto err_reconfig;
/* Initiate reconfiguration */
writel(WZRD_DR_BEGIN_DYNA_RECONF,
writel(WZRD_DR_BEGIN_DYNA_RECONF_5_2,
divider->base + WZRD_DR_INIT_REG_OFFSET);
writel(WZRD_DR_BEGIN_DYNA_RECONF1_5_2,
divider->base + WZRD_DR_INIT_REG_OFFSET);
/* Check status register */
@ -223,7 +228,7 @@ static int clk_wzrd_dynamic_reconfig_f(struct clk_hw *hw, unsigned long rate,
struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
void __iomem *div_addr = divider->base + divider->offset;
rate_div = ((parent_rate * 1000) / rate);
rate_div = DIV_ROUND_DOWN_ULL(parent_rate * 1000, rate);
clockout0_div = rate_div / 1000;
pre = DIV_ROUND_CLOSEST((parent_rate * 1000), rate);
@ -245,7 +250,9 @@ static int clk_wzrd_dynamic_reconfig_f(struct clk_hw *hw, unsigned long rate,
return err;
/* Initiate reconfiguration */
writel(WZRD_DR_BEGIN_DYNA_RECONF,
writel(WZRD_DR_BEGIN_DYNA_RECONF_5_2,
divider->base + WZRD_DR_INIT_REG_OFFSET);
writel(WZRD_DR_BEGIN_DYNA_RECONF1_5_2,
divider->base + WZRD_DR_INIT_REG_OFFSET);
/* Check status register */
@ -441,18 +448,14 @@ static int clk_wzrd_probe(struct platform_device *pdev)
}
clk_wzrd->clk_in1 = devm_clk_get(&pdev->dev, "clk_in1");
if (IS_ERR(clk_wzrd->clk_in1)) {
if (clk_wzrd->clk_in1 != ERR_PTR(-EPROBE_DEFER))
dev_err(&pdev->dev, "clk_in1 not found\n");
return PTR_ERR(clk_wzrd->clk_in1);
}
if (IS_ERR(clk_wzrd->clk_in1))
return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->clk_in1),
"clk_in1 not found\n");
clk_wzrd->axi_clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
if (IS_ERR(clk_wzrd->axi_clk)) {
if (clk_wzrd->axi_clk != ERR_PTR(-EPROBE_DEFER))
dev_err(&pdev->dev, "s_axi_aclk not found\n");
return PTR_ERR(clk_wzrd->axi_clk);
}
if (IS_ERR(clk_wzrd->axi_clk))
return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->axi_clk),
"s_axi_aclk not found\n");
ret = clk_prepare_enable(clk_wzrd->axi_clk);
if (ret) {
dev_err(&pdev->dev, "enabling s_axi_aclk failed\n");
@ -479,7 +482,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
goto err_disable_clk;
}
ret = of_property_read_u32(np, "nr-outputs", &nr_outputs);
ret = of_property_read_u32(np, "xlnx,nr-outputs", &nr_outputs);
if (ret || nr_outputs > WZRD_NUM_OUTPUTS) {
ret = -EINVAL;
goto err_disable_clk;
@ -614,6 +617,8 @@ static int clk_wzrd_remove(struct platform_device *pdev)
static const struct of_device_id clk_wzrd_ids[] = {
{ .compatible = "xlnx,clocking-wizard" },
{ .compatible = "xlnx,clocking-wizard-v5.2" },
{ .compatible = "xlnx,clocking-wizard-v6.0" },
{ },
};
MODULE_DEVICE_TABLE(of, clk_wzrd_ids);

19
drivers/clk/zynqmp/clkc.c
View File

@ -163,7 +163,7 @@ static int zynqmp_get_clock_name(u32 clk_id, char *clk_name)
ret = zynqmp_is_valid_clock(clk_id);
if (ret == 1) {
strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN);
strscpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN);
return 0;
}
@ -220,18 +220,22 @@ static int zynqmp_pm_clock_get_num_clocks(u32 *nclocks)
* This function is used to get name of clock specified by given
* clock ID.
*
* Return: Returns 0
* Return: 0 on success else error+reason
*/
static int zynqmp_pm_clock_get_name(u32 clock_id,
struct name_resp *response)
{
struct zynqmp_pm_query_data qdata = {0};
u32 ret_payload[PAYLOAD_ARG_CNT];
int ret;
qdata.qid = PM_QID_CLOCK_GET_NAME;
qdata.arg1 = clock_id;
zynqmp_pm_query_data(qdata, ret_payload);
ret = zynqmp_pm_query_data(qdata, ret_payload);
if (ret)
return ret;
memcpy(response, ret_payload, sizeof(*response));
return 0;
@ -710,9 +714,16 @@ static void zynqmp_get_clock_info(void)
FIELD_PREP(CLK_ATTR_NODE_INDEX, i);
zynqmp_pm_clock_get_name(clock[i].clk_id, &name);
/*
* Terminate with NULL character in case name provided by firmware
* is longer and truncated due to size limit.
*/
name.name[sizeof(name.name) - 1] = '\0';
if (!strcmp(name.name, RESERVED_CLK_NAME))
continue;
strncpy(clock[i].clk_name, name.name, MAX_NAME_LEN);
strscpy(clock[i].clk_name, name.name, MAX_NAME_LEN);
}
/* Get topology of all clock */

9
drivers/clk/zynqmp/divider.c
View File

@ -113,17 +113,20 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw,
static void zynqmp_get_divider2_val(struct clk_hw *hw,
unsigned long rate,
struct zynqmp_clk_divider *divider,
int *bestdiv)
u32 *bestdiv)
{
int div1;
int div2;
long error = LONG_MAX;
unsigned long div1_prate;
struct clk_hw *div1_parent_hw;
struct zynqmp_clk_divider *pdivider;
struct clk_hw *div2_parent_hw = clk_hw_get_parent(hw);
struct zynqmp_clk_divider *pdivider =
to_zynqmp_clk_divider(div2_parent_hw);
if (!div2_parent_hw)
return;
pdivider = to_zynqmp_clk_divider(div2_parent_hw);
if (!pdivider)
return;

31
drivers/clk/zynqmp/pll.c
View File

@ -102,26 +102,25 @@ static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
u32 fbdiv;
long rate_div, f;
u32 mult, div;
/* Enable the fractional mode if needed */
rate_div = (rate * FRAC_DIV) / *prate;
f = rate_div % FRAC_DIV;
if (f) {
if (rate > PS_PLL_VCO_MAX) {
fbdiv = rate / PS_PLL_VCO_MAX;
rate = rate / (fbdiv + 1);
}
if (rate < PS_PLL_VCO_MIN) {
fbdiv = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate);
rate = rate * fbdiv;
}
return rate;
/* Let rate fall inside the range PS_PLL_VCO_MIN ~ PS_PLL_VCO_MAX */
if (rate > PS_PLL_VCO_MAX) {
div = DIV_ROUND_UP(rate, PS_PLL_VCO_MAX);
rate = rate / div;
}
if (rate < PS_PLL_VCO_MIN) {
mult = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate);
rate = rate * mult;
}
fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
return *prate * fbdiv;
if (fbdiv < PLL_FBDIV_MIN || fbdiv > PLL_FBDIV_MAX) {
fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
rate = *prate * fbdiv;
}
return rate;
}
/**

2
drivers/staging/Kconfig
View File

@ -62,8 +62,6 @@ source "drivers/staging/gdm724x/Kconfig"
source "drivers/staging/fwserial/Kconfig"
source "drivers/staging/clocking-wizard/Kconfig"
source "drivers/staging/fbtft/Kconfig"
source "drivers/staging/most/Kconfig"

1
drivers/staging/Makefile
View File

@ -21,7 +21,6 @@ obj-$(CONFIG_MFD_NVEC) += nvec/
obj-$(CONFIG_STAGING_BOARD) += board/
obj-$(CONFIG_LTE_GDM724X) += gdm724x/
obj-$(CONFIG_FIREWIRE_SERIAL) += fwserial/
obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clocking-wizard/
obj-$(CONFIG_FB_TFT) += fbtft/
obj-$(CONFIG_MOST) += most/
obj-$(CONFIG_KS7010) += ks7010/

10
drivers/staging/clocking-wizard/Kconfig
View File

@ -1,10 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
#
# Xilinx Clocking Wizard Driver
#
config COMMON_CLK_XLNX_CLKWZRD
tristate "Xilinx Clocking Wizard"
depends on COMMON_CLK && OF && HAS_IOMEM
help
Support for the Xilinx Clocking Wizard IP core clock generator.

2
drivers/staging/clocking-wizard/Makefile
View File

@ -1,2 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o

13
drivers/staging/clocking-wizard/TODO
View File

@ -1,13 +0,0 @@
TODO:
- support for fractional multiplier
- support for fractional divider (output 0 only)
- support for set_rate() operations (may benefit from Stephen Boyd's
refactoring of the clk primitives:
https://lore.kernel.org/lkml/1409957256-23729-1-git-send-email-sboyd@codeaurora.org)
- review arithmetic
- overflow after multiplication?
- maximize accuracy before divisions
Patches to:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Sören Brinkmann <soren.brinkmann@xilinx.com>

30
drivers/staging/clocking-wizard/dt-binding.txt
View File

@ -1,30 +0,0 @@
Binding for Xilinx Clocking Wizard IP Core
This binding uses the common clock binding[1]. Details about the devices can be
found in the product guide[2].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Clocking Wizard Product Guide
https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_1/pg065-clk-wiz.pdf
Required properties:
- compatible: Must be 'xlnx,clocking-wizard'
- reg: Base and size of the cores register space
- clocks: Handle to input clock
- clock-names: Tuple containing 'clk_in1' and 's_axi_aclk'
- clock-output-names: Names for the output clocks
Optional properties:
- speed-grade: Speed grade of the device (valid values are 1..3)
Example:
clock-generator@40040000 {
reg = <0x40040000 0x1000>;
compatible = "xlnx,clocking-wizard";
speed-grade = <1>;
clock-names = "clk_in1", "s_axi_aclk";
clocks = <&clkc 15>, <&clkc 15>;
clock-output-names = "clk_out0", "clk_out1", "clk_out2",
"clk_out3", "clk_out4", "clk_out5",
"clk_out6", "clk_out7";
};

0
include/dt-bindings/clk/lochnagar.h → include/dt-bindings/clock/lochnagar.h
View File

0
include/dt-bindings/clk/versaclock.h → include/dt-bindings/clock/versaclock.h
View File

4
include/linux/clk-provider.h
View File

@ -1454,7 +1454,7 @@ int devm_of_clk_add_hw_provider(struct device *dev,
void *data),
void *data);
void of_clk_del_provider(struct device_node *np);
void devm_of_clk_del_provider(struct device *dev);
struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
void *data);
struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
@ -1491,7 +1491,7 @@ static inline int devm_of_clk_add_hw_provider(struct device *dev,
return 0;
}
static inline void of_clk_del_provider(struct device_node *np) {}
static inline void devm_of_clk_del_provider(struct device *dev) {}
static inline struct clk *of_clk_src_simple_get(
struct of_phandle_args *clkspec, void *data)
{

2
include/linux/clkdev.h
View File

@ -46,6 +46,4 @@ int clk_hw_register_clkdev(struct clk_hw *, const char *, const char *);
int devm_clk_hw_register_clkdev(struct device *dev, struct clk_hw *hw,
const char *con_id, const char *dev_id);
void devm_clk_release_clkdev(struct device *dev, const char *con_id,
const char *dev_id);
#endif