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spi: dw: Explicitly de-assert CS on SPI transfer completion
By design of the currently available native set_cs callback, the CS de-assertion will be done only if it's required by the corresponding controller capability. But in order to pre-fill the Tx FIFO buffer with data during the SPI memory ops execution the SER register needs to be left cleared before that. We'll also need a way to explicitly set and clear the corresponding CS bit at a certain moment of the operation. Let's alter the set_cs function then to also de-activate the CS, when it's required. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Link: https://lore.kernel.org/r/20201007235511.4935-15-Sergey.Semin@baikalelectronics.ru Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -100,7 +100,7 @@ void dw_spi_set_cs(struct spi_device *spi, bool enable)
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*/
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if (cs_high == enable)
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dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
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else if (dws->caps & DW_SPI_CAP_CS_OVERRIDE)
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else
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dw_writel(dws, DW_SPI_SER, 0);
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}
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EXPORT_SYMBOL_GPL(dw_spi_set_cs);
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