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drm/amd/display: Add missing CW4 programming for DCN30

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[Why]
To support inbox1 in CW4 we need to actually program CW4 instead of
region 4 for newer firmware.

This is done correctly on DCN20/DCN21 but this code wasn't added to
DCN30.

[How]
Copy over the missing code. It doesn't need address translation since
DCN30 uses virtual addressing.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nicholas Kazlauskas 2020-07-07 11:37:14 -04:00 committed by Alex Deucher
parent 714ec7a2bd
commit 497f15f2bd
1 changed files with 16 additions and 5 deletions
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21
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
View File

@ -153,11 +153,22 @@ void dmub_dcn30_setup_windows(struct dmub_srv *dmub,
offset = cw4->offset;
REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part);
REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, DMCUB_REGION4_TOP_ADDRESS,
cw4->region.top - cw4->region.base - 1, DMCUB_REGION4_ENABLE,
1);
/* New firmware can support CW4. */
if (dmub->fw_version > DMUB_FW_VERSION(1, 0, 10)) {
REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
DMCUB_REGION3_CW4_ENABLE, 1);
} else {
REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part);
REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0,
DMCUB_REGION4_TOP_ADDRESS,
cw4->region.top - cw4->region.base - 1,
DMCUB_REGION4_ENABLE, 1);
}
offset = cw5->offset;