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phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY
Exynos5440 SoC support has been dropped since commit 8c83315da1 ("ARM:
dts: exynos: Remove Exynos5440"). Rework this driver to support PCIe PHY
variant found in the Exynos5433 SoCs.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
[mszyprow: reworked the driver to support only Exynos5433 variant, rebased
onto current kernel code, rewrote commit message]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
Link: https://lore.kernel.org/r/20201120102627.14450-1-m.szyprowski@samsung.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Jaehoon Chung
Vinod Koul
parent
864788c00f
commit
496db02914
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@ -4,70 +4,41 @@
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*
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* Phy provider for PCIe controller on Exynos SoC series
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*
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* Copyright (C) 2017 Samsung Electronics Co., Ltd.
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* Copyright (C) 2017-2020 Samsung Electronics Co., Ltd.
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* Jaehoon Chung <jh80.chung@samsung.com>
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/init.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/phy/phy.h>
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#include <linux/regmap.h>
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/* PCIe Purple registers */
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#define PCIE_PHY_GLOBAL_RESET 0x000
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#define PCIE_PHY_COMMON_RESET 0x004
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#define PCIE_PHY_CMN_REG 0x008
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#define PCIE_PHY_MAC_RESET 0x00c
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#define PCIE_PHY_PLL_LOCKED 0x010
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#define PCIE_PHY_TRSVREG_RESET 0x020
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#define PCIE_PHY_TRSV_RESET 0x024
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#define PCIE_PHY_OFFSET(x) ((x) * 0x4)
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/* PCIe PHY registers */
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#define PCIE_PHY_IMPEDANCE 0x004
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#define PCIE_PHY_PLL_DIV_0 0x008
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#define PCIE_PHY_PLL_BIAS 0x00c
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#define PCIE_PHY_DCC_FEEDBACK 0x014
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#define PCIE_PHY_PLL_DIV_1 0x05c
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#define PCIE_PHY_COMMON_POWER 0x064
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#define PCIE_PHY_COMMON_PD_CMN BIT(3)
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#define PCIE_PHY_TRSV0_EMP_LVL 0x084
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#define PCIE_PHY_TRSV0_DRV_LVL 0x088
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#define PCIE_PHY_TRSV0_RXCDR 0x0ac
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#define PCIE_PHY_TRSV0_POWER 0x0c4
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#define PCIE_PHY_TRSV0_PD_TSV BIT(7)
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#define PCIE_PHY_TRSV0_LVCC 0x0dc
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#define PCIE_PHY_TRSV1_EMP_LVL 0x144
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#define PCIE_PHY_TRSV1_RXCDR 0x16c
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#define PCIE_PHY_TRSV1_POWER 0x184
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#define PCIE_PHY_TRSV1_PD_TSV BIT(7)
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#define PCIE_PHY_TRSV1_LVCC 0x19c
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#define PCIE_PHY_TRSV2_EMP_LVL 0x204
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#define PCIE_PHY_TRSV2_RXCDR 0x22c
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#define PCIE_PHY_TRSV2_POWER 0x244
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#define PCIE_PHY_TRSV2_PD_TSV BIT(7)
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#define PCIE_PHY_TRSV2_LVCC 0x25c
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#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
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#define PCIE_PHY_TRSV3_RXCDR 0x2ec
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#define PCIE_PHY_TRSV3_POWER 0x304
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#define PCIE_PHY_TRSV3_PD_TSV BIT(7)
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#define PCIE_PHY_TRSV3_LVCC 0x31c
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/* Sysreg FSYS register offsets and bits for Exynos5433 */
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#define PCIE_EXYNOS5433_PHY_MAC_RESET 0x0208
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#define PCIE_MAC_RESET_MASK 0xFF
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#define PCIE_MAC_RESET BIT(4)
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#define PCIE_EXYNOS5433_PHY_L1SUB_CM_CON 0x1010
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#define PCIE_REFCLK_GATING_EN BIT(0)
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#define PCIE_EXYNOS5433_PHY_COMMON_RESET 0x1020
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#define PCIE_PHY_RESET BIT(0)
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#define PCIE_EXYNOS5433_PHY_GLOBAL_RESET 0x1040
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#define PCIE_GLOBAL_RESET BIT(0)
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#define PCIE_REFCLK BIT(1)
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#define PCIE_REFCLK_MASK 0x16
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#define PCIE_APP_REQ_EXIT_L1_MODE BIT(5)
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struct exynos_pcie_phy_data {
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const struct phy_ops *ops;
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};
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/* PMU PCIE PHY isolation control */
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#define EXYNOS5433_PMU_PCIE_PHY_OFFSET 0x730
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/* For Exynos pcie phy */
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struct exynos_pcie_phy {
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const struct exynos_pcie_phy_data *drv_data;
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void __iomem *phy_base;
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void __iomem *blk_base; /* For exynos5440 */
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void __iomem *base;
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struct regmap *pmureg;
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struct regmap *fsysreg;
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};
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static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
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@ -75,153 +46,103 @@ static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
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writel(val, base + offset);
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}
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static u32 exynos_pcie_phy_readl(void __iomem *base, u32 offset)
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{
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return readl(base + offset);
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}
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/* For Exynos5440 specific functions */
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static int exynos5440_pcie_phy_init(struct phy *phy)
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/* Exynos5433 specific functions */
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static int exynos5433_pcie_phy_init(struct phy *phy)
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{
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struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
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/* DCC feedback control off */
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exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
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regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_COMMON_RESET,
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PCIE_PHY_RESET, 1);
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regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_MAC_RESET,
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PCIE_MAC_RESET, 0);
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/* set TX/RX impedance */
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exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
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/* PHY refclk 24MHz */
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regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET,
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PCIE_REFCLK_MASK, PCIE_REFCLK);
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regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET,
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PCIE_GLOBAL_RESET, 0);
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/* set 50Mhz PHY clock */
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exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
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exynos_pcie_phy_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
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/* set TX Differential output for lane 0 */
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exynos_pcie_phy_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
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exynos_pcie_phy_writel(ep->base, 0x11, PCIE_PHY_OFFSET(0x3));
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/* set TX Pre-emphasis Level Control for lane 0 to minimum */
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exynos_pcie_phy_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
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/* band gap reference on */
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exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x20));
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exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x4b));
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/* set RX clock and data recovery bandwidth */
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exynos_pcie_phy_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
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exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
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exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
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exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
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exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
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/* jitter tunning */
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exynos_pcie_phy_writel(ep->base, 0x34, PCIE_PHY_OFFSET(0x4));
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exynos_pcie_phy_writel(ep->base, 0x02, PCIE_PHY_OFFSET(0x7));
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exynos_pcie_phy_writel(ep->base, 0x41, PCIE_PHY_OFFSET(0x21));
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exynos_pcie_phy_writel(ep->base, 0x7F, PCIE_PHY_OFFSET(0x14));
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exynos_pcie_phy_writel(ep->base, 0xC0, PCIE_PHY_OFFSET(0x15));
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exynos_pcie_phy_writel(ep->base, 0x61, PCIE_PHY_OFFSET(0x36));
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/* change TX Pre-emphasis Level Control for lanes */
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exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
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exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
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exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
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exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
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/* D0 uninit.. */
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exynos_pcie_phy_writel(ep->base, 0x44, PCIE_PHY_OFFSET(0x3D));
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/* set LVCC */
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exynos_pcie_phy_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
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exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
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exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
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exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
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/* 24MHz */
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exynos_pcie_phy_writel(ep->base, 0x94, PCIE_PHY_OFFSET(0x8));
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exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x9));
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exynos_pcie_phy_writel(ep->base, 0x93, PCIE_PHY_OFFSET(0xA));
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exynos_pcie_phy_writel(ep->base, 0x6B, PCIE_PHY_OFFSET(0xC));
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exynos_pcie_phy_writel(ep->base, 0xA5, PCIE_PHY_OFFSET(0xF));
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exynos_pcie_phy_writel(ep->base, 0x34, PCIE_PHY_OFFSET(0x16));
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exynos_pcie_phy_writel(ep->base, 0xA3, PCIE_PHY_OFFSET(0x17));
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exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x1A));
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exynos_pcie_phy_writel(ep->base, 0x71, PCIE_PHY_OFFSET(0x23));
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exynos_pcie_phy_writel(ep->base, 0x4C, PCIE_PHY_OFFSET(0x24));
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/* pulse for common reset */
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exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_COMMON_RESET);
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udelay(500);
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exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
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exynos_pcie_phy_writel(ep->base, 0x0E, PCIE_PHY_OFFSET(0x26));
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exynos_pcie_phy_writel(ep->base, 0x14, PCIE_PHY_OFFSET(0x7));
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exynos_pcie_phy_writel(ep->base, 0x48, PCIE_PHY_OFFSET(0x43));
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exynos_pcie_phy_writel(ep->base, 0x44, PCIE_PHY_OFFSET(0x44));
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exynos_pcie_phy_writel(ep->base, 0x03, PCIE_PHY_OFFSET(0x45));
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exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x48));
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exynos_pcie_phy_writel(ep->base, 0x13, PCIE_PHY_OFFSET(0x54));
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exynos_pcie_phy_writel(ep->base, 0x04, PCIE_PHY_OFFSET(0x31));
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exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x32));
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regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_COMMON_RESET,
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PCIE_PHY_RESET, 0);
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regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_MAC_RESET,
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PCIE_MAC_RESET_MASK, PCIE_MAC_RESET);
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return 0;
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}
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static int exynos5440_pcie_phy_power_on(struct phy *phy)
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{
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struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
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u32 val;
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exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
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exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_CMN_REG);
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exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSVREG_RESET);
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exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSV_RESET);
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val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
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val &= ~PCIE_PHY_COMMON_PD_CMN;
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exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
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val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
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val &= ~PCIE_PHY_TRSV0_PD_TSV;
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exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
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val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
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val &= ~PCIE_PHY_TRSV1_PD_TSV;
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exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
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val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
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val &= ~PCIE_PHY_TRSV2_PD_TSV;
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exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
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val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
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val &= ~PCIE_PHY_TRSV3_PD_TSV;
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exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
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return 0;
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}
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static int exynos5440_pcie_phy_power_off(struct phy *phy)
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{
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struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
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u32 val;
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if (readl_poll_timeout(ep->phy_base + PCIE_PHY_PLL_LOCKED, val,
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(val != 0), 1, 500)) {
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dev_err(&phy->dev, "PLL Locked: 0x%x\n", val);
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return -ETIMEDOUT;
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}
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val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
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val |= PCIE_PHY_COMMON_PD_CMN;
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exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
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val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
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val |= PCIE_PHY_TRSV0_PD_TSV;
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exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
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val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
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val |= PCIE_PHY_TRSV1_PD_TSV;
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exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
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val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
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val |= PCIE_PHY_TRSV2_PD_TSV;
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exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
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val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
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val |= PCIE_PHY_TRSV3_PD_TSV;
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exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
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return 0;
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}
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static int exynos5440_pcie_phy_reset(struct phy *phy)
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static int exynos5433_pcie_phy_power_on(struct phy *phy)
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{
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struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
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exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_MAC_RESET);
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exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_GLOBAL_RESET);
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exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_GLOBAL_RESET);
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regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET,
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BIT(0), 1);
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regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET,
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PCIE_APP_REQ_EXIT_L1_MODE, 0);
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regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON,
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PCIE_REFCLK_GATING_EN, 0);
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return 0;
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}
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static const struct phy_ops exynos5440_phy_ops = {
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.init = exynos5440_pcie_phy_init,
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.power_on = exynos5440_pcie_phy_power_on,
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.power_off = exynos5440_pcie_phy_power_off,
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.reset = exynos5440_pcie_phy_reset,
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static int exynos5433_pcie_phy_power_off(struct phy *phy)
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{
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struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
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regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON,
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PCIE_REFCLK_GATING_EN, PCIE_REFCLK_GATING_EN);
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regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET,
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BIT(0), 0);
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return 0;
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}
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static const struct phy_ops exynos5433_phy_ops = {
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.init = exynos5433_pcie_phy_init,
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.power_on = exynos5433_pcie_phy_power_on,
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.power_off = exynos5433_pcie_phy_power_off,
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.owner = THIS_MODULE,
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};
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static const struct exynos_pcie_phy_data exynos5440_pcie_phy_data = {
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.ops = &exynos5440_phy_ops,
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};
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static const struct of_device_id exynos_pcie_phy_match[] = {
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{
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.compatible = "samsung,exynos5440-pcie-phy",
|
||||
.data = &exynos5440_pcie_phy_data,
|
||||
.compatible = "samsung,exynos5433-pcie-phy",
|
||||
},
|
||||
{},
|
||||
};
|
||||
|
|
@ -232,27 +153,30 @@ static int exynos_pcie_phy_probe(struct platform_device *pdev)
|
|||
struct exynos_pcie_phy *exynos_phy;
|
||||
struct phy *generic_phy;
|
||||
struct phy_provider *phy_provider;
|
||||
const struct exynos_pcie_phy_data *drv_data;
|
||||
|
||||
drv_data = of_device_get_match_data(dev);
|
||||
if (!drv_data)
|
||||
return -ENODEV;
|
||||
|
||||
exynos_phy = devm_kzalloc(dev, sizeof(*exynos_phy), GFP_KERNEL);
|
||||
if (!exynos_phy)
|
||||
return -ENOMEM;
|
||||
|
||||
exynos_phy->phy_base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(exynos_phy->phy_base))
|
||||
return PTR_ERR(exynos_phy->phy_base);
|
||||
exynos_phy->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(exynos_phy->base))
|
||||
return PTR_ERR(exynos_phy->base);
|
||||
|
||||
exynos_phy->blk_base = devm_platform_ioremap_resource(pdev, 1);
|
||||
if (IS_ERR(exynos_phy->blk_base))
|
||||
return PTR_ERR(exynos_phy->blk_base);
|
||||
exynos_phy->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
|
||||
"samsung,pmu-syscon");
|
||||
if (IS_ERR(exynos_phy->pmureg)) {
|
||||
dev_err(&pdev->dev, "PMU regmap lookup failed.\n");
|
||||
return PTR_ERR(exynos_phy->pmureg);
|
||||
}
|
||||
|
||||
exynos_phy->drv_data = drv_data;
|
||||
exynos_phy->fsysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
|
||||
"samsung,fsys-sysreg");
|
||||
if (IS_ERR(exynos_phy->fsysreg)) {
|
||||
dev_err(&pdev->dev, "FSYS sysreg regmap lookup failed.\n");
|
||||
return PTR_ERR(exynos_phy->fsysreg);
|
||||
}
|
||||
|
||||
generic_phy = devm_phy_create(dev, dev->of_node, drv_data->ops);
|
||||
generic_phy = devm_phy_create(dev, dev->of_node, &exynos5433_phy_ops);
|
||||
if (IS_ERR(generic_phy)) {
|
||||
dev_err(dev, "failed to create PHY\n");
|
||||
return PTR_ERR(generic_phy);
|
||||
|
|
@ -272,5 +196,4 @@ static struct platform_driver exynos_pcie_phy_driver = {
|
|||
.suppress_bind_attrs = true,
|
||||
}
|
||||
};
|
||||
|
||||
builtin_platform_driver(exynos_pcie_phy_driver);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user