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drm/nv50/pm: use hwsq for engine reclocking too
Idea from Martin Peres, different implementation by me. v2: Martin Peres: - fix mast calculation Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
This commit is contained in:
Ben Skeggs
parent
e495d0d7e3
commit
496a73bbec
@ -354,21 +354,12 @@ nv50_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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struct nv50_pm_state {
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struct nouveau_pm_level *perflvl;
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struct hwsq_ucode eclk_hwsq;
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struct hwsq_ucode mclk_hwsq;
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u32 mscript;
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u32 mmast;
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u32 mctrl;
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u32 mcoef;
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u32 emast;
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u32 nctrl;
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u32 ncoef;
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u32 sctrl;
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u32 scoef;
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u32 amast;
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u32 pdivs;
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};
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static u32
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@ -598,10 +589,11 @@ nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv50_pm_state *info;
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struct hwsq_ucode *hwsq;
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struct pll_lims pll;
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u32 out, mast, divs, ctrl;
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int clk, ret = -EINVAL;
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int N, M, P1, P2;
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u32 out;
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if (dev_priv->chipset == 0xaa ||
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dev_priv->chipset == 0xac)
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@ -622,41 +614,32 @@ nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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info->mscript = perflvl->memscript;
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}
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/* core: for the moment at least, always use nvpll */
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clk = calc_pll(dev, 0x4028, &pll, perflvl->core, &N, &M, &P1);
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if (clk == 0)
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goto error;
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divs = read_div(dev);
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mast = info->mmast;
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info->emast = 0x00000003;
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info->nctrl = 0x80000000 | (P1 << 19) | (P1 << 16);
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info->ncoef = (N << 8) | M;
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/* start building HWSQ script for engine reclocking */
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hwsq = &info->eclk_hwsq;
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hwsq_init(hwsq);
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hwsq_setf(hwsq, 0x10, 0); /* disable bus access */
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hwsq_op5f(hwsq, 0x00, 0x01); /* wait for access disabled? */
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/* shader: tie to nvclk if possible, otherwise use spll. have to be
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* very careful that the shader clock is at least twice the core, or
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* some chipsets will be very unhappy. i expect most or all of these
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* cases will be handled by tying to nvclk, but it's possible there's
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* corners
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*/
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if (P1-- && perflvl->shader == (perflvl->core << 1)) {
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info->emast |= 0x00000020;
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info->sctrl = 0x00000000 | (P1 << 19) | (P1 << 16);
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info->scoef = nv_rd32(dev, 0x004024);
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} else {
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clk = calc_pll(dev, 0x4020, &pll, perflvl->shader, &N, &M, &P1);
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if (clk == 0)
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goto error;
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info->emast |= 0x00000030;
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info->sctrl = 0x80000000 | (P1 << 19) | (P1 << 16);
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info->scoef = (N << 8) | M;
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/* vdec/dom6: switch to "safe" clocks temporarily */
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if (perflvl->vdec) {
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mast &= ~0x00000c00;
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divs &= ~0x00000700;
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}
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if (perflvl->dom6) {
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mast &= ~0x0c000000;
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divs &= ~0x00000007;
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}
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hwsq_wr32(hwsq, 0x00c040, mast);
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/* vdec: avoid modifying xpll until we know exactly how the other
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* clock domains work, i suspect at least some of them can also be
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* tied to xpll...
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*/
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info->amast = nv_rd32(dev, 0x00c040);
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info->pdivs = read_div(dev);
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if (perflvl->vdec) {
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/* see how close we can get using nvclk as a source */
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clk = calc_div(perflvl->core, perflvl->vdec, &P1);
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@ -669,16 +652,14 @@ nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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out = calc_div(out, perflvl->vdec, &P2);
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/* select whichever gets us closest */
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info->amast &= ~0x00000c00;
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info->pdivs &= ~0x00000700;
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if (abs((int)perflvl->vdec - clk) <=
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abs((int)perflvl->vdec - out)) {
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if (dev_priv->chipset != 0x98)
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info->amast |= 0x00000c00;
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info->pdivs |= P1 << 8;
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mast |= 0x00000c00;
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divs |= P1 << 8;
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} else {
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info->amast |= 0x00000800;
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info->pdivs |= P2 << 8;
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mast |= 0x00000800;
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divs |= P2 << 8;
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}
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}
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@ -686,21 +667,82 @@ nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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* of the host clock frequency
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*/
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if (perflvl->dom6) {
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info->amast &= ~0x0c000000;
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if (clk_same(perflvl->dom6, read_clk(dev, clk_src_href))) {
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info->amast |= 0x00000000;
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mast |= 0x00000000;
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} else
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if (clk_same(perflvl->dom6, read_clk(dev, clk_src_hclk))) {
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info->amast |= 0x08000000;
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mast |= 0x08000000;
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} else {
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clk = read_clk(dev, clk_src_hclk) * 3;
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clk = calc_div(clk, perflvl->dom6, &P1);
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info->amast |= 0x0c000000;
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info->pdivs = (info->pdivs & ~0x00000007) | P1;
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mast |= 0x0c000000;
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divs |= P1;
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}
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}
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/* vdec/dom6: complete switch to new clocks */
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switch (dev_priv->chipset) {
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case 0x92:
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case 0x94:
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case 0x96:
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hwsq_wr32(hwsq, 0x004800, divs);
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break;
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default:
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hwsq_wr32(hwsq, 0x004700, divs);
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break;
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}
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hwsq_wr32(hwsq, 0x00c040, mast);
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/* core/shader: make sure sclk/nvclk are disconnected from their
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* PLLs (nvclk to dom6, sclk to hclk)
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*/
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if (dev_priv->chipset < 0x92)
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mast = (mast & ~0x001000b0) | 0x00100080;
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else
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mast = (mast & ~0x000000b3) | 0x00000081;
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hwsq_wr32(hwsq, 0x00c040, mast);
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/* core: for the moment at least, always use nvpll */
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clk = calc_pll(dev, 0x4028, &pll, perflvl->core, &N, &M, &P1);
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if (clk == 0)
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goto error;
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ctrl = nv_rd32(dev, 0x004028) & ~0xc03f0100;
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mast &= ~0x00100000;
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mast |= 3;
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hwsq_wr32(hwsq, 0x004028, 0x80000000 | (P1 << 19) | (P1 << 16) | ctrl);
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hwsq_wr32(hwsq, 0x00402c, (N << 8) | M);
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/* shader: tie to nvclk if possible, otherwise use spll. have to be
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* very careful that the shader clock is at least twice the core, or
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* some chipsets will be very unhappy. i expect most or all of these
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* cases will be handled by tying to nvclk, but it's possible there's
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* corners
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*/
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ctrl = nv_rd32(dev, 0x004020) & ~0xc03f0100;
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if (P1-- && perflvl->shader == (perflvl->core << 1)) {
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hwsq_wr32(hwsq, 0x004020, (P1 << 19) | (P1 << 16) | ctrl);
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hwsq_wr32(hwsq, 0x00c040, 0x00000020 | mast);
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} else {
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clk = calc_pll(dev, 0x4020, &pll, perflvl->shader, &N, &M, &P1);
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if (clk == 0)
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goto error;
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ctrl |= 0x80000000;
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hwsq_wr32(hwsq, 0x004020, (P1 << 19) | (P1 << 16) | ctrl);
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hwsq_wr32(hwsq, 0x004024, (N << 8) | M);
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hwsq_wr32(hwsq, 0x00c040, 0x00000030 | mast);
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}
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hwsq_setf(hwsq, 0x10, 1); /* enable bus access */
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hwsq_op5f(hwsq, 0x00, 0x00); /* wait for access enabled? */
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hwsq_fini(hwsq);
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return info;
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error:
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kfree(info);
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@ -708,7 +750,7 @@ error:
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}
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static int
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prog_mclk(struct drm_device *dev, struct hwsq_ucode *hwsq)
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prog_hwsq(struct drm_device *dev, struct hwsq_ucode *hwsq)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u32 hwsq_data, hwsq_kick;
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@ -748,20 +790,17 @@ prog_mclk(struct drm_device *dev, struct hwsq_ucode *hwsq)
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int
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nv50_pm_clocks_set(struct drm_device *dev, void *data)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv50_pm_state *info = data;
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struct bit_entry M;
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int ret = 0;
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int ret = -EBUSY;
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/* halt and idle execution engines */
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nv_mask(dev, 0x002504, 0x00000001, 0x00000001);
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if (!nv_wait(dev, 0x002504, 0x00000010, 0x00000010))
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goto error;
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goto resume;
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/* memory: it is *very* important we change this first, the ucode
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* we build in pre() now has hardcoded 0xc040 values, which can't
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* change before we execute it or the engine clocks may end up
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* messed up.
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/* program memory clock, if necessary - must come before engine clock
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* reprogramming due to how we construct the hwsq scripts in pre()
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*/
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if (info->mclk_hwsq.len) {
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/* execute some scripts that do ??? from the vbios.. */
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@ -775,42 +814,14 @@ nv50_pm_clocks_set(struct drm_device *dev, void *data)
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nouveau_bios_init_exec(dev, info->mscript);
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}
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ret = prog_mclk(dev, &info->mclk_hwsq);
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ret = prog_hwsq(dev, &info->mclk_hwsq);
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if (ret)
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goto resume;
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}
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/* reclock vdec/dom6 */
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nv_mask(dev, 0x00c040, 0x00000c00, 0x00000000);
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switch (dev_priv->chipset) {
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case 0x92:
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case 0x94:
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case 0x96:
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nv_mask(dev, 0x004800, 0x00000707, info->pdivs);
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break;
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default:
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nv_mask(dev, 0x004700, 0x00000707, info->pdivs);
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break;
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}
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nv_mask(dev, 0x00c040, 0x0c000c00, info->amast);
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/* program engine clocks */
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ret = prog_hwsq(dev, &info->eclk_hwsq);
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/* core/shader: make sure sclk/nvclk are disconnected from their
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* plls (nvclk to dom6, sclk to hclk), modify the plls, and
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* reconnect sclk/nvclk to their new clock source
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*/
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if (dev_priv->chipset < 0x92)
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nv_mask(dev, 0x00c040, 0x001000b0, 0x00100080); /* grrr! */
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else
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nv_mask(dev, 0x00c040, 0x000000b3, 0x00000081);
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nv_mask(dev, 0x004020, 0xc03f0100, info->sctrl);
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nv_wr32(dev, 0x004024, info->scoef);
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nv_mask(dev, 0x004028, 0xc03f0100, info->nctrl);
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nv_wr32(dev, 0x00402c, info->ncoef);
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nv_mask(dev, 0x00c040, 0x00100033, info->emast);
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goto resume;
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error:
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ret = -EBUSY;
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resume:
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nv_mask(dev, 0x002504, 0x00000001, 0x00000000);
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kfree(info);
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