mirror of
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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Conflicts: net/ipv4/arp.c The net/ipv4/arp.c conflict was one commit adding a new local variable while another commit was deleting one. Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
4963ed48f2
@ -57,6 +57,8 @@ used to route Message Signalled Interrupts (MSI) to the CPUs.
|
||||
These nodes must have the following properties:
|
||||
- compatible : Should at least contain "arm,gic-v3-its".
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- msi-controller : Boolean property. Identifies the node as an MSI controller
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- #msi-cells: Must be <1>. The single msi-cell is the DeviceID of the device
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which will generate the MSI.
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- reg: Specifies the base physical address and size of the ITS
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registers.
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@ -83,6 +85,7 @@ Examples:
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gic-its@2c200000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x0 0x2c200000 0 0x200000>;
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};
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};
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@ -107,12 +110,14 @@ Examples:
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gic-its@2c200000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x0 0x2c200000 0 0x200000>;
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};
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gic-its@2c400000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x0 0x2c400000 0 0x200000>;
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};
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};
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@ -497,7 +497,7 @@ cpus {
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};
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idle-states {
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entry-method = "arm,psci";
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entry-method = "psci";
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CPU_RETENTION_0_0: cpu-retention-0-0 {
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compatible = "arm,idle-state";
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@ -16,7 +16,9 @@ properties, each containing a 'gpio-list':
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GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
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of this GPIO for the device. While a non-existent <name> is considered valid
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for compatibility reasons (resolving to the "gpios" property), it is not allowed
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for new bindings.
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for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
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bindings use it, but are only supported for compatibility reasons and should not
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be used for newer bindings since it has been deprecated.
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GPIO properties can contain one or more GPIO phandles, but only in exceptional
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cases should they contain more than one. If your device uses several GPIOs with
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@ -1,10 +1,11 @@
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* Bosch BMA180 triaxial acceleration sensor
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* Bosch BMA180 / BMA250 triaxial acceleration sensor
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http://omapworld.com/BMA180_111_1002839.pdf
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http://ae-bst.resource.bosch.com/media/products/dokumente/bma250/bst-bma250-ds002-05.pdf
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Required properties:
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- compatible : should be "bosch,bma180"
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- compatible : should be "bosch,bma180" or "bosch,bma250"
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- reg : the I2C address of the sensor
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Optional properties:
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@ -13,6 +14,9 @@ Optional properties:
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- interrupts : interrupt mapping for GPIO IRQ, it should by configured with
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flags IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING
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For the bma250 the first interrupt listed must be the one
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connected to the INT1 pin, the second (optional) interrupt
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listed must be the one connected to the INT2 pin.
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Example:
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@ -0,0 +1,36 @@
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* Toradex Colibri VF50 Touchscreen driver
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Required Properties:
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- compatible must be toradex,vf50-touchscreen
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- io-channels: adc channels being used by the Colibri VF50 module
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- xp-gpios: FET gate driver for input of X+
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- xm-gpios: FET gate driver for input of X-
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- yp-gpios: FET gate driver for input of Y+
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- ym-gpios: FET gate driver for input of Y-
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- interrupt-parent: phandle for the interrupt controller
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- interrupts: pen irq interrupt for touch detection
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- pinctrl-names: "idle", "default", "gpios"
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- pinctrl-0: pinctrl node for pen/touch detection state pinmux
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- pinctrl-1: pinctrl node for X/Y and pressure measurement (ADC) state pinmux
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- pinctrl-2: pinctrl node for gpios functioning as FET gate drivers
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- vf50-ts-min-pressure: pressure level at which to stop measuring X/Y values
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Example:
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touchctrl: vf50_touchctrl {
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compatible = "toradex,vf50-touchscreen";
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io-channels = <&adc1 0>,<&adc0 0>,
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<&adc0 1>,<&adc1 2>;
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xp-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
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xm-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
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yp-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
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ym-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
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interrupt-parent = <&gpio0>;
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interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "idle","default","gpios";
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pinctrl-0 = <&pinctrl_touchctrl_idle>;
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pinctrl-1 = <&pinctrl_touchctrl_default>;
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pinctrl-2 = <&pinctrl_touchctrl_gpios>;
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vf50-ts-min-pressure = <200>;
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status = "disabled";
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};
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@ -0,0 +1,36 @@
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* Freescale i.MX6UL Touch Controller
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Required properties:
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- compatible: must be "fsl,imx6ul-tsc".
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- reg: this touch controller address and the ADC2 address.
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- interrupts: the interrupt of this touch controller and ADC2.
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- clocks: the root clock of touch controller and ADC2.
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- clock-names; must be "tsc" and "adc".
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- xnur-gpio: the X- gpio this controller connect to.
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This xnur-gpio returns to low once the finger leave the touch screen (The
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last touch event the touch controller capture).
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Optional properties:
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- measure-delay-time: the value of measure delay time.
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Before X-axis or Y-axis measurement, the screen need some time before
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even potential distribution ready.
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This value depends on the touch screen.
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- pre-charge-time: the touch screen need some time to precharge.
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This value depends on the touch screen.
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Example:
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tsc: tsc@02040000 {
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compatible = "fsl,imx6ul-tsc";
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reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_IPG>,
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<&clks IMX6UL_CLK_ADC2>;
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clock-names = "tsc", "adc";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_tsc>;
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xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
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measure-delay-time = <0xfff>;
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pre-charge-time = <0xffff>;
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status = "okay";
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};
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@ -7,7 +7,8 @@ OHCI and EHCI controllers.
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Required properties:
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- compatible: "renesas,pci-r8a7790" for the R8A7790 SoC;
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"renesas,pci-r8a7791" for the R8A7791 SoC.
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"renesas,pci-r8a7791" for the R8A7791 SoC;
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"renesas,pci-r8a7794" for the R8A7794 SoC.
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- reg: A list of physical regions to access the device: the first is
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the operational registers for the OHCI/EHCI controllers and the
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second is for the bridge configuration and control registers.
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@ -2,7 +2,12 @@ PBIAS internal regulator for SD card dual voltage i/o pads on OMAP SoCs.
|
||||
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Required properties:
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- compatible:
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- "ti,pbias-omap" for OMAP2, OMAP3, OMAP4, OMAP5, DRA7.
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- should be "ti,pbias-dra7" for DRA7
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- should be "ti,pbias-omap2" for OMAP2
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- should be "ti,pbias-omap3" for OMAP3
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- should be "ti,pbias-omap4" for OMAP4
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- should be "ti,pbias-omap5" for OMAP5
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- "ti,pbias-omap" is deprecated
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- reg: pbias register offset from syscon base and size of pbias register.
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- syscon : phandle of the system control module
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- regulator-name : should be
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@ -15,17 +15,18 @@ Required properties:
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- interrupts: Should contain spi interrupt
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- clocks: phandles to input clocks.
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The first should be <&topckgen CLK_TOP_SPI_SEL>.
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The second should be one of the following.
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The first should be one of the following. It's PLL.
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- <&clk26m>: specify parent clock 26MHZ.
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- <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
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It's the default one.
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- <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
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- <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
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- <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
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The second should be <&topckgen CLK_TOP_SPI_SEL>. It's clock mux.
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The third is <&pericfg CLK_PERI_SPI0>. It's clock gate.
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- clock-names: shall be "spi-clk" for the controller clock, and
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"parent-clk" for the parent clock.
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- clock-names: shall be "parent-clk" for the parent clock, "sel-clk" for the
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muxes clock, and "spi-clk" for the clock gate.
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Optional properties:
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- mediatek,pad-select: specify which pins group(ck/mi/mo/cs) spi
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@ -44,8 +45,11 @@ spi: spi@1100a000 {
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#size-cells = <0>;
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reg = <0 0x1100a000 0 0x1000>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_SPI_SEL>, <&topckgen CLK_TOP_SYSPLL3_D2>;
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clock-names = "spi-clk", "parent-clk";
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clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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<&topckgen CLK_TOP_SPI_SEL>,
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<&pericfg CLK_PERI_SPI0>;
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clock-names = "parent-clk", "sel-clk", "spi-clk";
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mediatek,pad-select = <0>;
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status = "disabled";
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};
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@ -55,19 +55,11 @@ of heat dissipation). For example a fan's cooling states correspond to
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the different fan speeds possible. Cooling states are referred to by
|
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single unsigned integers, where larger numbers mean greater heat
|
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dissipation. The precise set of cooling states associated with a device
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(as referred to be the cooling-min-state and cooling-max-state
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(as referred to by the cooling-min-level and cooling-max-level
|
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properties) should be defined in a particular device's binding.
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For more examples of cooling devices, refer to the example sections below.
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Required properties:
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- cooling-min-state: An integer indicating the smallest
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Type: unsigned cooling state accepted. Typically 0.
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Size: one cell
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|
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- cooling-max-state: An integer indicating the largest
|
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Type: unsigned cooling state accepted.
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Size: one cell
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|
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- #cooling-cells: Used to provide cooling device specific information
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||||
Type: unsigned while referring to it. Must be at least 2, in order
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Size: one cell to specify minimum and maximum cooling state used
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@ -77,6 +69,15 @@ Required properties:
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See Cooling device maps section below for more details
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on how consumers refer to cooling devices.
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Optional properties:
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- cooling-min-level: An integer indicating the smallest
|
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Type: unsigned cooling state accepted. Typically 0.
|
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Size: one cell
|
||||
|
||||
- cooling-max-level: An integer indicating the largest
|
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Type: unsigned cooling state accepted.
|
||||
Size: one cell
|
||||
|
||||
* Trip points
|
||||
|
||||
The trip node is a node to describe a point in the temperature domain
|
||||
@ -225,8 +226,8 @@ cpus {
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||||
396000 950000
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||||
198000 850000
|
||||
>;
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cooling-min-state = <0>;
|
||||
cooling-max-state = <3>;
|
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cooling-min-level = <0>;
|
||||
cooling-max-level = <3>;
|
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#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
...
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||||
@ -240,8 +241,8 @@ cpus {
|
||||
*/
|
||||
fan0: fan@0x48 {
|
||||
...
|
||||
cooling-min-state = <0>;
|
||||
cooling-max-state = <9>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <9>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
};
|
||||
|
||||
@ -203,6 +203,7 @@ sitronix Sitronix Technology Corporation
|
||||
skyworks Skyworks Solutions, Inc.
|
||||
smsc Standard Microsystems Corporation
|
||||
snps Synopsys, Inc.
|
||||
socionext Socionext Inc.
|
||||
solidrun SolidRun
|
||||
solomon Solomon Systech Limited
|
||||
sony Sony Corporation
|
||||
|
||||
@ -0,0 +1,35 @@
|
||||
* Atmel SAMA5D4 Watchdog Timer (WDT) Controller
|
||||
|
||||
Required properties:
|
||||
- compatible: "atmel,sama5d4-wdt"
|
||||
- reg: base physical address and length of memory mapped region.
|
||||
|
||||
Optional properties:
|
||||
- timeout-sec: watchdog timeout value (in seconds).
|
||||
- interrupts: interrupt number to the CPU.
|
||||
- atmel,watchdog-type: should be "hardware" or "software".
|
||||
"hardware": enable watchdog fault reset. A watchdog fault triggers
|
||||
watchdog reset.
|
||||
"software": enable watchdog fault interrupt. A watchdog fault asserts
|
||||
watchdog interrupt.
|
||||
- atmel,idle-halt: present if you want to stop the watchdog when the CPU is
|
||||
in idle state.
|
||||
CAUTION: This property should be used with care, it actually makes the
|
||||
watchdog not counting when the CPU is in idle state, therefore the
|
||||
watchdog reset time depends on mean CPU usage and will not reset at all
|
||||
if the CPU stop working while it is in idle state, which is probably
|
||||
not what you want.
|
||||
- atmel,dbg-halt: present if you want to stop the watchdog when the CPU is
|
||||
in debug state.
|
||||
|
||||
Example:
|
||||
watchdog@fc068640 {
|
||||
compatible = "atmel,sama5d4-wdt";
|
||||
reg = <0xfc068640 0x10>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
timeout-sec = <10>;
|
||||
atmel,watchdog-type = "hardware";
|
||||
atmel,dbg-halt;
|
||||
atmel,idle-halt;
|
||||
status = "okay";
|
||||
};
|
||||
19
Documentation/devicetree/bindings/watchdog/lpc18xx-wdt.txt
Normal file
19
Documentation/devicetree/bindings/watchdog/lpc18xx-wdt.txt
Normal file
@ -0,0 +1,19 @@
|
||||
* NXP LPC18xx Watchdog Timer (WDT)
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "nxp,lpc1850-wwdt"
|
||||
- reg: Should contain WDT registers location and length
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
- clock-names: Should contain "wdtclk" and "reg"; the watchdog counter
|
||||
clock and register interface clock respectively.
|
||||
- interrupts: Should contain WDT interrupt
|
||||
|
||||
Examples:
|
||||
|
||||
watchdog@40080000 {
|
||||
compatible = "nxp,lpc1850-wwdt";
|
||||
reg = <0x40080000 0x24>;
|
||||
clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>;
|
||||
clock-names = "wdtclk", "reg";
|
||||
interrupts = <49>;
|
||||
};
|
||||
@ -21,8 +21,8 @@ exact way to do it depends on the GPIO controller providing the GPIOs, see the
|
||||
device tree bindings for your controller.
|
||||
|
||||
GPIOs mappings are defined in the consumer device's node, in a property named
|
||||
<function>-gpios, where <function> is the function the driver will request
|
||||
through gpiod_get(). For example:
|
||||
either <function>-gpios or <function>-gpio, where <function> is the function
|
||||
the driver will request through gpiod_get(). For example:
|
||||
|
||||
foo_device {
|
||||
compatible = "acme,foo";
|
||||
@ -31,7 +31,7 @@ through gpiod_get(). For example:
|
||||
<&gpio 16 GPIO_ACTIVE_HIGH>, /* green */
|
||||
<&gpio 17 GPIO_ACTIVE_HIGH>; /* blue */
|
||||
|
||||
power-gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
|
||||
power-gpio = <&gpio 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
This property will make GPIOs 15, 16 and 17 available to the driver under the
|
||||
@ -39,15 +39,24 @@ This property will make GPIOs 15, 16 and 17 available to the driver under the
|
||||
|
||||
struct gpio_desc *red, *green, *blue, *power;
|
||||
|
||||
red = gpiod_get_index(dev, "led", 0);
|
||||
green = gpiod_get_index(dev, "led", 1);
|
||||
blue = gpiod_get_index(dev, "led", 2);
|
||||
red = gpiod_get_index(dev, "led", 0, GPIOD_OUT_HIGH);
|
||||
green = gpiod_get_index(dev, "led", 1, GPIOD_OUT_HIGH);
|
||||
blue = gpiod_get_index(dev, "led", 2, GPIOD_OUT_HIGH);
|
||||
|
||||
power = gpiod_get(dev, "power");
|
||||
power = gpiod_get(dev, "power", GPIOD_OUT_HIGH);
|
||||
|
||||
The led GPIOs will be active-high, while the power GPIO will be active-low (i.e.
|
||||
gpiod_is_active_low(power) will be true).
|
||||
|
||||
The second parameter of the gpiod_get() functions, the con_id string, has to be
|
||||
the <function>-prefix of the GPIO suffixes ("gpios" or "gpio", automatically
|
||||
looked up by the gpiod functions internally) used in the device tree. With above
|
||||
"led-gpios" example, use the prefix without the "-" as con_id parameter: "led".
|
||||
|
||||
Internally, the GPIO subsystem prefixes the GPIO suffix ("gpios" or "gpio")
|
||||
with the string passed in con_id to get the resulting string
|
||||
(snprintf(... "%s-%s", con_id, gpio_suffixes[]).
|
||||
|
||||
ACPI
|
||||
----
|
||||
ACPI also supports function names for GPIOs in a similar fashion to DT.
|
||||
@ -142,13 +151,14 @@ The driver controlling "foo.0" will then be able to obtain its GPIOs as follows:
|
||||
|
||||
struct gpio_desc *red, *green, *blue, *power;
|
||||
|
||||
red = gpiod_get_index(dev, "led", 0);
|
||||
green = gpiod_get_index(dev, "led", 1);
|
||||
blue = gpiod_get_index(dev, "led", 2);
|
||||
red = gpiod_get_index(dev, "led", 0, GPIOD_OUT_HIGH);
|
||||
green = gpiod_get_index(dev, "led", 1, GPIOD_OUT_HIGH);
|
||||
blue = gpiod_get_index(dev, "led", 2, GPIOD_OUT_HIGH);
|
||||
|
||||
power = gpiod_get(dev, "power");
|
||||
gpiod_direction_output(power, 1);
|
||||
power = gpiod_get(dev, "power", GPIOD_OUT_HIGH);
|
||||
|
||||
Since the "power" GPIO is mapped as active-low, its actual signal will be 0
|
||||
after this code. Contrary to the legacy integer GPIO interface, the active-low
|
||||
property is handled during mapping and is thus transparent to GPIO consumers.
|
||||
Since the "led" GPIOs are mapped as active-high, this example will switch their
|
||||
signals to 1, i.e. enabling the LEDs. And for the "power" GPIO, which is mapped
|
||||
as active-low, its actual signal will be 0 after this code. Contrary to the legacy
|
||||
integer GPIO interface, the active-low property is handled during mapping and is
|
||||
thus transparent to GPIO consumers.
|
||||
|
||||
@ -39,6 +39,9 @@ device that displays digits), an additional index argument can be specified:
|
||||
const char *con_id, unsigned int idx,
|
||||
enum gpiod_flags flags)
|
||||
|
||||
For a more detailed description of the con_id parameter in the DeviceTree case
|
||||
see Documentation/gpio/board.txt
|
||||
|
||||
The flags parameter is used to optionally specify a direction and initial value
|
||||
for the GPIO. Values can be:
|
||||
|
||||
|
||||
@ -32,6 +32,10 @@ Supported chips:
|
||||
Prefix: 'nct6792'
|
||||
Addresses scanned: ISA address retrieved from Super I/O registers
|
||||
Datasheet: Available from Nuvoton upon request
|
||||
* Nuvoton NCT6793D
|
||||
Prefix: 'nct6793'
|
||||
Addresses scanned: ISA address retrieved from Super I/O registers
|
||||
Datasheet: Available from Nuvoton upon request
|
||||
|
||||
Authors:
|
||||
Guenter Roeck <linux@roeck-us.net>
|
||||
|
||||
96
Documentation/networking/vrf.txt
Normal file
96
Documentation/networking/vrf.txt
Normal file
@ -0,0 +1,96 @@
|
||||
Virtual Routing and Forwarding (VRF)
|
||||
====================================
|
||||
The VRF device combined with ip rules provides the ability to create virtual
|
||||
routing and forwarding domains (aka VRFs, VRF-lite to be specific) in the
|
||||
Linux network stack. One use case is the multi-tenancy problem where each
|
||||
tenant has their own unique routing tables and in the very least need
|
||||
different default gateways.
|
||||
|
||||
Processes can be "VRF aware" by binding a socket to the VRF device. Packets
|
||||
through the socket then use the routing table associated with the VRF
|
||||
device. An important feature of the VRF device implementation is that it
|
||||
impacts only Layer 3 and above so L2 tools (e.g., LLDP) are not affected
|
||||
(ie., they do not need to be run in each VRF). The design also allows
|
||||
the use of higher priority ip rules (Policy Based Routing, PBR) to take
|
||||
precedence over the VRF device rules directing specific traffic as desired.
|
||||
|
||||
In addition, VRF devices allow VRFs to be nested within namespaces. For
|
||||
example network namespaces provide separation of network interfaces at L1
|
||||
(Layer 1 separation), VLANs on the interfaces within a namespace provide
|
||||
L2 separation and then VRF devices provide L3 separation.
|
||||
|
||||
Design
|
||||
------
|
||||
A VRF device is created with an associated route table. Network interfaces
|
||||
are then enslaved to a VRF device:
|
||||
|
||||
+-----------------------------+
|
||||
| vrf-blue | ===> route table 10
|
||||
+-----------------------------+
|
||||
| | |
|
||||
+------+ +------+ +-------------+
|
||||
| eth1 | | eth2 | ... | bond1 |
|
||||
+------+ +------+ +-------------+
|
||||
| |
|
||||
+------+ +------+
|
||||
| eth8 | | eth9 |
|
||||
+------+ +------+
|
||||
|
||||
Packets received on an enslaved device and are switched to the VRF device
|
||||
using an rx_handler which gives the impression that packets flow through
|
||||
the VRF device. Similarly on egress routing rules are used to send packets
|
||||
to the VRF device driver before getting sent out the actual interface. This
|
||||
allows tcpdump on a VRF device to capture all packets into and out of the
|
||||
VRF as a whole.[1] Similiarly, netfilter [2] and tc rules can be applied
|
||||
using the VRF device to specify rules that apply to the VRF domain as a whole.
|
||||
|
||||
[1] Packets in the forwarded state do not flow through the device, so those
|
||||
packets are not seen by tcpdump. Will revisit this limitation in a
|
||||
future release.
|
||||
|
||||
[2] Iptables on ingress is limited to NF_INET_PRE_ROUTING only with skb->dev
|
||||
set to real ingress device and egress is limited to NF_INET_POST_ROUTING.
|
||||
Will revisit this limitation in a future release.
|
||||
|
||||
|
||||
Setup
|
||||
-----
|
||||
1. VRF device is created with an association to a FIB table.
|
||||
e.g, ip link add vrf-blue type vrf table 10
|
||||
ip link set dev vrf-blue up
|
||||
|
||||
2. Rules are added that send lookups to the associated FIB table when the
|
||||
iif or oif is the VRF device. e.g.,
|
||||
ip ru add oif vrf-blue table 10
|
||||
ip ru add iif vrf-blue table 10
|
||||
|
||||
Set the default route for the table (and hence default route for the VRF).
|
||||
e.g, ip route add table 10 prohibit default
|
||||
|
||||
3. Enslave L3 interfaces to a VRF device.
|
||||
e.g, ip link set dev eth1 master vrf-blue
|
||||
|
||||
Local and connected routes for enslaved devices are automatically moved to
|
||||
the table associated with VRF device. Any additional routes depending on
|
||||
the enslaved device will need to be reinserted following the enslavement.
|
||||
|
||||
4. Additional VRF routes are added to associated table.
|
||||
e.g., ip route add table 10 ...
|
||||
|
||||
|
||||
Applications
|
||||
------------
|
||||
Applications that are to work within a VRF need to bind their socket to the
|
||||
VRF device:
|
||||
|
||||
setsockopt(sd, SOL_SOCKET, SO_BINDTODEVICE, dev, strlen(dev)+1);
|
||||
|
||||
or to specify the output device using cmsg and IP_PKTINFO.
|
||||
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
VRF device currently only works for IPv4. Support for IPv6 is under development.
|
||||
|
||||
Index of original ingress interface is not available via cmsg. Will address
|
||||
soon.
|
||||
@ -15,8 +15,8 @@ The updated API replacements are:
|
||||
|
||||
DEFINE_STATIC_KEY_TRUE(key);
|
||||
DEFINE_STATIC_KEY_FALSE(key);
|
||||
static_key_likely()
|
||||
statick_key_unlikely()
|
||||
static_branch_likely()
|
||||
static_branch_unlikely()
|
||||
|
||||
0) Abstract
|
||||
|
||||
|
||||
@ -54,13 +54,15 @@ default_qdisc
|
||||
--------------
|
||||
|
||||
The default queuing discipline to use for network devices. This allows
|
||||
overriding the default queue discipline of pfifo_fast with an
|
||||
alternative. Since the default queuing discipline is created with the
|
||||
no additional parameters so is best suited to queuing disciplines that
|
||||
work well without configuration like stochastic fair queue (sfq),
|
||||
CoDel (codel) or fair queue CoDel (fq_codel). Don't use queuing disciplines
|
||||
like Hierarchical Token Bucket or Deficit Round Robin which require setting
|
||||
up classes and bandwidths.
|
||||
overriding the default of pfifo_fast with an alternative. Since the default
|
||||
queuing discipline is created without additional parameters so is best suited
|
||||
to queuing disciplines that work well without configuration like stochastic
|
||||
fair queue (sfq), CoDel (codel) or fair queue CoDel (fq_codel). Don't use
|
||||
queuing disciplines like Hierarchical Token Bucket or Deficit Round Robin
|
||||
which require setting up classes and bandwidths. Note that physical multiqueue
|
||||
interfaces still use mq as root qdisc, which in turn uses this default for its
|
||||
leaves. Virtual devices (like e.g. lo or veth) ignore this setting and instead
|
||||
default to noqueue.
|
||||
Default: pfifo_fast
|
||||
|
||||
busy_read
|
||||
|
||||
@ -4,7 +4,7 @@ Power allocator governor tunables
|
||||
Trip points
|
||||
-----------
|
||||
|
||||
The governor requires the following two passive trip points:
|
||||
The governor works optimally with the following two passive trip points:
|
||||
|
||||
1. "switch on" trip point: temperature above which the governor
|
||||
control loop starts operating. This is the first passive trip
|
||||
|
||||
@ -180,6 +180,7 @@ Thermal zone device sys I/F, created once it's registered:
|
||||
|---temp: Current temperature
|
||||
|---mode: Working mode of the thermal zone
|
||||
|---policy: Thermal governor used for this zone
|
||||
|---available_policies: Available thermal governors for this zone
|
||||
|---trip_point_[0-*]_temp: Trip point temperature
|
||||
|---trip_point_[0-*]_type: Trip point type
|
||||
|---trip_point_[0-*]_hyst: Hysteresis value for this trip point
|
||||
@ -256,6 +257,10 @@ policy
|
||||
One of the various thermal governors used for a particular zone.
|
||||
RW, Required
|
||||
|
||||
available_policies
|
||||
Available thermal governors which can be used for a particular zone.
|
||||
RO, Required
|
||||
|
||||
trip_point_[0-*]_temp
|
||||
The temperature above which trip point will be fired.
|
||||
Unit: millidegree Celsius
|
||||
@ -417,6 +422,7 @@ method, the sys I/F structure will be built like this:
|
||||
|---temp: 37000
|
||||
|---mode: enabled
|
||||
|---policy: step_wise
|
||||
|---available_policies: step_wise fair_share
|
||||
|---trip_point_0_temp: 100000
|
||||
|---trip_point_0_type: critical
|
||||
|---trip_point_1_temp: 80000
|
||||
|
||||
@ -41,6 +41,7 @@ static void term(int sig)
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
int flags;
|
||||
unsigned int ping_rate = 1;
|
||||
|
||||
fd = open("/dev/watchdog", O_WRONLY);
|
||||
|
||||
@ -63,22 +64,33 @@ int main(int argc, char *argv[])
|
||||
fprintf(stderr, "Watchdog card enabled.\n");
|
||||
fflush(stderr);
|
||||
goto end;
|
||||
} else if (!strncasecmp(argv[1], "-t", 2) && argv[2]) {
|
||||
flags = atoi(argv[2]);
|
||||
ioctl(fd, WDIOC_SETTIMEOUT, &flags);
|
||||
fprintf(stderr, "Watchdog timeout set to %u seconds.\n", flags);
|
||||
fflush(stderr);
|
||||
goto end;
|
||||
} else if (!strncasecmp(argv[1], "-p", 2) && argv[2]) {
|
||||
ping_rate = strtoul(argv[2], NULL, 0);
|
||||
fprintf(stderr, "Watchdog ping rate set to %u seconds.\n", ping_rate);
|
||||
fflush(stderr);
|
||||
} else {
|
||||
fprintf(stderr, "-d to disable, -e to enable.\n");
|
||||
fprintf(stderr, "-d to disable, -e to enable, -t <n> to set " \
|
||||
"the timeout,\n-p <n> to set the ping rate, and \n");
|
||||
fprintf(stderr, "run by itself to tick the card.\n");
|
||||
fflush(stderr);
|
||||
goto end;
|
||||
}
|
||||
} else {
|
||||
fprintf(stderr, "Watchdog Ticking Away!\n");
|
||||
fflush(stderr);
|
||||
}
|
||||
|
||||
fprintf(stderr, "Watchdog Ticking Away!\n");
|
||||
fflush(stderr);
|
||||
|
||||
signal(SIGINT, term);
|
||||
|
||||
while(1) {
|
||||
keep_alive();
|
||||
sleep(1);
|
||||
sleep(ping_rate);
|
||||
}
|
||||
end:
|
||||
close(fd);
|
||||
|
||||
42
MAINTAINERS
42
MAINTAINERS
@ -808,6 +808,13 @@ S: Maintained
|
||||
F: drivers/video/fbdev/arcfb.c
|
||||
F: drivers/video/fbdev/core/fb_defio.c
|
||||
|
||||
ARCNET NETWORK LAYER
|
||||
M: Michael Grzeschik <m.grzeschik@pengutronix.de>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/net/arcnet/
|
||||
F: include/uapi/linux/if_arcnet.h
|
||||
|
||||
ARM MFM AND FLOPPY DRIVERS
|
||||
M: Ian Molton <spyro@f2s.com>
|
||||
S: Maintained
|
||||
@ -6452,11 +6459,11 @@ F: drivers/hwmon/ltc4261.c
|
||||
LTP (Linux Test Project)
|
||||
M: Mike Frysinger <vapier@gentoo.org>
|
||||
M: Cyril Hrubis <chrubis@suse.cz>
|
||||
M: Wanlong Gao <gaowanlong@cn.fujitsu.com>
|
||||
M: Wanlong Gao <wanlong.gao@gmail.com>
|
||||
M: Jan Stancek <jstancek@redhat.com>
|
||||
M: Stanislav Kholmanskikh <stanislav.kholmanskikh@oracle.com>
|
||||
M: Alexey Kodanev <alexey.kodanev@oracle.com>
|
||||
L: ltp-list@lists.sourceforge.net (subscribers-only)
|
||||
L: ltp@lists.linux.it (subscribers-only)
|
||||
W: http://linux-test-project.github.io/
|
||||
T: git git://github.com/linux-test-project/ltp.git
|
||||
S: Maintained
|
||||
@ -6789,6 +6796,14 @@ W: http://www.mellanox.com
|
||||
Q: http://patchwork.ozlabs.org/project/netdev/list/
|
||||
F: drivers/net/ethernet/mellanox/mlxsw/
|
||||
|
||||
MEMBARRIER SUPPORT
|
||||
M: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
|
||||
M: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Supported
|
||||
F: kernel/membarrier.c
|
||||
F: include/uapi/linux/membarrier.h
|
||||
|
||||
MEMORY MANAGEMENT
|
||||
L: linux-mm@kvack.org
|
||||
W: http://www.linux-mm.org
|
||||
@ -7395,6 +7410,7 @@ NTB DRIVER CORE
|
||||
M: Jon Mason <jdmason@kudzu.us>
|
||||
M: Dave Jiang <dave.jiang@intel.com>
|
||||
M: Allen Hubbe <Allen.Hubbe@emc.com>
|
||||
L: linux-ntb@googlegroups.com
|
||||
S: Supported
|
||||
W: https://github.com/jonmason/ntb/wiki
|
||||
T: git git://github.com/jonmason/ntb.git
|
||||
@ -7406,6 +7422,7 @@ F: include/linux/ntb_transport.h
|
||||
NTB INTEL DRIVER
|
||||
M: Jon Mason <jdmason@kudzu.us>
|
||||
M: Dave Jiang <dave.jiang@intel.com>
|
||||
L: linux-ntb@googlegroups.com
|
||||
S: Supported
|
||||
W: https://github.com/jonmason/ntb/wiki
|
||||
T: git git://github.com/jonmason/ntb.git
|
||||
@ -8489,7 +8506,6 @@ F: Documentation/networking/LICENSE.qla3xxx
|
||||
F: drivers/net/ethernet/qlogic/qla3xxx.*
|
||||
|
||||
QLOGIC QLCNIC (1/10)Gb ETHERNET DRIVER
|
||||
M: Shahed Shaikh <shahed.shaikh@qlogic.com>
|
||||
M: Dept-GELinuxNICDev@qlogic.com
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
@ -10327,6 +10343,16 @@ F: include/uapi/linux/thermal.h
|
||||
F: include/linux/cpu_cooling.h
|
||||
F: Documentation/devicetree/bindings/thermal/
|
||||
|
||||
THERMAL/CPU_COOLING
|
||||
M: Amit Daniel Kachhap <amit.kachhap@gmail.com>
|
||||
M: Viresh Kumar <viresh.kumar@linaro.org>
|
||||
M: Javi Merino <javi.merino@arm.com>
|
||||
L: linux-pm@vger.kernel.org
|
||||
S: Supported
|
||||
F: Documentation/thermal/cpu-cooling-api.txt
|
||||
F: drivers/thermal/cpu_cooling.c
|
||||
F: include/linux/cpu_cooling.h
|
||||
|
||||
THINGM BLINK(1) USB RGB LED DRIVER
|
||||
M: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
|
||||
S: Maintained
|
||||
@ -11228,7 +11254,6 @@ VOLTAGE AND CURRENT REGULATOR FRAMEWORK
|
||||
M: Liam Girdwood <lgirdwood@gmail.com>
|
||||
M: Mark Brown <broonie@kernel.org>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
W: http://opensource.wolfsonmicro.com/node/15
|
||||
W: http://www.slimlogic.co.uk/?p=48
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git
|
||||
S: Supported
|
||||
@ -11242,6 +11267,7 @@ L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/net/vrf.c
|
||||
F: include/net/vrf.h
|
||||
F: Documentation/networking/vrf.txt
|
||||
|
||||
VT1211 HARDWARE MONITOR DRIVER
|
||||
M: Juerg Haefliger <juergh@gmail.com>
|
||||
@ -11357,17 +11383,15 @@ WM97XX TOUCHSCREEN DRIVERS
|
||||
M: Mark Brown <broonie@kernel.org>
|
||||
M: Liam Girdwood <lrg@slimlogic.co.uk>
|
||||
L: linux-input@vger.kernel.org
|
||||
T: git git://opensource.wolfsonmicro.com/linux-2.6-touch
|
||||
W: http://opensource.wolfsonmicro.com/node/7
|
||||
W: https://github.com/CirrusLogic/linux-drivers/wiki
|
||||
S: Supported
|
||||
F: drivers/input/touchscreen/*wm97*
|
||||
F: include/linux/wm97xx.h
|
||||
|
||||
WOLFSON MICROELECTRONICS DRIVERS
|
||||
L: patches@opensource.wolfsonmicro.com
|
||||
T: git git://opensource.wolfsonmicro.com/linux-2.6-asoc
|
||||
T: git git://opensource.wolfsonmicro.com/linux-2.6-audioplus
|
||||
W: http://opensource.wolfsonmicro.com/content/linux-drivers-wolfson-devices
|
||||
T: git https://github.com/CirrusLogic/linux-drivers.git
|
||||
W: https://github.com/CirrusLogic/linux-drivers/wiki
|
||||
S: Supported
|
||||
F: Documentation/hwmon/wm83??
|
||||
F: arch/arm/mach-s3c64xx/mach-crag6410*
|
||||
|
||||
4
Makefile
4
Makefile
@ -1,7 +1,7 @@
|
||||
VERSION = 4
|
||||
PATCHLEVEL = 2
|
||||
PATCHLEVEL = 3
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION =
|
||||
EXTRAVERSION = -rc2
|
||||
NAME = Hurr durr I'ma sheep
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
||||
@ -297,7 +297,9 @@ static inline void __iomem * ioremap_nocache(unsigned long offset,
|
||||
unsigned long size)
|
||||
{
|
||||
return ioremap(offset, size);
|
||||
}
|
||||
}
|
||||
|
||||
#define ioremap_uc ioremap_nocache
|
||||
|
||||
static inline void iounmap(volatile void __iomem *addr)
|
||||
{
|
||||
|
||||
@ -117,6 +117,6 @@ handle_irq(int irq)
|
||||
}
|
||||
|
||||
irq_enter();
|
||||
generic_handle_irq_desc(irq, desc);
|
||||
generic_handle_irq_desc(desc);
|
||||
irq_exit();
|
||||
}
|
||||
|
||||
@ -242,7 +242,12 @@ pci_restore_srm_config(void)
|
||||
|
||||
void pcibios_fixup_bus(struct pci_bus *bus)
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
struct pci_dev *dev = bus->self;
|
||||
|
||||
if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
|
||||
(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
|
||||
pci_read_bridge_bases(bus);
|
||||
}
|
||||
|
||||
list_for_each_entry(dev, &bus->devices, bus_list) {
|
||||
pdev_save_srm_config(dev);
|
||||
|
||||
@ -30,6 +30,7 @@ __delay(int loops)
|
||||
" bgt %0,1b"
|
||||
: "=&r" (tmp), "=r" (loops) : "1"(loops));
|
||||
}
|
||||
EXPORT_SYMBOL(__delay);
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
#define LPJ cpu_data[smp_processor_id()].loops_per_jiffy
|
||||
|
||||
@ -252,7 +252,7 @@ static struct irq_chip idu_irq_chip = {
|
||||
|
||||
static int idu_first_irq;
|
||||
|
||||
static void idu_cascade_isr(unsigned int __core_irq, struct irq_desc *desc)
|
||||
static void idu_cascade_isr(struct irq_desc *desc)
|
||||
{
|
||||
struct irq_domain *domain = irq_desc_get_handler_data(desc);
|
||||
unsigned int core_irq = irq_desc_get_irq(desc);
|
||||
|
||||
@ -402,6 +402,8 @@ static void __init axs103_early_init(void)
|
||||
unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
|
||||
if (num_cores > 2)
|
||||
arc_set_core_freq(50 * 1000000);
|
||||
else if (num_cores == 2)
|
||||
arc_set_core_freq(75 * 1000000);
|
||||
#endif
|
||||
|
||||
switch (arc_get_core_freq()/1000000) {
|
||||
|
||||
@ -54,6 +54,14 @@ AS += -EL
|
||||
LD += -EL
|
||||
endif
|
||||
|
||||
#
|
||||
# The Scalar Replacement of Aggregates (SRA) optimization pass in GCC 4.9 and
|
||||
# later may result in code being generated that handles signed short and signed
|
||||
# char struct members incorrectly. So disable it.
|
||||
# (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65932)
|
||||
#
|
||||
KBUILD_CFLAGS += $(call cc-option,-fno-ipa-sra)
|
||||
|
||||
# This selects which instruction set is used.
|
||||
# Note that GCC does not numerically define an architecture version
|
||||
# macro, but instead defines a whole series of macros which makes
|
||||
|
||||
@ -95,7 +95,7 @@ void it8152_init_irq(void)
|
||||
}
|
||||
}
|
||||
|
||||
void it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
|
||||
void it8152_irq_demux(struct irq_desc *desc)
|
||||
{
|
||||
int bits_pd, bits_lp, bits_ld;
|
||||
int i;
|
||||
|
||||
@ -138,7 +138,7 @@ static struct locomo_dev_info locomo_devices[] = {
|
||||
},
|
||||
};
|
||||
|
||||
static void locomo_handler(unsigned int __irq, struct irq_desc *desc)
|
||||
static void locomo_handler(struct irq_desc *desc)
|
||||
{
|
||||
struct locomo *lchip = irq_desc_get_chip_data(desc);
|
||||
int req, i;
|
||||
|
||||
@ -196,10 +196,8 @@ static struct sa1111_dev_info sa1111_devices[] = {
|
||||
* active IRQs causes the interrupt output to pulse, the upper levels
|
||||
* will call us again if there are more interrupts to process.
|
||||
*/
|
||||
static void
|
||||
sa1111_irq_handler(unsigned int __irq, struct irq_desc *desc)
|
||||
static void sa1111_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
unsigned int irq = irq_desc_get_irq(desc);
|
||||
unsigned int stat0, stat1, i;
|
||||
struct sa1111 *sachip = irq_desc_get_handler_data(desc);
|
||||
void __iomem *mapbase = sachip->base + SA1111_INTC;
|
||||
@ -214,7 +212,7 @@ sa1111_irq_handler(unsigned int __irq, struct irq_desc *desc)
|
||||
sa1111_writel(stat1, mapbase + SA1111_INTSTATCLR1);
|
||||
|
||||
if (stat0 == 0 && stat1 == 0) {
|
||||
do_bad_IRQ(irq, desc);
|
||||
do_bad_IRQ(desc);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
@ -491,11 +491,6 @@ THUMB( orr \reg , \reg , #PSR_T_BIT )
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro uaccess_save_and_disable, tmp
|
||||
uaccess_save \tmp
|
||||
uaccess_disable \tmp
|
||||
.endm
|
||||
|
||||
.irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
|
||||
.macro ret\c, reg
|
||||
#if __LINUX_ARM_ARCH__ < 6
|
||||
|
||||
@ -40,6 +40,7 @@ do { \
|
||||
"2:\t.asciz " #__file "\n" \
|
||||
".popsection\n" \
|
||||
".pushsection __bug_table,\"a\"\n" \
|
||||
".align 2\n" \
|
||||
"3:\t.word 1b, 2b\n" \
|
||||
"\t.hword " #__line ", 0\n" \
|
||||
".popsection"); \
|
||||
|
||||
@ -12,6 +12,7 @@
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <asm/barrier.h>
|
||||
#include <asm/thread_info.h>
|
||||
#endif
|
||||
|
||||
/*
|
||||
@ -89,7 +90,8 @@ static inline unsigned int get_domain(void)
|
||||
|
||||
asm(
|
||||
"mrc p15, 0, %0, c3, c0 @ get domain"
|
||||
: "=r" (domain));
|
||||
: "=r" (domain)
|
||||
: "m" (current_thread_info()->cpu_domain));
|
||||
|
||||
return domain;
|
||||
}
|
||||
@ -98,7 +100,7 @@ static inline void set_domain(unsigned val)
|
||||
{
|
||||
asm volatile(
|
||||
"mcr p15, 0, %0, c3, c0 @ set domain"
|
||||
: : "r" (val));
|
||||
: : "r" (val) : "memory");
|
||||
isb();
|
||||
}
|
||||
|
||||
|
||||
@ -106,7 +106,7 @@ extern void __iomem *it8152_base_address;
|
||||
struct pci_dev;
|
||||
struct pci_sys_data;
|
||||
|
||||
extern void it8152_irq_demux(unsigned int irq, struct irq_desc *desc);
|
||||
extern void it8152_irq_demux(struct irq_desc *desc);
|
||||
extern void it8152_init_irq(void);
|
||||
extern int it8152_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
|
||||
extern int it8152_pci_setup(int nr, struct pci_sys_data *sys);
|
||||
|
||||
@ -11,12 +11,6 @@ static inline void ack_bad_irq(int irq)
|
||||
pr_crit("unexpected IRQ trap at vector %02x\n", irq);
|
||||
}
|
||||
|
||||
void set_irq_flags(unsigned int irq, unsigned int flags);
|
||||
|
||||
#define IRQF_VALID (1 << 0)
|
||||
#define IRQF_PROBE (1 << 1)
|
||||
#define IRQF_NOAUTOEN (1 << 2)
|
||||
|
||||
#define ARCH_IRQ_INIT_FLAGS (IRQ_NOREQUEST | IRQ_NOPROBE)
|
||||
|
||||
#endif
|
||||
|
||||
@ -29,21 +29,18 @@
|
||||
|
||||
#define __KVM_HAVE_ARCH_INTC_INITIALIZED
|
||||
|
||||
#if defined(CONFIG_KVM_ARM_MAX_VCPUS)
|
||||
#define KVM_MAX_VCPUS CONFIG_KVM_ARM_MAX_VCPUS
|
||||
#else
|
||||
#define KVM_MAX_VCPUS 0
|
||||
#endif
|
||||
|
||||
#define KVM_USER_MEM_SLOTS 32
|
||||
#define KVM_PRIVATE_MEM_SLOTS 4
|
||||
#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
|
||||
#define KVM_HAVE_ONE_REG
|
||||
#define KVM_HALT_POLL_NS_DEFAULT 500000
|
||||
|
||||
#define KVM_VCPU_MAX_FEATURES 2
|
||||
|
||||
#include <kvm/arm_vgic.h>
|
||||
|
||||
#define KVM_MAX_VCPUS VGIC_V2_MAX_CPUS
|
||||
|
||||
u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode);
|
||||
int __attribute_const__ kvm_target_cpu(void);
|
||||
int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
|
||||
@ -148,6 +145,7 @@ struct kvm_vm_stat {
|
||||
|
||||
struct kvm_vcpu_stat {
|
||||
u32 halt_successful_poll;
|
||||
u32 halt_attempted_poll;
|
||||
u32 halt_wakeup;
|
||||
};
|
||||
|
||||
|
||||
@ -23,10 +23,10 @@ extern int show_fiq_list(struct seq_file *, int);
|
||||
/*
|
||||
* This is for easy migration, but should be changed in the source
|
||||
*/
|
||||
#define do_bad_IRQ(irq,desc) \
|
||||
#define do_bad_IRQ(desc) \
|
||||
do { \
|
||||
raw_spin_lock(&desc->lock); \
|
||||
handle_bad_irq(irq, desc); \
|
||||
handle_bad_irq(desc); \
|
||||
raw_spin_unlock(&desc->lock); \
|
||||
} while(0)
|
||||
|
||||
|
||||
@ -25,7 +25,6 @@
|
||||
struct task_struct;
|
||||
|
||||
#include <asm/types.h>
|
||||
#include <asm/domain.h>
|
||||
|
||||
typedef unsigned long mm_segment_t;
|
||||
|
||||
|
||||
@ -79,26 +79,6 @@ asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
|
||||
handle_IRQ(irq, regs);
|
||||
}
|
||||
|
||||
void set_irq_flags(unsigned int irq, unsigned int iflags)
|
||||
{
|
||||
unsigned long clr = 0, set = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
|
||||
|
||||
if (irq >= nr_irqs) {
|
||||
pr_err("Trying to set irq flags for IRQ%d\n", irq);
|
||||
return;
|
||||
}
|
||||
|
||||
if (iflags & IRQF_VALID)
|
||||
clr |= IRQ_NOREQUEST;
|
||||
if (iflags & IRQF_PROBE)
|
||||
clr |= IRQ_NOPROBE;
|
||||
if (!(iflags & IRQF_NOAUTOEN))
|
||||
clr |= IRQ_NOAUTOEN;
|
||||
/* Order is clear bits in "clr" then set bits in "set" */
|
||||
irq_modify_status(irq, clr, set & ~clr);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(set_irq_flags);
|
||||
|
||||
void __init init_IRQ(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
@ -259,15 +259,17 @@ int kgdb_arch_set_breakpoint(struct kgdb_bkpt *bpt)
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
patch_text((void *)bpt->bpt_addr,
|
||||
*(unsigned int *)arch_kgdb_ops.gdb_bpt_instr);
|
||||
/* Machine is already stopped, so we can use __patch_text() directly */
|
||||
__patch_text((void *)bpt->bpt_addr,
|
||||
*(unsigned int *)arch_kgdb_ops.gdb_bpt_instr);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
int kgdb_arch_remove_breakpoint(struct kgdb_bkpt *bpt)
|
||||
{
|
||||
patch_text((void *)bpt->bpt_addr, *(unsigned int *)bpt->saved_instr);
|
||||
/* Machine is already stopped, so we can use __patch_text() directly */
|
||||
__patch_text((void *)bpt->bpt_addr, *(unsigned int *)bpt->saved_instr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -226,6 +226,7 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
|
||||
|
||||
memset(&thread->cpu_context, 0, sizeof(struct cpu_context_save));
|
||||
|
||||
#ifdef CONFIG_CPU_USE_DOMAINS
|
||||
/*
|
||||
* Copy the initial value of the domain access control register
|
||||
* from the current thread: thread->addr_limit will have been
|
||||
@ -233,6 +234,7 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
|
||||
* kernel/fork.c
|
||||
*/
|
||||
thread->cpu_domain = get_domain();
|
||||
#endif
|
||||
|
||||
if (likely(!(p->flags & PF_KTHREAD))) {
|
||||
*childregs = *current_pt_regs();
|
||||
|
||||
@ -343,15 +343,18 @@ setup_return(struct pt_regs *regs, struct ksignal *ksig,
|
||||
*/
|
||||
thumb = handler & 1;
|
||||
|
||||
#if __LINUX_ARM_ARCH__ >= 7
|
||||
/*
|
||||
* Clear the If-Then Thumb-2 execution state
|
||||
* ARM spec requires this to be all 000s in ARM mode
|
||||
* Snapdragon S4/Krait misbehaves on a Thumb=>ARM
|
||||
* signal transition without this.
|
||||
* Clear the If-Then Thumb-2 execution state. ARM spec
|
||||
* requires this to be all 000s in ARM mode. Snapdragon
|
||||
* S4/Krait misbehaves on a Thumb=>ARM signal transition
|
||||
* without this.
|
||||
*
|
||||
* We must do this whenever we are running on a Thumb-2
|
||||
* capable CPU, which includes ARMv6T2. However, we elect
|
||||
* to always do this to simplify the code; this field is
|
||||
* marked UNK/SBZP for older architectures.
|
||||
*/
|
||||
cpsr &= ~PSR_IT_MASK;
|
||||
#endif
|
||||
|
||||
if (thumb) {
|
||||
cpsr |= PSR_T_BIT;
|
||||
|
||||
@ -45,15 +45,4 @@ config KVM_ARM_HOST
|
||||
---help---
|
||||
Provides host support for ARM processors.
|
||||
|
||||
config KVM_ARM_MAX_VCPUS
|
||||
int "Number maximum supported virtual CPUs per VM"
|
||||
depends on KVM_ARM_HOST
|
||||
default 4
|
||||
help
|
||||
Static number of max supported virtual CPUs per VM.
|
||||
|
||||
If you choose a high number, the vcpu structures will be quite
|
||||
large, so only choose a reasonable number that you expect to
|
||||
actually use.
|
||||
|
||||
endif # VIRTUALIZATION
|
||||
|
||||
@ -446,7 +446,7 @@ static int kvm_vcpu_first_run_init(struct kvm_vcpu *vcpu)
|
||||
* Map the VGIC hardware resources before running a vcpu the first
|
||||
* time on this VM.
|
||||
*/
|
||||
if (unlikely(!vgic_ready(kvm))) {
|
||||
if (unlikely(irqchip_in_kernel(kvm) && !vgic_ready(kvm))) {
|
||||
ret = kvm_vgic_map_resources(kvm);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@ -515,8 +515,7 @@ ARM_BE8(rev r6, r6 )
|
||||
|
||||
mrc p15, 0, r2, c14, c3, 1 @ CNTV_CTL
|
||||
str r2, [vcpu, #VCPU_TIMER_CNTV_CTL]
|
||||
bic r2, #1 @ Clear ENABLE
|
||||
mcr p15, 0, r2, c14, c3, 1 @ CNTV_CTL
|
||||
|
||||
isb
|
||||
|
||||
mrrc p15, 3, rr_lo_hi(r2, r3), c14 @ CNTV_CVAL
|
||||
@ -529,6 +528,9 @@ ARM_BE8(rev r6, r6 )
|
||||
mcrr p15, 4, r2, r2, c14 @ CNTVOFF
|
||||
|
||||
1:
|
||||
mov r2, #0 @ Clear ENABLE
|
||||
mcr p15, 0, r2, c14, c3, 1 @ CNTV_CTL
|
||||
|
||||
@ Allow physical timer/counter access for the host
|
||||
mrc p15, 4, r2, c14, c1, 0 @ CNTHCTL
|
||||
orr r2, r2, #(CNTHCTL_PL1PCEN | CNTHCTL_PL1PCTEN)
|
||||
|
||||
@ -1792,8 +1792,10 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm,
|
||||
if (vma->vm_flags & VM_PFNMAP) {
|
||||
gpa_t gpa = mem->guest_phys_addr +
|
||||
(vm_start - mem->userspace_addr);
|
||||
phys_addr_t pa = (vma->vm_pgoff << PAGE_SHIFT) +
|
||||
vm_start - vma->vm_start;
|
||||
phys_addr_t pa;
|
||||
|
||||
pa = (phys_addr_t)vma->vm_pgoff << PAGE_SHIFT;
|
||||
pa += vm_start - vma->vm_start;
|
||||
|
||||
/* IO region dirty page logging not allowed */
|
||||
if (memslot->flags & KVM_MEM_LOG_DIRTY_PAGES)
|
||||
|
||||
@ -126,7 +126,7 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu)
|
||||
|
||||
static unsigned long kvm_psci_vcpu_affinity_info(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
int i;
|
||||
int i, matching_cpus = 0;
|
||||
unsigned long mpidr;
|
||||
unsigned long target_affinity;
|
||||
unsigned long target_affinity_mask;
|
||||
@ -151,12 +151,16 @@ static unsigned long kvm_psci_vcpu_affinity_info(struct kvm_vcpu *vcpu)
|
||||
*/
|
||||
kvm_for_each_vcpu(i, tmp, kvm) {
|
||||
mpidr = kvm_vcpu_get_mpidr_aff(tmp);
|
||||
if (((mpidr & target_affinity_mask) == target_affinity) &&
|
||||
!tmp->arch.pause) {
|
||||
return PSCI_0_2_AFFINITY_LEVEL_ON;
|
||||
if ((mpidr & target_affinity_mask) == target_affinity) {
|
||||
matching_cpus++;
|
||||
if (!tmp->arch.pause)
|
||||
return PSCI_0_2_AFFINITY_LEVEL_ON;
|
||||
}
|
||||
}
|
||||
|
||||
if (!matching_cpus)
|
||||
return PSCI_RET_INVALID_PARAMS;
|
||||
|
||||
return PSCI_0_2_AFFINITY_LEVEL_OFF;
|
||||
}
|
||||
|
||||
|
||||
@ -69,14 +69,14 @@ static struct irq_chip pmu_irq_chip = {
|
||||
.irq_ack = pmu_irq_ack,
|
||||
};
|
||||
|
||||
static void pmu_irq_handler(unsigned int __irq, struct irq_desc *desc)
|
||||
static void pmu_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
unsigned int irq = irq_desc_get_irq(desc);
|
||||
unsigned long cause = readl(PMU_INTERRUPT_CAUSE);
|
||||
unsigned int irq;
|
||||
|
||||
cause &= readl(PMU_INTERRUPT_MASK);
|
||||
if (cause == 0) {
|
||||
do_bad_IRQ(irq, desc);
|
||||
do_bad_IRQ(desc);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
@ -87,13 +87,12 @@ static struct irq_chip isa_hi_chip = {
|
||||
.irq_unmask = isa_unmask_pic_hi_irq,
|
||||
};
|
||||
|
||||
static void
|
||||
isa_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
static void isa_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
unsigned int isa_irq = *(unsigned char *)PCIIACK_BASE;
|
||||
|
||||
if (isa_irq < _ISA_IRQ(0) || isa_irq >= _ISA_IRQ(16)) {
|
||||
do_bad_IRQ(isa_irq, desc);
|
||||
do_bad_IRQ(desc);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
@ -126,7 +126,7 @@ static int gpio_set_irq_type(struct irq_data *d, unsigned int type)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
static void gpio_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
unsigned int port = (unsigned int)irq_desc_get_handler_data(desc);
|
||||
unsigned int gpio_irq_no, irq_stat;
|
||||
|
||||
@ -85,7 +85,7 @@ static struct platform_device smsc_lan9217_device = {
|
||||
.resource = smsc911x_resources,
|
||||
};
|
||||
|
||||
static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
|
||||
static void mxc_expio_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
u32 imr_val;
|
||||
u32 int_valid;
|
||||
|
||||
@ -154,7 +154,7 @@ static inline void mxc_init_imx_uart(void)
|
||||
imx31_add_imx_uart0(&uart_pdata);
|
||||
}
|
||||
|
||||
static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
|
||||
static void mx31ads_expio_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
u32 imr_val;
|
||||
u32 int_valid;
|
||||
|
||||
@ -91,7 +91,7 @@ static void (*write_imipr[])(u32) = {
|
||||
write_imipr_3,
|
||||
};
|
||||
|
||||
static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc)
|
||||
static void iop13xx_msi_handler(struct irq_desc *desc)
|
||||
{
|
||||
int i, j;
|
||||
unsigned long status;
|
||||
|
||||
@ -370,7 +370,7 @@ static struct irq_chip lpc32xx_irq_chip = {
|
||||
.irq_set_wake = lpc32xx_irq_wake
|
||||
};
|
||||
|
||||
static void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc)
|
||||
static void lpc32xx_sic1_handler(struct irq_desc *desc)
|
||||
{
|
||||
unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC1_BASE));
|
||||
|
||||
@ -383,7 +383,7 @@ static void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc)
|
||||
}
|
||||
}
|
||||
|
||||
static void lpc32xx_sic2_handler(unsigned int irq, struct irq_desc *desc)
|
||||
static void lpc32xx_sic2_handler(struct irq_desc *desc)
|
||||
{
|
||||
unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC2_BASE));
|
||||
|
||||
|
||||
@ -69,8 +69,7 @@ static struct platform_device *devices[] __initdata = {
|
||||
#define DEBUG_IRQ(fmt...) while (0) {}
|
||||
#endif
|
||||
|
||||
static void
|
||||
netx_hif_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
|
||||
static void netx_hif_demux_handler(struct irq_desc *desc)
|
||||
{
|
||||
unsigned int irq = NETX_IRQ_HIF_CHAINED(0);
|
||||
unsigned int stat;
|
||||
|
||||
@ -87,7 +87,7 @@ static void fpga_mask_ack_irq(struct irq_data *d)
|
||||
fpga_ack_irq(d);
|
||||
}
|
||||
|
||||
static void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
|
||||
static void innovator_fpga_IRQ_demux(struct irq_desc *desc)
|
||||
{
|
||||
u32 stat;
|
||||
int fpga_irq;
|
||||
|
||||
@ -102,7 +102,7 @@ static void omap_prcm_events_filter_priority(unsigned long *events,
|
||||
* dispatched accordingly. Clearing of the wakeup events should be
|
||||
* done by the SoC specific individual handlers.
|
||||
*/
|
||||
static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
static void omap_prcm_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
|
||||
unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
|
||||
|
||||
@ -496,7 +496,7 @@ static struct irq_chip balloon3_irq_chip = {
|
||||
.irq_unmask = balloon3_unmask_irq,
|
||||
};
|
||||
|
||||
static void balloon3_irq_handler(unsigned int __irq, struct irq_desc *desc)
|
||||
static void balloon3_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
unsigned long pending = __raw_readl(BALLOON3_INT_CONTROL_REG) &
|
||||
balloon3_irq_enabled;
|
||||
|
||||
@ -29,13 +29,12 @@
|
||||
void __iomem *it8152_base_address;
|
||||
static int cmx2xx_it8152_irq_gpio;
|
||||
|
||||
static void cmx2xx_it8152_irq_demux(unsigned int __irq, struct irq_desc *desc)
|
||||
static void cmx2xx_it8152_irq_demux(struct irq_desc *desc)
|
||||
{
|
||||
unsigned int irq = irq_desc_get_irq(desc);
|
||||
/* clear our parent irq */
|
||||
desc->irq_data.chip->irq_ack(&desc->irq_data);
|
||||
|
||||
it8152_irq_demux(irq, desc);
|
||||
it8152_irq_demux(desc);
|
||||
}
|
||||
|
||||
void __cmx2xx_pci_init_irq(int irq_gpio)
|
||||
|
||||
@ -120,7 +120,7 @@ static struct irq_chip lpd270_irq_chip = {
|
||||
.irq_unmask = lpd270_unmask_irq,
|
||||
};
|
||||
|
||||
static void lpd270_irq_handler(unsigned int __irq, struct irq_desc *desc)
|
||||
static void lpd270_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
unsigned int irq;
|
||||
unsigned long pending;
|
||||
|
||||
@ -284,7 +284,7 @@ static struct irq_chip pcm990_irq_chip = {
|
||||
.irq_unmask = pcm990_unmask_irq,
|
||||
};
|
||||
|
||||
static void pcm990_irq_handler(unsigned int __irq, struct irq_desc *desc)
|
||||
static void pcm990_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
unsigned int irq;
|
||||
unsigned long pending;
|
||||
|
||||
@ -276,7 +276,7 @@ static inline unsigned long viper_irq_pending(void)
|
||||
viper_irq_enabled_mask;
|
||||
}
|
||||
|
||||
static void viper_irq_handler(unsigned int __irq, struct irq_desc *desc)
|
||||
static void viper_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
unsigned int irq;
|
||||
unsigned long pending;
|
||||
|
||||
@ -105,7 +105,7 @@ static inline unsigned long zeus_irq_pending(void)
|
||||
return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask;
|
||||
}
|
||||
|
||||
static void zeus_irq_handler(unsigned int __irq, struct irq_desc *desc)
|
||||
static void zeus_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
unsigned int irq;
|
||||
unsigned long pending;
|
||||
|
||||
@ -551,8 +551,7 @@ static void ecard_check_lockup(struct irq_desc *desc)
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
ecard_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
static void ecard_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
ecard_t *ec;
|
||||
int called = 0;
|
||||
|
||||
@ -100,9 +100,7 @@ static struct irq_chip bast_pc104_chip = {
|
||||
.irq_ack = bast_pc104_maskack
|
||||
};
|
||||
|
||||
static void
|
||||
bast_irq_pc104_demux(unsigned int irq,
|
||||
struct irq_desc *desc)
|
||||
static void bast_irq_pc104_demux(struct irq_desc *desc)
|
||||
{
|
||||
unsigned int stat;
|
||||
unsigned int irqno;
|
||||
|
||||
@ -388,22 +388,22 @@ static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
|
||||
}
|
||||
}
|
||||
|
||||
static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
|
||||
static void s3c_irq_demux_eint0_3(struct irq_desc *desc)
|
||||
{
|
||||
s3c_irq_demux_eint(0, 3);
|
||||
}
|
||||
|
||||
static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
|
||||
static void s3c_irq_demux_eint4_11(struct irq_desc *desc)
|
||||
{
|
||||
s3c_irq_demux_eint(4, 11);
|
||||
}
|
||||
|
||||
static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
|
||||
static void s3c_irq_demux_eint12_19(struct irq_desc *desc)
|
||||
{
|
||||
s3c_irq_demux_eint(12, 19);
|
||||
}
|
||||
|
||||
static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
|
||||
static void s3c_irq_demux_eint20_27(struct irq_desc *desc)
|
||||
{
|
||||
s3c_irq_demux_eint(20, 27);
|
||||
}
|
||||
|
||||
@ -166,7 +166,7 @@ static struct sa1100_port_fns neponset_port_fns = {
|
||||
* ensure that the IRQ signal is deasserted before returning. This
|
||||
* is rather unfortunate.
|
||||
*/
|
||||
static void neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
static void neponset_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
struct neponset_drvdata *d = irq_desc_get_handler_data(desc);
|
||||
unsigned int irr;
|
||||
|
||||
@ -1249,7 +1249,7 @@ __iommu_create_mapping(struct device *dev, struct page **pages, size_t size)
|
||||
struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
|
||||
unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
|
||||
dma_addr_t dma_addr, iova;
|
||||
int i, ret = DMA_ERROR_CODE;
|
||||
int i;
|
||||
|
||||
dma_addr = __alloc_iova(mapping, size);
|
||||
if (dma_addr == DMA_ERROR_CODE)
|
||||
@ -1257,6 +1257,8 @@ __iommu_create_mapping(struct device *dev, struct page **pages, size_t size)
|
||||
|
||||
iova = dma_addr;
|
||||
for (i = 0; i < count; ) {
|
||||
int ret;
|
||||
|
||||
unsigned int next_pfn = page_to_pfn(pages[i]) + 1;
|
||||
phys_addr_t phys = page_to_phys(pages[i]);
|
||||
unsigned int len, j;
|
||||
|
||||
@ -95,9 +95,10 @@ emulate:
|
||||
reteq r4 @ no, return failure
|
||||
|
||||
next:
|
||||
uaccess_enable r3
|
||||
.Lx1: ldrt r6, [r5], #4 @ get the next instruction and
|
||||
@ increment PC
|
||||
|
||||
uaccess_disable r3
|
||||
and r2, r6, #0x0F000000 @ test for FP insns
|
||||
teq r2, #0x0C000000
|
||||
teqne r2, #0x0D000000
|
||||
|
||||
@ -407,7 +407,7 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void gpio_irq_handler(unsigned __irq, struct irq_desc *desc)
|
||||
static void gpio_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
struct orion_gpio_chip *ochip = irq_desc_get_handler_data(desc);
|
||||
u32 cause, type;
|
||||
|
||||
@ -98,8 +98,23 @@ ENTRY(privcmd_call)
|
||||
mov r1, r2
|
||||
mov r2, r3
|
||||
ldr r3, [sp, #8]
|
||||
/*
|
||||
* Privcmd calls are issued by the userspace. We need to allow the
|
||||
* kernel to access the userspace memory before issuing the hypercall.
|
||||
*/
|
||||
uaccess_enable r4
|
||||
|
||||
/* r4 is loaded now as we use it as scratch register before */
|
||||
ldr r4, [sp, #4]
|
||||
__HVC(XEN_IMM)
|
||||
|
||||
/*
|
||||
* Disable userspace access from kernel. This is fine to do it
|
||||
* unconditionally as no set_fs(KERNEL_DS)/set_fs(get_ds()) is
|
||||
* called before.
|
||||
*/
|
||||
uaccess_disable r4
|
||||
|
||||
ldm sp!, {r4}
|
||||
ret lr
|
||||
ENDPROC(privcmd_call);
|
||||
|
||||
@ -32,6 +32,7 @@ config ARM64
|
||||
select GENERIC_CLOCKEVENTS_BROADCAST
|
||||
select GENERIC_CPU_AUTOPROBE
|
||||
select GENERIC_EARLY_IOREMAP
|
||||
select GENERIC_IDLE_POLL_SETUP
|
||||
select GENERIC_IRQ_PROBE
|
||||
select GENERIC_IRQ_SHOW
|
||||
select GENERIC_IRQ_SHOW_LEVEL
|
||||
@ -331,6 +332,22 @@ config ARM64_ERRATUM_845719
|
||||
|
||||
If unsure, say Y.
|
||||
|
||||
config ARM64_ERRATUM_843419
|
||||
bool "Cortex-A53: 843419: A load or store might access an incorrect address"
|
||||
depends on MODULES
|
||||
default y
|
||||
help
|
||||
This option builds kernel modules using the large memory model in
|
||||
order to avoid the use of the ADRP instruction, which can cause
|
||||
a subsequent memory access to use an incorrect address on Cortex-A53
|
||||
parts up to r0p4.
|
||||
|
||||
Note that the kernel itself must be linked with a version of ld
|
||||
which fixes potentially affected ADRP instructions through the
|
||||
use of veneers.
|
||||
|
||||
If unsure, say Y.
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
|
||||
@ -41,6 +41,10 @@ endif
|
||||
|
||||
CHECKFLAGS += -D__aarch64__
|
||||
|
||||
ifeq ($(CONFIG_ARM64_ERRATUM_843419), y)
|
||||
CFLAGS_MODULE += -mcmodel=large
|
||||
endif
|
||||
|
||||
# Default value
|
||||
head-y := arch/arm64/kernel/head.o
|
||||
|
||||
|
||||
@ -81,7 +81,7 @@
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "arm,psci";
|
||||
entry-method = "psci";
|
||||
|
||||
CPU_SLEEP_0: cpu-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
|
||||
@ -106,7 +106,7 @@
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "arm,psci";
|
||||
entry-method = "psci";
|
||||
|
||||
cpu_sleep: cpu-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
|
||||
@ -43,9 +43,4 @@ static inline void ack_bad_irq(unsigned int irq)
|
||||
irq_err_count++;
|
||||
}
|
||||
|
||||
/*
|
||||
* No arch-specific IRQ flags.
|
||||
*/
|
||||
#define set_irq_flags(irq, flags)
|
||||
|
||||
#endif /* __ASM_HARDIRQ_H */
|
||||
|
||||
@ -95,6 +95,7 @@
|
||||
SCTLR_EL2_SA | SCTLR_EL2_I)
|
||||
|
||||
/* TCR_EL2 Registers bits */
|
||||
#define TCR_EL2_RES1 ((1 << 31) | (1 << 23))
|
||||
#define TCR_EL2_TBI (1 << 20)
|
||||
#define TCR_EL2_PS (7 << 16)
|
||||
#define TCR_EL2_PS_40B (2 << 16)
|
||||
@ -106,9 +107,10 @@
|
||||
#define TCR_EL2_MASK (TCR_EL2_TG0 | TCR_EL2_SH0 | \
|
||||
TCR_EL2_ORGN0 | TCR_EL2_IRGN0 | TCR_EL2_T0SZ)
|
||||
|
||||
#define TCR_EL2_FLAGS (TCR_EL2_PS_40B)
|
||||
#define TCR_EL2_FLAGS (TCR_EL2_RES1 | TCR_EL2_PS_40B)
|
||||
|
||||
/* VTCR_EL2 Registers bits */
|
||||
#define VTCR_EL2_RES1 (1 << 31)
|
||||
#define VTCR_EL2_PS_MASK (7 << 16)
|
||||
#define VTCR_EL2_TG0_MASK (1 << 14)
|
||||
#define VTCR_EL2_TG0_4K (0 << 14)
|
||||
@ -147,7 +149,8 @@
|
||||
*/
|
||||
#define VTCR_EL2_FLAGS (VTCR_EL2_TG0_64K | VTCR_EL2_SH0_INNER | \
|
||||
VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \
|
||||
VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B)
|
||||
VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B | \
|
||||
VTCR_EL2_RES1)
|
||||
#define VTTBR_X (38 - VTCR_EL2_T0SZ_40B)
|
||||
#else
|
||||
/*
|
||||
@ -158,7 +161,8 @@
|
||||
*/
|
||||
#define VTCR_EL2_FLAGS (VTCR_EL2_TG0_4K | VTCR_EL2_SH0_INNER | \
|
||||
VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \
|
||||
VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B)
|
||||
VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B | \
|
||||
VTCR_EL2_RES1)
|
||||
#define VTTBR_X (37 - VTCR_EL2_T0SZ_40B)
|
||||
#endif
|
||||
|
||||
@ -168,7 +172,6 @@
|
||||
#define VTTBR_VMID_MASK (UL(0xFF) << VTTBR_VMID_SHIFT)
|
||||
|
||||
/* Hyp System Trap Register */
|
||||
#define HSTR_EL2_TTEE (1 << 16)
|
||||
#define HSTR_EL2_T(x) (1 << x)
|
||||
|
||||
/* Hyp Coproccessor Trap Register Shifts */
|
||||
|
||||
@ -53,9 +53,7 @@
|
||||
#define IFSR32_EL2 25 /* Instruction Fault Status Register */
|
||||
#define FPEXC32_EL2 26 /* Floating-Point Exception Control Register */
|
||||
#define DBGVCR32_EL2 27 /* Debug Vector Catch Register */
|
||||
#define TEECR32_EL1 28 /* ThumbEE Configuration Register */
|
||||
#define TEEHBR32_EL1 29 /* ThumbEE Handler Base Register */
|
||||
#define NR_SYS_REGS 30
|
||||
#define NR_SYS_REGS 28
|
||||
|
||||
/* 32bit mapping */
|
||||
#define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
|
||||
|
||||
@ -30,19 +30,16 @@
|
||||
|
||||
#define __KVM_HAVE_ARCH_INTC_INITIALIZED
|
||||
|
||||
#if defined(CONFIG_KVM_ARM_MAX_VCPUS)
|
||||
#define KVM_MAX_VCPUS CONFIG_KVM_ARM_MAX_VCPUS
|
||||
#else
|
||||
#define KVM_MAX_VCPUS 0
|
||||
#endif
|
||||
|
||||
#define KVM_USER_MEM_SLOTS 32
|
||||
#define KVM_PRIVATE_MEM_SLOTS 4
|
||||
#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
|
||||
#define KVM_HALT_POLL_NS_DEFAULT 500000
|
||||
|
||||
#include <kvm/arm_vgic.h>
|
||||
#include <kvm/arm_arch_timer.h>
|
||||
|
||||
#define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
|
||||
|
||||
#define KVM_VCPU_MAX_FEATURES 3
|
||||
|
||||
int __attribute_const__ kvm_target_cpu(void);
|
||||
@ -195,6 +192,7 @@ struct kvm_vm_stat {
|
||||
|
||||
struct kvm_vcpu_stat {
|
||||
u32 halt_successful_poll;
|
||||
u32 halt_attempted_poll;
|
||||
u32 halt_wakeup;
|
||||
};
|
||||
|
||||
|
||||
@ -26,13 +26,9 @@
|
||||
* Software defined PTE bits definition.
|
||||
*/
|
||||
#define PTE_VALID (_AT(pteval_t, 1) << 0)
|
||||
#define PTE_WRITE (PTE_DBM) /* same as DBM (51) */
|
||||
#define PTE_DIRTY (_AT(pteval_t, 1) << 55)
|
||||
#define PTE_SPECIAL (_AT(pteval_t, 1) << 56)
|
||||
#ifdef CONFIG_ARM64_HW_AFDBM
|
||||
#define PTE_WRITE (PTE_DBM) /* same as DBM */
|
||||
#else
|
||||
#define PTE_WRITE (_AT(pteval_t, 1) << 57)
|
||||
#endif
|
||||
#define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
|
||||
|
||||
/*
|
||||
@ -146,7 +142,7 @@ extern struct page *empty_zero_page;
|
||||
#define pte_exec(pte) (!(pte_val(pte) & PTE_UXN))
|
||||
|
||||
#ifdef CONFIG_ARM64_HW_AFDBM
|
||||
#define pte_hw_dirty(pte) (!(pte_val(pte) & PTE_RDONLY))
|
||||
#define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
|
||||
#else
|
||||
#define pte_hw_dirty(pte) (0)
|
||||
#endif
|
||||
@ -238,7 +234,7 @@ extern void __sync_icache_dcache(pte_t pteval, unsigned long addr);
|
||||
* When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
|
||||
* the page fault mechanism. Checking the dirty status of a pte becomes:
|
||||
*
|
||||
* PTE_DIRTY || !PTE_RDONLY
|
||||
* PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
|
||||
*/
|
||||
static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
|
||||
pte_t *ptep, pte_t pte)
|
||||
@ -503,7 +499,7 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
|
||||
PTE_PROT_NONE | PTE_WRITE | PTE_TYPE_MASK;
|
||||
/* preserve the hardware dirty information */
|
||||
if (pte_hw_dirty(pte))
|
||||
newprot |= PTE_DIRTY;
|
||||
pte = pte_mkdirty(pte);
|
||||
pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
|
||||
return pte;
|
||||
}
|
||||
|
||||
@ -134,7 +134,7 @@ static int os_lock_notify(struct notifier_block *self,
|
||||
unsigned long action, void *data)
|
||||
{
|
||||
int cpu = (unsigned long)data;
|
||||
if (action == CPU_ONLINE)
|
||||
if ((action & ~CPU_TASKS_FROZEN) == CPU_ONLINE)
|
||||
smp_call_function_single(cpu, clear_os_lock, NULL, 1);
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
@ -523,6 +523,11 @@ CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems
|
||||
msr hstr_el2, xzr // Disable CP15 traps to EL2
|
||||
#endif
|
||||
|
||||
/* EL2 debug */
|
||||
mrs x0, pmcr_el0 // Disable debug access traps
|
||||
ubfx x0, x0, #11, #5 // to EL2 and allow access to
|
||||
msr mdcr_el2, x0 // all PMU counters from EL1
|
||||
|
||||
/* Stage-2 translation */
|
||||
msr vttbr_el2, xzr
|
||||
|
||||
|
||||
@ -872,7 +872,7 @@ static int hw_breakpoint_reset_notify(struct notifier_block *self,
|
||||
void *hcpu)
|
||||
{
|
||||
int cpu = (long)hcpu;
|
||||
if (action == CPU_ONLINE)
|
||||
if ((action & ~CPU_TASKS_FROZEN) == CPU_ONLINE)
|
||||
smp_call_function_single(cpu, hw_breakpoint_reset, NULL, 1);
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
@ -332,12 +332,14 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
|
||||
ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21,
|
||||
AARCH64_INSN_IMM_ADR);
|
||||
break;
|
||||
#ifndef CONFIG_ARM64_ERRATUM_843419
|
||||
case R_AARCH64_ADR_PREL_PG_HI21_NC:
|
||||
overflow_check = false;
|
||||
case R_AARCH64_ADR_PREL_PG_HI21:
|
||||
ovf = reloc_insn_imm(RELOC_OP_PAGE, loc, val, 12, 21,
|
||||
AARCH64_INSN_IMM_ADR);
|
||||
break;
|
||||
#endif
|
||||
case R_AARCH64_ADD_ABS_LO12_NC:
|
||||
case R_AARCH64_LDST8_ABS_LO12_NC:
|
||||
overflow_check = false;
|
||||
|
||||
@ -212,14 +212,32 @@ int copy_siginfo_from_user32(siginfo_t *to, compat_siginfo_t __user *from)
|
||||
|
||||
/*
|
||||
* VFP save/restore code.
|
||||
*
|
||||
* We have to be careful with endianness, since the fpsimd context-switch
|
||||
* code operates on 128-bit (Q) register values whereas the compat ABI
|
||||
* uses an array of 64-bit (D) registers. Consequently, we need to swap
|
||||
* the two halves of each Q register when running on a big-endian CPU.
|
||||
*/
|
||||
union __fpsimd_vreg {
|
||||
__uint128_t raw;
|
||||
struct {
|
||||
#ifdef __AARCH64EB__
|
||||
u64 hi;
|
||||
u64 lo;
|
||||
#else
|
||||
u64 lo;
|
||||
u64 hi;
|
||||
#endif
|
||||
};
|
||||
};
|
||||
|
||||
static int compat_preserve_vfp_context(struct compat_vfp_sigframe __user *frame)
|
||||
{
|
||||
struct fpsimd_state *fpsimd = ¤t->thread.fpsimd_state;
|
||||
compat_ulong_t magic = VFP_MAGIC;
|
||||
compat_ulong_t size = VFP_STORAGE_SIZE;
|
||||
compat_ulong_t fpscr, fpexc;
|
||||
int err = 0;
|
||||
int i, err = 0;
|
||||
|
||||
/*
|
||||
* Save the hardware registers to the fpsimd_state structure.
|
||||
@ -235,10 +253,15 @@ static int compat_preserve_vfp_context(struct compat_vfp_sigframe __user *frame)
|
||||
/*
|
||||
* Now copy the FP registers. Since the registers are packed,
|
||||
* we can copy the prefix we want (V0-V15) as it is.
|
||||
* FIXME: Won't work if big endian.
|
||||
*/
|
||||
err |= __copy_to_user(&frame->ufp.fpregs, fpsimd->vregs,
|
||||
sizeof(frame->ufp.fpregs));
|
||||
for (i = 0; i < ARRAY_SIZE(frame->ufp.fpregs); i += 2) {
|
||||
union __fpsimd_vreg vreg = {
|
||||
.raw = fpsimd->vregs[i >> 1],
|
||||
};
|
||||
|
||||
__put_user_error(vreg.lo, &frame->ufp.fpregs[i], err);
|
||||
__put_user_error(vreg.hi, &frame->ufp.fpregs[i + 1], err);
|
||||
}
|
||||
|
||||
/* Create an AArch32 fpscr from the fpsr and the fpcr. */
|
||||
fpscr = (fpsimd->fpsr & VFP_FPSCR_STAT_MASK) |
|
||||
@ -263,7 +286,7 @@ static int compat_restore_vfp_context(struct compat_vfp_sigframe __user *frame)
|
||||
compat_ulong_t magic = VFP_MAGIC;
|
||||
compat_ulong_t size = VFP_STORAGE_SIZE;
|
||||
compat_ulong_t fpscr;
|
||||
int err = 0;
|
||||
int i, err = 0;
|
||||
|
||||
__get_user_error(magic, &frame->magic, err);
|
||||
__get_user_error(size, &frame->size, err);
|
||||
@ -273,12 +296,14 @@ static int compat_restore_vfp_context(struct compat_vfp_sigframe __user *frame)
|
||||
if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE)
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* Copy the FP registers into the start of the fpsimd_state.
|
||||
* FIXME: Won't work if big endian.
|
||||
*/
|
||||
err |= __copy_from_user(fpsimd.vregs, frame->ufp.fpregs,
|
||||
sizeof(frame->ufp.fpregs));
|
||||
/* Copy the FP registers into the start of the fpsimd_state. */
|
||||
for (i = 0; i < ARRAY_SIZE(frame->ufp.fpregs); i += 2) {
|
||||
union __fpsimd_vreg vreg;
|
||||
|
||||
__get_user_error(vreg.lo, &frame->ufp.fpregs[i], err);
|
||||
__get_user_error(vreg.hi, &frame->ufp.fpregs[i + 1], err);
|
||||
fpsimd.vregs[i >> 1] = vreg.raw;
|
||||
}
|
||||
|
||||
/* Extract the fpsr and the fpcr from the fpscr */
|
||||
__get_user_error(fpscr, &frame->ufp.fpscr, err);
|
||||
|
||||
@ -41,15 +41,4 @@ config KVM_ARM_HOST
|
||||
---help---
|
||||
Provides host support for ARM processors.
|
||||
|
||||
config KVM_ARM_MAX_VCPUS
|
||||
int "Number maximum supported virtual CPUs per VM"
|
||||
depends on KVM_ARM_HOST
|
||||
default 4
|
||||
help
|
||||
Static number of max supported virtual CPUs per VM.
|
||||
|
||||
If you choose a high number, the vcpu structures will be quite
|
||||
large, so only choose a reasonable number that you expect to
|
||||
actually use.
|
||||
|
||||
endif # VIRTUALIZATION
|
||||
|
||||
@ -433,20 +433,13 @@
|
||||
mrs x5, ifsr32_el2
|
||||
stp x4, x5, [x3]
|
||||
|
||||
skip_fpsimd_state x8, 3f
|
||||
skip_fpsimd_state x8, 2f
|
||||
mrs x6, fpexc32_el2
|
||||
str x6, [x3, #16]
|
||||
3:
|
||||
skip_debug_state x8, 2f
|
||||
2:
|
||||
skip_debug_state x8, 1f
|
||||
mrs x7, dbgvcr32_el2
|
||||
str x7, [x3, #24]
|
||||
2:
|
||||
skip_tee_state x8, 1f
|
||||
|
||||
add x3, x2, #CPU_SYSREG_OFFSET(TEECR32_EL1)
|
||||
mrs x4, teecr32_el1
|
||||
mrs x5, teehbr32_el1
|
||||
stp x4, x5, [x3]
|
||||
1:
|
||||
.endm
|
||||
|
||||
@ -466,16 +459,9 @@
|
||||
msr dacr32_el2, x4
|
||||
msr ifsr32_el2, x5
|
||||
|
||||
skip_debug_state x8, 2f
|
||||
skip_debug_state x8, 1f
|
||||
ldr x7, [x3, #24]
|
||||
msr dbgvcr32_el2, x7
|
||||
2:
|
||||
skip_tee_state x8, 1f
|
||||
|
||||
add x3, x2, #CPU_SYSREG_OFFSET(TEECR32_EL1)
|
||||
ldp x4, x5, [x3]
|
||||
msr teecr32_el1, x4
|
||||
msr teehbr32_el1, x5
|
||||
1:
|
||||
.endm
|
||||
|
||||
@ -570,8 +556,6 @@ alternative_endif
|
||||
mrs x3, cntv_ctl_el0
|
||||
and x3, x3, #3
|
||||
str w3, [x0, #VCPU_TIMER_CNTV_CTL]
|
||||
bic x3, x3, #1 // Clear Enable
|
||||
msr cntv_ctl_el0, x3
|
||||
|
||||
isb
|
||||
|
||||
@ -579,6 +563,9 @@ alternative_endif
|
||||
str x3, [x0, #VCPU_TIMER_CNTV_CVAL]
|
||||
|
||||
1:
|
||||
// Disable the virtual timer
|
||||
msr cntv_ctl_el0, xzr
|
||||
|
||||
// Allow physical timer/counter access for the host
|
||||
mrs x2, cnthctl_el2
|
||||
orr x2, x2, #3
|
||||
@ -753,6 +740,9 @@ ENTRY(__kvm_vcpu_run)
|
||||
// Guest context
|
||||
add x2, x0, #VCPU_CONTEXT
|
||||
|
||||
// We must restore the 32-bit state before the sysregs, thanks
|
||||
// to Cortex-A57 erratum #852523.
|
||||
restore_guest_32bit_state
|
||||
bl __restore_sysregs
|
||||
|
||||
skip_debug_state x3, 1f
|
||||
@ -760,7 +750,6 @@ ENTRY(__kvm_vcpu_run)
|
||||
kern_hyp_va x3
|
||||
bl __restore_debug
|
||||
1:
|
||||
restore_guest_32bit_state
|
||||
restore_guest_regs
|
||||
|
||||
// That's it, no more messing around.
|
||||
|
||||
@ -272,7 +272,7 @@ static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
|
||||
{
|
||||
__u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
|
||||
|
||||
if (copy_from_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
|
||||
if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
|
||||
return -EFAULT;
|
||||
return 0;
|
||||
}
|
||||
@ -314,7 +314,7 @@ static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
|
||||
{
|
||||
__u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
|
||||
|
||||
if (copy_from_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
|
||||
if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
|
||||
return -EFAULT;
|
||||
|
||||
return 0;
|
||||
@ -358,7 +358,7 @@ static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
|
||||
{
|
||||
__u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
|
||||
|
||||
if (copy_from_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
|
||||
if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
|
||||
return -EFAULT;
|
||||
return 0;
|
||||
}
|
||||
@ -400,7 +400,7 @@ static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
|
||||
{
|
||||
__u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
|
||||
|
||||
if (copy_from_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
|
||||
if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
|
||||
return -EFAULT;
|
||||
return 0;
|
||||
}
|
||||
@ -539,13 +539,6 @@ static const struct sys_reg_desc sys_reg_descs[] = {
|
||||
{ Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b110),
|
||||
trap_dbgauthstatus_el1 },
|
||||
|
||||
/* TEECR32_EL1 */
|
||||
{ Op0(0b10), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
|
||||
NULL, reset_val, TEECR32_EL1, 0 },
|
||||
/* TEEHBR32_EL1 */
|
||||
{ Op0(0b10), Op1(0b010), CRn(0b0001), CRm(0b0000), Op2(0b000),
|
||||
NULL, reset_val, TEEHBR32_EL1, 0 },
|
||||
|
||||
/* MDCCSR_EL1 */
|
||||
{ Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0001), Op2(0b000),
|
||||
trap_raz_wi },
|
||||
|
||||
@ -100,7 +100,7 @@ static void *__dma_alloc_coherent(struct device *dev, size_t size,
|
||||
if (IS_ENABLED(CONFIG_ZONE_DMA) &&
|
||||
dev->coherent_dma_mask <= DMA_BIT_MASK(32))
|
||||
flags |= GFP_DMA;
|
||||
if (IS_ENABLED(CONFIG_DMA_CMA) && (flags & __GFP_WAIT)) {
|
||||
if (dev_get_cma_area(dev) && (flags & __GFP_WAIT)) {
|
||||
struct page *page;
|
||||
void *addr;
|
||||
|
||||
|
||||
@ -144,7 +144,7 @@ static struct irq_chip eic_chip = {
|
||||
.irq_set_type = eic_set_irq_type,
|
||||
};
|
||||
|
||||
static void demux_eic_irq(unsigned int irq, struct irq_desc *desc)
|
||||
static void demux_eic_irq(struct irq_desc *desc)
|
||||
{
|
||||
struct eic *eic = irq_desc_get_handler_data(desc);
|
||||
unsigned long status, pending;
|
||||
|
||||
@ -281,7 +281,7 @@ static struct irq_chip gpio_irqchip = {
|
||||
.irq_set_type = gpio_irq_type,
|
||||
};
|
||||
|
||||
static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
|
||||
static void gpio_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
struct pio_device *pio = irq_desc_get_chip_data(desc);
|
||||
unsigned gpio_irq;
|
||||
|
||||
@ -60,7 +60,7 @@ extern void bfin_internal_mask_irq(unsigned int irq);
|
||||
extern void bfin_internal_unmask_irq(unsigned int irq);
|
||||
|
||||
struct irq_desc;
|
||||
extern void bfin_demux_mac_status_irq(unsigned int, struct irq_desc *);
|
||||
extern void bfin_demux_gpio_irq(unsigned int, struct irq_desc *);
|
||||
extern void bfin_demux_mac_status_irq(struct irq_desc *);
|
||||
extern void bfin_demux_gpio_irq(struct irq_desc *);
|
||||
|
||||
#endif
|
||||
|
||||
@ -107,7 +107,7 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
|
||||
* than crashing, do something sensible.
|
||||
*/
|
||||
if (irq >= NR_IRQS)
|
||||
handle_bad_irq(irq, &bad_irq_desc);
|
||||
handle_bad_irq(&bad_irq_desc);
|
||||
else
|
||||
generic_handle_irq(irq);
|
||||
|
||||
|
||||
@ -89,8 +89,7 @@ static struct irq_chip bf537_generic_error_irqchip = {
|
||||
.irq_unmask = bf537_generic_error_unmask_irq,
|
||||
};
|
||||
|
||||
static void bf537_demux_error_irq(unsigned int int_err_irq,
|
||||
struct irq_desc *inta_desc)
|
||||
static void bf537_demux_error_irq(struct irq_desc *inta_desc)
|
||||
{
|
||||
int irq = 0;
|
||||
|
||||
@ -182,15 +181,12 @@ static struct irq_chip bf537_mac_rx_irqchip = {
|
||||
.irq_unmask = bf537_mac_rx_unmask_irq,
|
||||
};
|
||||
|
||||
static void bf537_demux_mac_rx_irq(unsigned int __int_irq,
|
||||
struct irq_desc *desc)
|
||||
static void bf537_demux_mac_rx_irq(struct irq_desc *desc)
|
||||
{
|
||||
unsigned int int_irq = irq_desc_get_irq(desc);
|
||||
|
||||
if (bfin_read_DMA1_IRQ_STATUS() & (DMA_DONE | DMA_ERR))
|
||||
bfin_handle_irq(IRQ_MAC_RX);
|
||||
else
|
||||
bfin_demux_gpio_irq(int_irq, desc);
|
||||
bfin_demux_gpio_irq(desc);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@ -656,8 +656,7 @@ static struct irq_chip bfin_mac_status_irqchip = {
|
||||
.irq_set_wake = bfin_mac_status_set_wake,
|
||||
};
|
||||
|
||||
void bfin_demux_mac_status_irq(unsigned int int_err_irq,
|
||||
struct irq_desc *inta_desc)
|
||||
void bfin_demux_mac_status_irq(struct irq_desc *inta_desc)
|
||||
{
|
||||
int i, irq = 0;
|
||||
u32 status = bfin_read_EMAC_SYSTAT();
|
||||
@ -825,7 +824,7 @@ static void bfin_demux_gpio_block(unsigned int irq)
|
||||
}
|
||||
}
|
||||
|
||||
void bfin_demux_gpio_irq(unsigned int __inta_irq, struct irq_desc *desc)
|
||||
void bfin_demux_gpio_irq(struct irq_desc *desc)
|
||||
{
|
||||
unsigned int inta_irq = irq_desc_get_irq(desc);
|
||||
unsigned int irq;
|
||||
|
||||
@ -93,7 +93,7 @@ static struct irq_chip megamod_chip = {
|
||||
.irq_unmask = unmask_megamod,
|
||||
};
|
||||
|
||||
static void megamod_irq_cascade(unsigned int __irq, struct irq_desc *desc)
|
||||
static void megamod_irq_cascade(struct irq_desc *desc)
|
||||
{
|
||||
struct megamod_cascade_data *cascade;
|
||||
struct megamod_pic *pic;
|
||||
|
||||
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Reference in New Issue
Block a user