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Pull ticket4byte into release branch
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commit
48fade6c5a
@ -25,61 +25,82 @@
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* by atomically noting the tail and incrementing it by one (thus adding
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* ourself to the queue and noting our position), then waiting until the head
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* becomes equal to the the initial value of the tail.
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* The pad bits in the middle are used to prevent the next_ticket number
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* overflowing into the now_serving number.
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*
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* 63 32 31 0
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* 31 17 16 15 14 0
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* +----------------------------------------------------+
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* | next_ticket_number | now_serving |
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* | now_serving | padding | next_ticket |
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* +----------------------------------------------------+
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*/
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#define TICKET_SHIFT 32
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#define TICKET_SHIFT 17
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#define TICKET_BITS 15
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#define TICKET_MASK ((1 << TICKET_BITS) - 1)
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static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
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{
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int *p = (int *)&lock->lock, turn, now_serving;
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int *p = (int *)&lock->lock, ticket, serve;
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now_serving = *p;
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turn = ia64_fetchadd(1, p+1, acq);
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ticket = ia64_fetchadd(1, p, acq);
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if (turn == now_serving)
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if (!(((ticket >> TICKET_SHIFT) ^ ticket) & TICKET_MASK))
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return;
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do {
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ia64_invala();
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for (;;) {
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asm volatile ("ld4.c.nc %0=[%1]" : "=r"(serve) : "r"(p) : "memory");
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if (!(((serve >> TICKET_SHIFT) ^ ticket) & TICKET_MASK))
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return;
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cpu_relax();
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} while (ACCESS_ONCE(*p) != turn);
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}
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}
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static __always_inline int __ticket_spin_trylock(raw_spinlock_t *lock)
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{
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long tmp = ACCESS_ONCE(lock->lock), try;
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int tmp = ACCESS_ONCE(lock->lock);
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if (!(((tmp >> TICKET_SHIFT) ^ tmp) & ((1L << TICKET_SHIFT) - 1))) {
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try = tmp + (1L << TICKET_SHIFT);
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return ia64_cmpxchg(acq, &lock->lock, tmp, try, sizeof (tmp)) == tmp;
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}
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if (!(((tmp >> TICKET_SHIFT) ^ tmp) & TICKET_MASK))
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return ia64_cmpxchg(acq, &lock->lock, tmp, tmp + 1, sizeof (tmp)) == tmp;
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return 0;
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}
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static __always_inline void __ticket_spin_unlock(raw_spinlock_t *lock)
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{
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int *p = (int *)&lock->lock;
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unsigned short *p = (unsigned short *)&lock->lock + 1, tmp;
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(void)ia64_fetchadd(1, p, rel);
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asm volatile ("ld2.bias %0=[%1]" : "=r"(tmp) : "r"(p));
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ACCESS_ONCE(*p) = (tmp + 2) & ~1;
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}
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static __always_inline void __ticket_spin_unlock_wait(raw_spinlock_t *lock)
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{
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int *p = (int *)&lock->lock, ticket;
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ia64_invala();
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for (;;) {
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asm volatile ("ld4.c.nc %0=[%1]" : "=r"(ticket) : "r"(p) : "memory");
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if (!(((ticket >> TICKET_SHIFT) ^ ticket) & TICKET_MASK))
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return;
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cpu_relax();
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}
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}
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static inline int __ticket_spin_is_locked(raw_spinlock_t *lock)
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{
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long tmp = ACCESS_ONCE(lock->lock);
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return !!(((tmp >> TICKET_SHIFT) ^ tmp) & ((1L << TICKET_SHIFT) - 1));
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return !!(((tmp >> TICKET_SHIFT) ^ tmp) & TICKET_MASK);
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}
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static inline int __ticket_spin_is_contended(raw_spinlock_t *lock)
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{
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long tmp = ACCESS_ONCE(lock->lock);
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return (((tmp >> TICKET_SHIFT) - tmp) & ((1L << TICKET_SHIFT) - 1)) > 1;
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return ((tmp - (tmp >> TICKET_SHIFT)) & TICKET_MASK) > 1;
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}
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static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
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@ -116,8 +137,7 @@ static __always_inline void __raw_spin_lock_flags(raw_spinlock_t *lock,
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static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
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{
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while (__raw_spin_is_locked(lock))
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cpu_relax();
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__ticket_spin_unlock_wait(lock);
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}
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#define __raw_read_can_lock(rw) (*(volatile int *)(rw) >= 0)
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@ -6,7 +6,7 @@
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#endif
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typedef struct {
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volatile unsigned long lock;
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volatile unsigned int lock;
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} raw_spinlock_t;
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#define __RAW_SPIN_LOCK_UNLOCKED { 0 }
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