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wifi: rtl8xxxu: Name some bits used in burst init

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Use descriptive names instead of magic numbers.

Suggested-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com>
Reviewed-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/e7d05bd9-e096-8361-f1b4-3c8b8599a7eb@gmail.com
This commit is contained in:
Bitterblue Smith 2022-11-10 15:58:16 +02:00 committed by Kalle Valo
parent e948023d5f
commit 486e0315c4
2 changed files with 11 additions and 5 deletions
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10
drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
View File

@ -3786,16 +3786,16 @@ void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv)
* For USB high speed set 512B packets
*/
val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
val8 &= ~(BIT(4) | BIT(5));
val8 |= BIT(4);
val8 |= BIT(1) | BIT(2) | BIT(3);
u8p_replace_bits(&val8, 1, RXDMA_PRO_DMA_BURST_SIZE);
u8p_replace_bits(&val8, 3, RXDMA_PRO_DMA_BURST_CNT);
val8 |= RXDMA_PRO_DMA_MODE;
rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);
/*
* Enable single packet AMPDU
*/
val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);
val8 |= BIT(7);
val8 |= HT_SINGLE_AMPDU_ENABLE;
rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14);
@ -3820,7 +3820,7 @@ void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv)
/* to prevent mac is reseted by bus. */
val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
val8 |= BIT(5) | BIT(6);
val8 |= RSV_CTRL_WLOCK_1C | RSV_CTRL_DIS_PRST;
rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
}

6
drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
View File

@ -68,6 +68,8 @@
#define REG_SPS_OCP_CFG 0x0018
#define REG_8192E_LDOV12_CTRL 0x0014
#define REG_RSV_CTRL 0x001c
#define RSV_CTRL_WLOCK_1C BIT(5)
#define RSV_CTRL_DIS_PRST BIT(6)
#define REG_RF_CTRL 0x001f
#define RF_ENABLE BIT(0)
@ -472,6 +474,9 @@
/* Presumably only found on newer chips such as 8723bu */
#define REG_RX_DMA_CTRL_8723B 0x0286
#define REG_RXDMA_PRO_8723B 0x0290
#define RXDMA_PRO_DMA_MODE BIT(1) /* Set to 0x1. */
#define RXDMA_PRO_DMA_BURST_CNT GENMASK(3, 2) /* Set to 0x3. */
#define RXDMA_PRO_DMA_BURST_SIZE GENMASK(5, 4) /* Set to 0x1. */
#define REG_RF_BB_CMD_ADDR 0x02c0
#define REG_RF_BB_CMD_DATA 0x02c4
@ -577,6 +582,7 @@
#define REG_STBC_SETTING 0x04c4
#define REG_QUEUE_CTRL 0x04c6
#define REG_HT_SINGLE_AMPDU_8723B 0x04c7
#define HT_SINGLE_AMPDU_ENABLE BIT(7)
#define REG_PROT_MODE_CTRL 0x04c8
#define REG_MAX_AGGR_NUM 0x04ca
#define REG_RTS_MAX_AGGR_NUM 0x04cb