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EDAC, altera: Add Arria10 QSPI support

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Add Altera Arria10 QSPI FIFO memory support.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1468512408-5156-9-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>
This commit is contained in:
Thor Thayer 2016-07-14 11:06:46 -05:00 committed by Borislav Petkov
parent c609581d1f
commit 485fe9e24e
2 changed files with 39 additions and 1 deletions
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7
drivers/edac/Kconfig
View File

@ -419,6 +419,13 @@ config EDAC_ALTERA_USB
Support for error detection and correction on the Support for error detection and correction on the
Altera USB FIFO Memory for Altera SoCs. Altera USB FIFO Memory for Altera SoCs.
config EDAC_ALTERA_QSPI
bool "Altera QSPI FIFO ECC"
depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
help
Support for error detection and correction on the
Altera QSPI FIFO Memory for Altera SoCs.
config EDAC_SYNOPSYS config EDAC_SYNOPSYS
tristate "Synopsys DDR Memory Controller" tristate "Synopsys DDR Memory Controller"
depends on EDAC_MM_EDAC && ARCH_ZYNQ depends on EDAC_MM_EDAC && ARCH_ZYNQ

33
drivers/edac/altera_edac.c
View File

@ -1366,6 +1366,33 @@ early_initcall(socfpga_init_usb_ecc);
#endif /* CONFIG_EDAC_ALTERA_USB */ #endif /* CONFIG_EDAC_ALTERA_USB */
/********************** QSPI Device Functions **********************/
#ifdef CONFIG_EDAC_ALTERA_QSPI
static const struct edac_device_prv_data a10_qspiecc_data = {
.setup = altr_check_ecc_deps,
.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
.dbgfs_name = "altr_trigger",
.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
.ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
.ce_set_mask = ALTR_A10_ECC_TSERRA,
.ue_set_mask = ALTR_A10_ECC_TDERRA,
.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
.ecc_irq_handler = altr_edac_a10_ecc_irq,
.inject_fops = &altr_edac_a10_device_inject_fops,
};
static int __init socfpga_init_qspi_ecc(void)
{
return altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
}
early_initcall(socfpga_init_qspi_ecc);
#endif /* CONFIG_EDAC_ALTERA_QSPI */
/********************* Arria10 EDAC Device Functions *************************/ /********************* Arria10 EDAC Device Functions *************************/
static const struct of_device_id altr_edac_a10_device_of_match[] = { static const struct of_device_id altr_edac_a10_device_of_match[] = {
#ifdef CONFIG_EDAC_ALTERA_L2C #ifdef CONFIG_EDAC_ALTERA_L2C
@ -1387,6 +1414,9 @@ static const struct of_device_id altr_edac_a10_device_of_match[] = {
#endif #endif
#ifdef CONFIG_EDAC_ALTERA_USB #ifdef CONFIG_EDAC_ALTERA_USB
{ .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data }, { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data },
#endif
#ifdef CONFIG_EDAC_ALTERA_QSPI
{ .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data },
#endif #endif
{}, {},
}; };
@ -1680,7 +1710,8 @@ static int altr_edac_a10_probe(struct platform_device *pdev)
of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") || of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") ||
of_device_is_compatible(child, "altr,socfpga-nand-ecc") || of_device_is_compatible(child, "altr,socfpga-nand-ecc") ||
of_device_is_compatible(child, "altr,socfpga-dma-ecc") || of_device_is_compatible(child, "altr,socfpga-dma-ecc") ||
of_device_is_compatible(child, "altr,socfpga-usb-ecc")) of_device_is_compatible(child, "altr,socfpga-usb-ecc") ||
of_device_is_compatible(child, "altr,socfpga-qspi-ecc"))
altr_edac_a10_device_add(edac, child); altr_edac_a10_device_add(edac, child);