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net/mlx5: Set QP timestamp mode to default
QPs which don't care from timestamp mode, should set the ts_format
to default, otherwise the QP creation could be failed if the timestamp
mode is not supported.
Fixes: 2fe8d4b878
("RDMA/mlx5: Fail QP creation if the device can not support the CQE TS")
Signed-off-by: Maor Gottlieb <maorg@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
This commit is contained in:
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469549e477
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@ -575,6 +575,7 @@ static int mlx5_fpga_conn_create_qp(struct mlx5_fpga_conn *conn,
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MLX5_SET(qpc, qpc, log_sq_size, ilog2(conn->qp.sq.size));
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MLX5_SET(qpc, qpc, cqn_snd, conn->cq.mcq.cqn);
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MLX5_SET(qpc, qpc, cqn_rcv, conn->cq.mcq.cqn);
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MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(mdev));
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MLX5_SET64(qpc, qpc, dbr_addr, conn->qp.wq_ctrl.db.dma);
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if (MLX5_CAP_GEN(mdev, cqe_version) == 1)
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MLX5_SET(qpc, qpc, user_index, 0xFFFFFF);
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@ -233,6 +233,7 @@ int mlx5i_create_underlay_qp(struct mlx5e_priv *priv)
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}
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qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
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MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(priv->mdev));
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MLX5_SET(qpc, qpc, st, MLX5_QP_ST_UD);
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MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
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MLX5_SET(qpc, qpc, ulp_stateless_offload_mode,
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@ -169,6 +169,7 @@ static struct mlx5dr_qp *dr_create_rc_qp(struct mlx5_core_dev *mdev,
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MLX5_SET(qpc, qpc, log_rq_size, ilog2(dr_qp->rq.wqe_cnt));
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MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
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MLX5_SET(qpc, qpc, log_sq_size, ilog2(dr_qp->sq.wqe_cnt));
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MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(mdev));
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MLX5_SET64(qpc, qpc, dbr_addr, dr_qp->wq_ctrl.db.dma);
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if (MLX5_CAP_GEN(mdev, cqe_version) == 1)
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MLX5_SET(qpc, qpc, user_index, 0xFFFFFF);
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@ -547,4 +547,11 @@ static inline const char *mlx5_qp_state_str(int state)
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}
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}
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static inline int mlx5_get_qp_default_ts(struct mlx5_core_dev *dev)
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{
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return !MLX5_CAP_ROCE(dev, qp_ts_format) ?
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MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :
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MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
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}
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#endif /* MLX5_QP_H */
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