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KVM/arm64 updates for 5.19

Browse Source 
- Add support for the ARMv8.6 WFxT extension
 
 - Guard pages for the EL2 stacks
 
 - Trap and emulate AArch32 ID registers to hide unsupported features
 
 - Ability to select and save/restore the set of hypercalls exposed
   to the guest
 
 - Support for PSCI-initiated suspend in collaboration with userspace
 
 - GICv3 register-based LPI invalidation support
 
 - Move host PMU event merging into the vcpu data structure
 
 - GICv3 ITS save/restore fixes
 
 - The usual set of small-scale cleanups and fixes
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Merge tag 'kvmarm-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD

KVM/arm64 updates for 5.19

- Add support for the ARMv8.6 WFxT extension

- Guard pages for the EL2 stacks

- Trap and emulate AArch32 ID registers to hide unsupported features

- Ability to select and save/restore the set of hypercalls exposed
  to the guest

- Support for PSCI-initiated suspend in collaboration with userspace

- GICv3 register-based LPI invalidation support

- Move host PMU event merging into the vcpu data structure

- GICv3 ITS save/restore fixes

- The usual set of small-scale cleanups and fixes

[Due to the conflict, KVM_SYSTEM_EVENT_SEV_TERM is relocated
 from 4 to 6. - Paolo]
This commit is contained in:
Paolo Bonzini 2022-05-20 07:16:27 -04:00
commit 47e8eec832
1425 changed files with 17263 additions and 9788 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
.mailmap
View File

@ -391,6 +391,10 @@ Uwe Kleine-König <ukleinek@strlen.de>
Uwe Kleine-König <ukl@pengutronix.de>
Uwe Kleine-König <Uwe.Kleine-Koenig@digi.com>
Valdis Kletnieks <Valdis.Kletnieks@vt.edu>
Vasily Averin <vasily.averin@linux.dev> <vvs@virtuozzo.com>
Vasily Averin <vasily.averin@linux.dev> <vvs@openvz.org>
Vasily Averin <vasily.averin@linux.dev> <vvs@parallels.com>
Vasily Averin <vasily.averin@linux.dev> <vvs@sw.ru>
Vinod Koul <vkoul@kernel.org> <vinod.koul@intel.com>
Vinod Koul <vkoul@kernel.org> <vinod.koul@linux.intel.com>
Vinod Koul <vkoul@kernel.org> <vkoul@infradead.org>

48
Documentation/ABI/testing/sysfs-class-firmware-attributes
View File

@ -116,7 +116,7 @@ Description:
<value>[ForceIf:<attribute>=<value>]
<value>[ForceIfNot:<attribute>=<value>]
For example:
For example::
LegacyOrom/dell_value_modifier has value:
Disabled[ForceIf:SecureBoot=Enabled]
@ -212,7 +212,7 @@ Description:
the next boot.
Lenovo specific class extensions
------------------------------
--------------------------------
On Lenovo systems the following additional settings are available:
@ -246,9 +246,7 @@ Description:
that is being referenced (e.g hdd0, hdd1 etc)
This attribute defaults to device 0.
certificate:
signature:
save_signature:
certificate, signature, save_signature:
These attributes are used for certificate based authentication. This is
used in conjunction with a signing server as an alternative to password
based authentication.
@ -257,22 +255,27 @@ Description:
The attributes can be displayed to check the stored value.
Some usage examples:
Installing a certificate to enable feature:
echo <supervisor password > authentication/Admin/current_password
echo <signed certificate> > authentication/Admin/certificate
Updating the installed certificate:
echo <signature> > authentication/Admin/signature
echo <signed certificate> > authentication/Admin/certificate
Installing a certificate to enable feature::
Removing the installed certificate:
echo <signature> > authentication/Admin/signature
echo '' > authentication/Admin/certificate
echo "supervisor password" > authentication/Admin/current_password
echo "signed certificate" > authentication/Admin/certificate
Changing a BIOS setting:
echo <signature> > authentication/Admin/signature
echo <save signature> > authentication/Admin/save_signature
echo Enable > attribute/PasswordBeep/current_value
Updating the installed certificate::
echo "signature" > authentication/Admin/signature
echo "signed certificate" > authentication/Admin/certificate
Removing the installed certificate::
echo "signature" > authentication/Admin/signature
echo "" > authentication/Admin/certificate
Changing a BIOS setting::
echo "signature" > authentication/Admin/signature
echo "save signature" > authentication/Admin/save_signature
echo Enable > attribute/PasswordBeep/current_value
You cannot enable certificate authentication if a supervisor password
has not been set.
@ -288,9 +291,10 @@ Description:
certificate_to_password:
Write only attribute used to switch from certificate based authentication
back to password based.
Usage:
echo <signature> > authentication/Admin/signature
echo <password> > authentication/Admin/certificate_to_password
Usage::
echo "signature" > authentication/Admin/signature
echo "password" > authentication/Admin/certificate_to_password
What: /sys/class/firmware-attributes/*/attributes/pending_reboot
@ -345,7 +349,7 @@ Description:
# echo "factory" > /sys/class/firmware-attributes/*/device/attributes/reset_bios
# cat /sys/class/firmware-attributes/*/device/attributes/reset_bios
# builtinsafe lastknowngood [factory] custom
builtinsafe lastknowngood [factory] custom
Note that any changes to this attribute requires a reboot
for changes to take effect.

18
Documentation/ABI/testing/sysfs-driver-intel_sdsi
View File

@ -13,17 +13,19 @@ Description:
Should the operation fail, one of the following error codes
may be returned:
========== =====
Error Code Cause
---------- -----
EIO General mailbox failure. Log may indicate cause.
EBUSY Mailbox is owned by another agent.
EPERM SDSI capability is not enabled in hardware.
EPROTO Failure in mailbox protocol detected by driver.
========== =====
EIO General mailbox failure. Log may indicate cause.
EBUSY Mailbox is owned by another agent.
EPERM SDSI capability is not enabled in hardware.
EPROTO Failure in mailbox protocol detected by driver.
See log for details.
EOVERFLOW For provision commands, the size of the data
EOVERFLOW For provision commands, the size of the data
exceeds what may be written.
ESPIPE Seeking is not allowed.
ETIMEDOUT Failure to complete mailbox transaction in time.
ESPIPE Seeking is not allowed.
ETIMEDOUT Failure to complete mailbox transaction in time.
========== =====
What: /sys/bus/auxiliary/devices/intel_vsec.sdsi.X/guid
Date: Feb 2022

5
Documentation/ABI/testing/sysfs-fs-erofs
View File

@ -9,8 +9,9 @@ Description: Shows all enabled kernel features.
What: /sys/fs/erofs/<disk>/sync_decompress
Date: November 2021
Contact: "Huang Jianan" <huangjianan@oppo.com>
Description: Control strategy of sync decompression
Description: Control strategy of sync decompression:
- 0 (default, auto): enable for readpage, and enable for
readahead on atomic contexts only,
readahead on atomic contexts only.
- 1 (force on): enable for readpage and readahead.
- 2 (force off): disable for all situations.

2
Documentation/arm64/cpu-feature-registers.rst
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@ -290,6 +290,8 @@ infrastructure:
+------------------------------+---------+---------+
| RPRES | [7-4] | y |
+------------------------------+---------+---------+
| WFXT | [3-0] | y |
+------------------------------+---------+---------+
Appendix I: Example

37
Documentation/arm64/elf_hwcaps.rst
View File

@ -264,6 +264,43 @@ HWCAP2_MTE3
Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0011, as described
by Documentation/arm64/memory-tagging-extension.rst.
HWCAP2_SME
Functionality implied by ID_AA64PFR1_EL1.SME == 0b0001, as described
by Documentation/arm64/sme.rst.
HWCAP2_SME_I16I64
Functionality implied by ID_AA64SMFR0_EL1.I16I64 == 0b1111.
HWCAP2_SME_F64F64
Functionality implied by ID_AA64SMFR0_EL1.F64F64 == 0b1.
HWCAP2_SME_I8I32
Functionality implied by ID_AA64SMFR0_EL1.I8I32 == 0b1111.
HWCAP2_SME_F16F32
Functionality implied by ID_AA64SMFR0_EL1.F16F32 == 0b1.
HWCAP2_SME_B16F32
Functionality implied by ID_AA64SMFR0_EL1.B16F32 == 0b1.
HWCAP2_SME_F32F32
Functionality implied by ID_AA64SMFR0_EL1.F32F32 == 0b1.
HWCAP2_SME_FA64
Functionality implied by ID_AA64SMFR0_EL1.FA64 == 0b1.
HWCAP2_WFXT
Functionality implied by ID_AA64ISAR2_EL1.WFXT == 0b0010.
4. Unused AT_HWCAP bits
-----------------------

1
Documentation/arm64/index.rst
View File

@ -21,6 +21,7 @@ ARM64 Architecture
perf
pointer-authentication
silicon-errata
sme
sve
tagged-address-abi
tagged-pointers

4
Documentation/arm64/memory-tagging-extension.rst
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@ -228,10 +228,10 @@ Core dump support
-----------------
The allocation tags for user memory mapped with ``PROT_MTE`` are dumped
in the core file as additional ``PT_ARM_MEMTAG_MTE`` segments. The
in the core file as additional ``PT_AARCH64_MEMTAG_MTE`` segments. The
program header for such segment is defined as:
:``p_type``: ``PT_ARM_MEMTAG_MTE``
:``p_type``: ``PT_AARCH64_MEMTAG_MTE``
:``p_flags``: 0
:``p_offset``: segment file offset
:``p_vaddr``: segment virtual address, same as the corresponding

428
Documentation/arm64/sme.rst Normal file
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@ -0,0 +1,428 @@
===================================================
Scalable Matrix Extension support for AArch64 Linux
===================================================
This document outlines briefly the interface provided to userspace by Linux in
order to support use of the ARM Scalable Matrix Extension (SME).
This is an outline of the most important features and issues only and not
intended to be exhaustive. It should be read in conjunction with the SVE
documentation in sve.rst which provides details on the Streaming SVE mode
included in SME.
This document does not aim to describe the SME architecture or programmer's
model. To aid understanding, a minimal description of relevant programmer's
model features for SME is included in Appendix A.
1. General
-----------
* PSTATE.SM, PSTATE.ZA, the streaming mode vector length, the ZA
register state and TPIDR2_EL0 are tracked per thread.
* The presence of SME is reported to userspace via HWCAP2_SME in the aux vector
AT_HWCAP2 entry. Presence of this flag implies the presence of the SME
instructions and registers, and the Linux-specific system interfaces
described in this document. SME is reported in /proc/cpuinfo as "sme".
* Support for the execution of SME instructions in userspace can also be
detected by reading the CPU ID register ID_AA64PFR1_EL1 using an MRS
instruction, and checking that the value of the SME field is nonzero. [3]
It does not guarantee the presence of the system interfaces described in the
following sections: software that needs to verify that those interfaces are
present must check for HWCAP2_SME instead.
* There are a number of optional SME features, presence of these is reported
through AT_HWCAP2 through:
HWCAP2_SME_I16I64
HWCAP2_SME_F64F64
HWCAP2_SME_I8I32
HWCAP2_SME_F16F32
HWCAP2_SME_B16F32
HWCAP2_SME_F32F32
HWCAP2_SME_FA64
This list may be extended over time as the SME architecture evolves.
These extensions are also reported via the CPU ID register ID_AA64SMFR0_EL1,
which userspace can read using an MRS instruction. See elf_hwcaps.txt and
cpu-feature-registers.txt for details.
* Debuggers should restrict themselves to interacting with the target via the
NT_ARM_SVE, NT_ARM_SSVE and NT_ARM_ZA regsets. The recommended way
of detecting support for these regsets is to connect to a target process
first and then attempt a
ptrace(PTRACE_GETREGSET, pid, NT_ARM_<regset>, &iov).
* Whenever ZA register values are exchanged in memory between userspace and
the kernel, the register value is encoded in memory as a series of horizontal
vectors from 0 to VL/8-1 stored in the same endianness invariant format as is
used for SVE vectors.
* On thread creation TPIDR2_EL0 is preserved unless CLONE_SETTLS is specified,
in which case it is set to 0.
2. Vector lengths
------------------
SME defines a second vector length similar to the SVE vector length which is
controls the size of the streaming mode SVE vectors and the ZA matrix array.
The ZA matrix is square with each side having as many bytes as a streaming
mode SVE vector.
3. Sharing of streaming and non-streaming mode SVE state
---------------------------------------------------------
It is implementation defined which if any parts of the SVE state are shared
between streaming and non-streaming modes. When switching between modes
via software interfaces such as ptrace if no register content is provided as
part of switching no state will be assumed to be shared and everything will
be zeroed.
4. System call behaviour
-------------------------
* On syscall PSTATE.ZA is preserved, if PSTATE.ZA==1 then the contents of the
ZA matrix are preserved.
* On syscall PSTATE.SM will be cleared and the SVE registers will be handled
as per the standard SVE ABI.
* Neither the SVE registers nor ZA are used to pass arguments to or receive
results from any syscall.
* On process creation (eg, clone()) the newly created process will have
PSTATE.SM cleared.
* All other SME state of a thread, including the currently configured vector
length, the state of the PR_SME_VL_INHERIT flag, and the deferred vector
length (if any), is preserved across all syscalls, subject to the specific
exceptions for execve() described in section 6.
5. Signal handling
-------------------
* Signal handlers are invoked with streaming mode and ZA disabled.
* A new signal frame record za_context encodes the ZA register contents on
signal delivery. [1]
* The signal frame record for ZA always contains basic metadata, in particular
the thread's vector length (in za_context.vl).
* The ZA matrix may or may not be included in the record, depending on
the value of PSTATE.ZA. The registers are present if and only if:
za_context.head.size >= ZA_SIG_CONTEXT_SIZE(sve_vq_from_vl(za_context.vl))
in which case PSTATE.ZA == 1.
* If matrix data is present, the remainder of the record has a vl-dependent
size and layout. Macros ZA_SIG_* are defined [1] to facilitate access to
them.
* The matrix is stored as a series of horizontal vectors in the same format as
is used for SVE vectors.
* If the ZA context is too big to fit in sigcontext.__reserved[], then extra
space is allocated on the stack, an extra_context record is written in
__reserved[] referencing this space. za_context is then written in the
extra space. Refer to [1] for further details about this mechanism.
5. Signal return
-----------------
When returning from a signal handler:
* If there is no za_context record in the signal frame, or if the record is
present but contains no register data as described in the previous section,
then ZA is disabled.
* If za_context is present in the signal frame and contains matrix data then
PSTATE.ZA is set to 1 and ZA is populated with the specified data.
* The vector length cannot be changed via signal return. If za_context.vl in
the signal frame does not match the current vector length, the signal return
attempt is treated as illegal, resulting in a forced SIGSEGV.
6. prctl extensions
--------------------
Some new prctl() calls are added to allow programs to manage the SME vector
length:
prctl(PR_SME_SET_VL, unsigned long arg)
Sets the vector length of the calling thread and related flags, where
arg == vl | flags. Other threads of the calling process are unaffected.
vl is the desired vector length, where sve_vl_valid(vl) must be true.
flags:
PR_SME_VL_INHERIT
Inherit the current vector length across execve(). Otherwise, the
vector length is reset to the system default at execve(). (See
Section 9.)
PR_SME_SET_VL_ONEXEC
Defer the requested vector length change until the next execve()
performed by this thread.
The effect is equivalent to implicit execution of the following
call immediately after the next execve() (if any) by the thread:
prctl(PR_SME_SET_VL, arg & ~PR_SME_SET_VL_ONEXEC)
This allows launching of a new program with a different vector
length, while avoiding runtime side effects in the caller.
Without PR_SME_SET_VL_ONEXEC, the requested change takes effect
immediately.
Return value: a nonnegative on success, or a negative value on error:
EINVAL: SME not supported, invalid vector length requested, or
invalid flags.
On success:
* Either the calling thread's vector length or the deferred vector length
to be applied at the next execve() by the thread (dependent on whether
PR_SME_SET_VL_ONEXEC is present in arg), is set to the largest value
supported by the system that is less than or equal to vl. If vl ==
SVE_VL_MAX, the value set will be the largest value supported by the
system.
* Any previously outstanding deferred vector length change in the calling
thread is cancelled.
* The returned value describes the resulting configuration, encoded as for
PR_SME_GET_VL. The vector length reported in this value is the new
current vector length for this thread if PR_SME_SET_VL_ONEXEC was not
present in arg; otherwise, the reported vector length is the deferred
vector length that will be applied at the next execve() by the calling
thread.
* Changing the vector length causes all of ZA, P0..P15, FFR and all bits of
Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become
unspecified, including both streaming and non-streaming SVE state.
Calling PR_SME_SET_VL with vl equal to the thread's current vector
length, or calling PR_SME_SET_VL with the PR_SVE_SET_VL_ONEXEC flag,
does not constitute a change to the vector length for this purpose.
* Changing the vector length causes PSTATE.ZA and PSTATE.SM to be cleared.
Calling PR_SME_SET_VL with vl equal to the thread's current vector
length, or calling PR_SME_SET_VL with the PR_SVE_SET_VL_ONEXEC flag,
does not constitute a change to the vector length for this purpose.
prctl(PR_SME_GET_VL)
Gets the vector length of the calling thread.
The following flag may be OR-ed into the result:
PR_SME_VL_INHERIT
Vector length will be inherited across execve().
There is no way to determine whether there is an outstanding deferred
vector length change (which would only normally be the case between a
fork() or vfork() and the corresponding execve() in typical use).
To extract the vector length from the result, bitwise and it with
PR_SME_VL_LEN_MASK.
Return value: a nonnegative value on success, or a negative value on error:
EINVAL: SME not supported.
7. ptrace extensions
---------------------
* A new regset NT_ARM_SSVE is defined for access to streaming mode SVE
state via PTRACE_GETREGSET and PTRACE_SETREGSET, this is documented in
sve.rst.
* A new regset NT_ARM_ZA is defined for ZA state for access to ZA state via
PTRACE_GETREGSET and PTRACE_SETREGSET.
Refer to [2] for definitions.
The regset data starts with struct user_za_header, containing:
size
Size of the complete regset, in bytes.
This depends on vl and possibly on other things in the future.
If a call to PTRACE_GETREGSET requests less data than the value of
size, the caller can allocate a larger buffer and retry in order to
read the complete regset.
max_size
Maximum size in bytes that the regset can grow to for the target
thread. The regset won't grow bigger than this even if the target
thread changes its vector length etc.
vl
Target thread's current streaming vector length, in bytes.
max_vl
Maximum possible streaming vector length for the target thread.
flags
Zero or more of the following flags, which have the same
meaning and behaviour as the corresponding PR_SET_VL_* flags:
SME_PT_VL_INHERIT
SME_PT_VL_ONEXEC (SETREGSET only).
* The effects of changing the vector length and/or flags are equivalent to
those documented for PR_SME_SET_VL.
The caller must make a further GETREGSET call if it needs to know what VL is
actually set by SETREGSET, unless is it known in advance that the requested
VL is supported.
* The size and layout of the payload depends on the header fields. The
SME_PT_ZA_*() macros are provided to facilitate access to the data.
* In either case, for SETREGSET it is permissible to omit the payload, in which
case the vector length and flags are changed and PSTATE.ZA is set to 0
(along with any consequences of those changes). If a payload is provided
then PSTATE.ZA will be set to 1.
* For SETREGSET, if the requested VL is not supported, the effect will be the
same as if the payload were omitted, except that an EIO error is reported.
No attempt is made to translate the payload data to the correct layout
for the vector length actually set. It is up to the caller to translate the
payload layout for the actual VL and retry.
* The effect of writing a partial, incomplete payload is unspecified.
8. ELF coredump extensions
---------------------------
* NT_ARM_SSVE notes will be added to each coredump for
each thread of the dumped process. The contents will be equivalent to the
data that would have been read if a PTRACE_GETREGSET of the corresponding
type were executed for each thread when the coredump was generated.
* A NT_ARM_ZA note will be added to each coredump for each thread of the
dumped process. The contents will be equivalent to the data that would have
been read if a PTRACE_GETREGSET of NT_ARM_ZA were executed for each thread
when the coredump was generated.
9. System runtime configuration
--------------------------------
* To mitigate the ABI impact of expansion of the signal frame, a policy
mechanism is provided for administrators, distro maintainers and developers
to set the default vector length for userspace processes:
/proc/sys/abi/sme_default_vector_length
Writing the text representation of an integer to this file sets the system
default vector length to the specified value, unless the value is greater
than the maximum vector length supported by the system in which case the
default vector length is set to that maximum.
The result can be determined by reopening the file and reading its
contents.
At boot, the default vector length is initially set to 32 or the maximum
supported vector length, whichever is smaller and supported. This
determines the initial vector length of the init process (PID 1).
Reading this file returns the current system default vector length.
* At every execve() call, the new vector length of the new process is set to
the system default vector length, unless
* PR_SME_VL_INHERIT (or equivalently SME_PT_VL_INHERIT) is set for the
calling thread, or
* a deferred vector length change is pending, established via the
PR_SME_SET_VL_ONEXEC flag (or SME_PT_VL_ONEXEC).
* Modifying the system default vector length does not affect the vector length
of any existing process or thread that does not make an execve() call.
Appendix A. SME programmer's model (informative)
=================================================
This section provides a minimal description of the additions made by SVE to the
ARMv8-A programmer's model that are relevant to this document.
Note: This section is for information only and not intended to be complete or
to replace any architectural specification.
A.1. Registers
---------------
In A64 state, SME adds the following:
* A new mode, streaming mode, in which a subset of the normal FPSIMD and SVE
features are available. When supported EL0 software may enter and leave
streaming mode at any time.
For best system performance it is strongly encouraged for software to enable
streaming mode only when it is actively being used.
* A new vector length controlling the size of ZA and the Z registers when in
streaming mode, separately to the vector length used for SVE when not in
streaming mode. There is no requirement that either the currently selected
vector length or the set of vector lengths supported for the two modes in
a given system have any relationship. The streaming mode vector length
is referred to as SVL.
* A new ZA matrix register. This is a square matrix of SVLxSVL bits. Most
operations on ZA require that streaming mode be enabled but ZA can be
enabled without streaming mode in order to load, save and retain data.
For best system performance it is strongly encouraged for software to enable
ZA only when it is actively being used.
* Two new 1 bit fields in PSTATE which may be controlled via the SMSTART and
SMSTOP instructions or by access to the SVCR system register:
* PSTATE.ZA, if this is 1 then the ZA matrix is accessible and has valid
data while if it is 0 then ZA can not be accessed. When PSTATE.ZA is
changed from 0 to 1 all bits in ZA are cleared.
* PSTATE.SM, if this is 1 then the PE is in streaming mode. When the value
of PSTATE.SM is changed then it is implementation defined if the subset
of the floating point register bits valid in both modes may be retained.
Any other bits will be cleared.
References
==========
[1] arch/arm64/include/uapi/asm/sigcontext.h
AArch64 Linux signal ABI definitions
[2] arch/arm64/include/uapi/asm/ptrace.h
AArch64 Linux ptrace ABI definitions
[3] Documentation/arm64/cpu-feature-registers.rst

70
Documentation/arm64/sve.rst
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@ -7,7 +7,9 @@ Author: Dave Martin <Dave.Martin@arm.com>
Date: 4 August 2017
This document outlines briefly the interface provided to userspace by Linux in
order to support use of the ARM Scalable Vector Extension (SVE).
order to support use of the ARM Scalable Vector Extension (SVE), including
interactions with Streaming SVE mode added by the Scalable Matrix Extension
(SME).
This is an outline of the most important features and issues only and not
intended to be exhaustive.
@ -23,6 +25,10 @@ model features for SVE is included in Appendix A.
* SVE registers Z0..Z31, P0..P15 and FFR and the current vector length VL, are
tracked per-thread.
* In streaming mode FFR is not accessible unless HWCAP2_SME_FA64 is present
in the system, when it is not supported and these interfaces are used to
access streaming mode FFR is read and written as zero.
* The presence of SVE is reported to userspace via HWCAP_SVE in the aux vector
AT_HWCAP entry. Presence of this flag implies the presence of the SVE
instructions and registers, and the Linux-specific system interfaces
@ -53,10 +59,19 @@ model features for SVE is included in Appendix A.
which userspace can read using an MRS instruction. See elf_hwcaps.txt and
cpu-feature-registers.txt for details.
* On hardware that supports the SME extensions, HWCAP2_SME will also be
reported in the AT_HWCAP2 aux vector entry. Among other things SME adds
streaming mode which provides a subset of the SVE feature set using a
separate SME vector length and the same Z/V registers. See sme.rst
for more details.
* Debuggers should restrict themselves to interacting with the target via the
NT_ARM_SVE regset. The recommended way of detecting support for this regset
is to connect to a target process first and then attempt a
ptrace(PTRACE_GETREGSET, pid, NT_ARM_SVE, &iov).
ptrace(PTRACE_GETREGSET, pid, NT_ARM_SVE, &iov). Note that when SME is
present and streaming SVE mode is in use the FPSIMD subset of registers
will be read via NT_ARM_SVE and NT_ARM_SVE writes will exit streaming mode
in the target.
* Whenever SVE scalable register values (Zn, Pn, FFR) are exchanged in memory
between userspace and the kernel, the register value is encoded in memory in
@ -126,6 +141,11 @@ the SVE instruction set architecture.
are only present in fpsimd_context. For convenience, the content of V0..V31
is duplicated between sve_context and fpsimd_context.
* The record contains a flag field which includes a flag SVE_SIG_FLAG_SM which
if set indicates that the thread is in streaming mode and the vector length
and register data (if present) describe the streaming SVE data and vector
length.
* The signal frame record for SVE always contains basic metadata, in particular
the thread's vector length (in sve_context.vl).
@ -170,6 +190,11 @@ When returning from a signal handler:
the signal frame does not match the current vector length, the signal return
attempt is treated as illegal, resulting in a forced SIGSEGV.
* It is permitted to enter or leave streaming mode by setting or clearing
the SVE_SIG_FLAG_SM flag but applications should take care to ensure that
when doing so sve_context.vl and any register data are appropriate for the
vector length in the new mode.
6. prctl extensions
--------------------
@ -265,8 +290,14 @@ prctl(PR_SVE_GET_VL)
7. ptrace extensions
---------------------
* A new regset NT_ARM_SVE is defined for use with PTRACE_GETREGSET and
PTRACE_SETREGSET.
* New regsets NT_ARM_SVE and NT_ARM_SSVE are defined for use with
PTRACE_GETREGSET and PTRACE_SETREGSET. NT_ARM_SSVE describes the
streaming mode SVE registers and NT_ARM_SVE describes the
non-streaming mode SVE registers.
In this description a register set is referred to as being "live" when
the target is in the appropriate streaming or non-streaming mode and is
using data beyond the subset shared with the FPSIMD Vn registers.
Refer to [2] for definitions.
@ -297,7 +328,7 @@ The regset data starts with struct user_sve_header, containing:
flags
either
at most one of
SVE_PT_REGS_FPSIMD
@ -331,6 +362,10 @@ The regset data starts with struct user_sve_header, containing:
SVE_PT_VL_ONEXEC (SETREGSET only).
If neither FPSIMD nor SVE flags are provided then no register
payload is available, this is only possible when SME is implemented.
* The effects of changing the vector length and/or flags are equivalent to
those documented for PR_SVE_SET_VL.
@ -346,6 +381,13 @@ The regset data starts with struct user_sve_header, containing:
case only the vector length and flags are changed (along with any
consequences of those changes).
* In systems supporting SME when in streaming mode a GETREGSET for
NT_REG_SVE will return only the user_sve_header with no register data,
similarly a GETREGSET for NT_REG_SSVE will not return any register data
when not in streaming mode.
* A GETREGSET for NT_ARM_SSVE will never return SVE_PT_REGS_FPSIMD.
* For SETREGSET, if an SVE_PT_REGS_SVE payload is present and the
requested VL is not supported, the effect will be the same as if the
payload were omitted, except that an EIO error is reported. No
@ -355,17 +397,25 @@ The regset data starts with struct user_sve_header, containing:
unspecified. It is up to the caller to translate the payload layout
for the actual VL and retry.
* Where SME is implemented it is not possible to GETREGSET the register
state for normal SVE when in streaming mode, nor the streaming mode
register state when in normal mode, regardless of the implementation defined
behaviour of the hardware for sharing data between the two modes.
* Any SETREGSET of NT_ARM_SVE will exit streaming mode if the target was in
streaming mode and any SETREGSET of NT_ARM_SSVE will enter streaming mode
if the target was not in streaming mode.
* The effect of writing a partial, incomplete payload is unspecified.
8. ELF coredump extensions
---------------------------
* A NT_ARM_SVE note will be added to each coredump for each thread of the
dumped process. The contents will be equivalent to the data that would have
been read if a PTRACE_GETREGSET of NT_ARM_SVE were executed for each thread
when the coredump was generated.
* NT_ARM_SVE and NT_ARM_SSVE notes will be added to each coredump for
each thread of the dumped process. The contents will be equivalent to the
data that would have been read if a PTRACE_GETREGSET of the corresponding
type were executed for each thread when the coredump was generated.
9. System runtime configuration
--------------------------------

11
Documentation/dev-tools/kunit/start.rst
View File

@ -41,13 +41,18 @@ or ``VFAT_FS``. To run ``FAT_KUNIT_TEST``, the ``.kunitconfig`` has:
CONFIG_MSDOS_FS=y
CONFIG_FAT_KUNIT_TEST=y
1. A good starting point for the ``.kunitconfig``, is the KUnit default
config. Run the command:
1. A good starting point for the ``.kunitconfig`` is the KUnit default config.
You can generate it by running:
.. code-block:: bash
cd $PATH_TO_LINUX_REPO
cp tools/testing/kunit/configs/default.config .kunitconfig
tools/testing/kunit/kunit.py config
cat .kunit/.kunitconfig
.. note ::
``.kunitconfig`` lives in the ``--build_dir`` used by kunit.py, which is
``.kunit`` by default.
.. note ::
You may want to remove CONFIG_KUNIT_ALL_TESTS from the ``.kunitconfig`` as

1
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
View File

@ -13,7 +13,6 @@ maintainers:
properties:
compatible:
enum:
- nvidia,tegra20-pmc
- nvidia,tegra20-pmc
- nvidia,tegra30-pmc
- nvidia,tegra114-pmc

1
Documentation/devicetree/bindings/bus/ti-sysc.yaml
View File

@ -34,7 +34,6 @@ properties:
oneOf:
- items:
- enum:
- ti,sysc-omap2
- ti,sysc-omap2
- ti,sysc-omap4
- ti,sysc-omap4-simple

13
Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
View File

@ -22,7 +22,16 @@ properties:
const: microchip,mpfs-clkcfg
reg:
maxItems: 1
items:
- description: |
clock config registers:
These registers contain enable, reset & divider tables for the, cpu,
axi, ahb and rtc/mtimer reference clocks as well as enable and reset
for the peripheral clocks.
- description: |
mss pll dri registers:
Block of registers responsible for dynamic reconfiguration of the mss
pll
clocks:
maxItems: 1
@ -51,7 +60,7 @@ examples:
#size-cells = <2>;
clkcfg: clock-controller@20002000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x20002000 0x0 0x1000>;
reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
clocks = <&ref>;
#clock-cells = <1>;
};

2
Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml
View File

@ -8,7 +8,7 @@ title: Samsung Exynos SoC Audio SubSystem clock controller
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>

2
Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
View File

@ -8,7 +8,7 @@ title: Samsung Exynos SoC clock controller
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>

2
Documentation/devicetree/bindings/clock/samsung,exynos-ext-clock.yaml
View File

@ -8,7 +8,7 @@ title: Samsung SoC external/osc/XXTI/XusbXTI clock
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>

2
Documentation/devicetree/bindings/clock/samsung,exynos4412-isp-clock.yaml
View File

@ -8,7 +8,7 @@ title: Samsung Exynos4412 SoC ISP clock controller
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>

2
Documentation/devicetree/bindings/clock/samsung,exynos5260-clock.yaml
View File

@ -8,7 +8,7 @@ title: Samsung Exynos5260 SoC clock controller
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>

2
Documentation/devicetree/bindings/clock/samsung,exynos5410-clock.yaml
View File

@ -8,7 +8,7 @@ title: Samsung Exynos5410 SoC clock controller
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>

2
Documentation/devicetree/bindings/clock/samsung,exynos5433-clock.yaml
View File

@ -8,7 +8,7 @@ title: Samsung Exynos5433 SoC clock controller
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>

2
Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml
View File

@ -8,7 +8,7 @@ title: Samsung Exynos7 SoC clock controller
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>

2
Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml
View File

@ -9,7 +9,7 @@ title: Samsung Exynos7885 SoC clock controller
maintainers:
- Dávid Virág <virag.david003@gmail.com>
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>

2
Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
View File

@ -9,7 +9,7 @@ title: Samsung Exynos850 SoC clock controller
maintainers:
- Sam Protsenko <semen.protsenko@linaro.org>
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>

2
Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S2M and S5M family clock generator block
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
This is a part of device tree bindings for S2M and S5M family of Power

2
Documentation/devicetree/bindings/clock/samsung,s5pv210-audss-clock.yaml
View File

@ -8,7 +8,7 @@ title: Samsung S5Pv210 SoC Audio SubSystem clock controller
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>

2
Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.yaml
View File

@ -8,7 +8,7 @@ title: Samsung S5P6442/S5PC110/S5PV210 SoC clock controller
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>

2
Documentation/devicetree/bindings/devfreq/event/samsung,exynos-nocp.yaml
View File

@ -8,7 +8,7 @@ title: Samsung Exynos NoC (Network on Chip) Probe
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
The Samsung Exynos542x SoC has a NoC (Network on Chip) Probe for NoC bus.

2
Documentation/devicetree/bindings/devfreq/event/samsung,exynos-ppmu.yaml
View File

@ -8,7 +8,7 @@ title: Samsung Exynos SoC PPMU (Platform Performance Monitoring Unit)
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
The Samsung Exynos SoC has PPMU (Platform Performance Monitoring Unit) for

1
Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
View File

@ -51,7 +51,6 @@ properties:
Video port for MIPI DPI output (panel or connector).
required:
- port@0
- port@1
required:

1
Documentation/devicetree/bindings/display/bridge/toshiba,tc358762.yaml
View File

@ -39,7 +39,6 @@ properties:
Video port for MIPI DPI output (panel or connector).
required:
- port@0
- port@1
required:

4
Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml
View File

@ -160,7 +160,7 @@ examples:
mdss: mdss@5e00000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "qcom,qcm2290-mdss", "qcom,mdss";
compatible = "qcom,qcm2290-mdss";
reg = <0x05e00000 0x1000>;
reg-names = "mdss";
power-domains = <&dispcc MDSS_GDSC>;
@ -180,7 +180,7 @@ examples:
<&apps_smmu 0x421 0x0>;
ranges;
mdss_mdp: mdp@5e01000 {
mdss_mdp: display-controller@5e01000 {
compatible = "qcom,qcm2290-dpu";
reg = <0x05e01000 0x8f000>,
<0x05eb0000 0x2008>;

2
Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml
View File

@ -83,6 +83,8 @@ properties:
required:
- compatible
- reg
- width-mm
- height-mm
- panel-timing
unevaluatedProperties: false

42
Documentation/devicetree/bindings/display/panel/panel-timing.yaml
View File

@ -71,78 +71,72 @@ properties:
hfront-porch:
description: Horizontal front porch panel timing
$ref: /schemas/types.yaml#/definitions/uint32-array
oneOf:
- $ref: /schemas/types.yaml#/definitions/uint32
maxItems: 1
- maxItems: 1
items:
description: typical number of pixels
- $ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 3
- minItems: 3
maxItems: 3
items:
description: min, typ, max number of pixels
hback-porch:
description: Horizontal back porch timing
$ref: /schemas/types.yaml#/definitions/uint32-array
oneOf:
- $ref: /schemas/types.yaml#/definitions/uint32
maxItems: 1
- maxItems: 1
items:
description: typical number of pixels
- $ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 3
- minItems: 3
maxItems: 3
items:
description: min, typ, max number of pixels
hsync-len:
description: Horizontal sync length panel timing
$ref: /schemas/types.yaml#/definitions/uint32-array
oneOf:
- $ref: /schemas/types.yaml#/definitions/uint32
maxItems: 1
- maxItems: 1
items:
description: typical number of pixels
- $ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 3
- minItems: 3
maxItems: 3
items:
description: min, typ, max number of pixels
vfront-porch:
description: Vertical front porch panel timing
$ref: /schemas/types.yaml#/definitions/uint32-array
oneOf:
- $ref: /schemas/types.yaml#/definitions/uint32
maxItems: 1
- maxItems: 1
items:
description: typical number of lines
- $ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 3
- minItems: 3
maxItems: 3
items:
description: min, typ, max number of lines
vback-porch:
description: Vertical back porch panel timing
$ref: /schemas/types.yaml#/definitions/uint32-array
oneOf:
- $ref: /schemas/types.yaml#/definitions/uint32
maxItems: 1
- maxItems: 1
items:
description: typical number of lines
- $ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 3
- minItems: 3
maxItems: 3
items:
description: min, typ, max number of lines
vsync-len:
description: Vertical sync length panel timing
$ref: /schemas/types.yaml#/definitions/uint32-array
oneOf:
- $ref: /schemas/types.yaml#/definitions/uint32
maxItems: 1
- maxItems: 1
items:
description: typical number of lines
- $ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 3
- minItems: 3
maxItems: 3
items:
description: min, typ, max number of lines

2
Documentation/devicetree/bindings/display/samsung/samsung,exynos-hdmi-ddc.yaml
View File

@ -11,7 +11,7 @@ maintainers:
- Joonyoung Shim <jy0922.shim@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:

2
Documentation/devicetree/bindings/display/samsung/samsung,exynos-hdmi.yaml
View File

@ -11,7 +11,7 @@ maintainers:
- Joonyoung Shim <jy0922.shim@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:

2
Documentation/devicetree/bindings/display/samsung/samsung,exynos-mixer.yaml
View File

@ -11,7 +11,7 @@ maintainers:
- Joonyoung Shim <jy0922.shim@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description:
Samsung Exynos SoC Mixer is responsible for mixing and blending multiple data

2
Documentation/devicetree/bindings/display/samsung/samsung,exynos5433-decon.yaml
View File

@ -11,7 +11,7 @@ maintainers:
- Joonyoung Shim <jy0922.shim@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
DECON (Display and Enhancement Controller) is the Display Controller for the

2
Documentation/devicetree/bindings/display/samsung/samsung,exynos5433-mic.yaml
View File

@ -11,7 +11,7 @@ maintainers:
- Joonyoung Shim <jy0922.shim@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
MIC (Mobile Image Compressor) resides between DECON and MIPI DSI. MIPI DSI is

2
Documentation/devicetree/bindings/display/samsung/samsung,exynos7-decon.yaml
View File

@ -11,7 +11,7 @@ maintainers:
- Joonyoung Shim <jy0922.shim@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
DECON (Display and Enhancement Controller) is the Display Controller for the

2
Documentation/devicetree/bindings/display/samsung/samsung,fimd.yaml
View File

@ -11,7 +11,7 @@ maintainers:
- Joonyoung Shim <jy0922.shim@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:

1
Documentation/devicetree/bindings/dma/qcom,gpi.yaml
View File

@ -29,6 +29,7 @@ properties:
interrupts:
description:
Interrupt lines for each GPI instance
minItems: 1
maxItems: 13
"#dma-cells":

4
Documentation/devicetree/bindings/extcon/maxim,max77843.yaml
View File

@ -8,7 +8,7 @@ title: Maxim MAX77843 MicroUSB and Companion Power Management IC Extcon
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
This is a part of device tree bindings for Maxim MAX77843 MicroUSB
@ -25,7 +25,7 @@ properties:
$ref: /schemas/connector/usb-connector.yaml#
ports:
$ref: /schemas/graph.yaml#/properties/port
$ref: /schemas/graph.yaml#/properties/ports
description:
Any connector to the data bus of this controller should be modelled using
the OF graph bindings specified

5
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
View File

@ -20,6 +20,7 @@ properties:
- mediatek,mt8183-mali
- realtek,rtd1619-mali
- renesas,r9a07g044-mali
- renesas,r9a07g054-mali
- rockchip,px30-mali
- rockchip,rk3568-mali
- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
@ -109,7 +110,9 @@ allOf:
properties:
compatible:
contains:
const: renesas,r9a07g044-mali
enum:
- renesas,r9a07g044-mali
- renesas,r9a07g054-mali
then:
properties:
interrupts:

2
Documentation/devicetree/bindings/hwmon/lltc,ltc4151.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: LTC4151 High Voltage I2C Current and Voltage Monitor
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:

2
Documentation/devicetree/bindings/hwmon/microchip,mcp3021.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip MCP3021 A/D converter
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:

2
Documentation/devicetree/bindings/hwmon/sensirion,sht15.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sensirion SHT15 humidity and temperature sensor
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:

2
Documentation/devicetree/bindings/hwmon/ti,tmp102.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: TMP102 temperature sensor
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:

2
Documentation/devicetree/bindings/hwmon/ti,tmp108.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: TMP108 temperature sensor
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:

5
Documentation/devicetree/bindings/hwmon/ti,tmp464.yaml
View File

@ -58,9 +58,8 @@ patternProperties:
The value (two's complement) to be programmed in the channel specific N correction register.
For remote channels only.
$ref: /schemas/types.yaml#/definitions/int32
items:
minimum: -128
maximum: 127
minimum: -128
maximum: 127
required:
- reg

2
Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung's High Speed I2C controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
The Samsung's High Speed I2C controller is used to interface with I2C devices

2
Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S3C/S5P/Exynos SoC I2C Controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:

1
Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml
View File

@ -98,6 +98,7 @@ allOf:
- ti,adc121s
- ti,ads7866
- ti,ads7868
then:
required:
- vcc-supply
# Devices with a vref

12
Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
View File

@ -108,9 +108,7 @@ patternProperties:
- [1-5]: order 1 to 5.
For audio purpose it is recommended to use order 3 to 5.
$ref: /schemas/types.yaml#/definitions/uint32
items:
minimum: 0
maximum: 5
maximum: 5
"#io-channel-cells":
const: 1
@ -174,7 +172,7 @@ patternProperties:
contains:
const: st,stm32-dfsdm-adc
- then:
then:
properties:
st,adc-channels:
minItems: 1
@ -206,7 +204,7 @@ patternProperties:
contains:
const: st,stm32-dfsdm-dmic
- then:
then:
properties:
st,adc-channels:
maxItems: 1
@ -254,7 +252,7 @@ allOf:
contains:
const: st,stm32h7-dfsdm
- then:
then:
patternProperties:
"^filter@[0-9]+$":
properties:
@ -269,7 +267,7 @@ allOf:
contains:
const: st,stm32mp1-dfsdm
- then:
then:
patternProperties:
"^filter@[0-9]+$":
properties:

6
Documentation/devicetree/bindings/iio/dac/adi,ad5360.yaml
View File

@ -59,9 +59,9 @@ allOf:
contains:
enum:
- adi,ad5371
then:
required:
- vref2-supply
then:
required:
- vref2-supply
examples:
- |

70
Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml
View File

@ -93,48 +93,48 @@ allOf:
- qcom,sdm660-gnoc
- qcom,sdm660-snoc
then:
properties:
clock-names:
items:
- const: bus
- const: bus_a
then:
properties:
clock-names:
items:
- const: bus
- const: bus_a
clocks:
items:
- description: Bus Clock
- description: Bus A Clock
clocks:
items:
- description: Bus Clock
- description: Bus A Clock
# Child node's properties
patternProperties:
'^interconnect-[a-z0-9]+$':
type: object
description:
snoc-mm is a child of snoc, sharing snoc's register address space.
# Child node's properties
patternProperties:
'^interconnect-[a-z0-9]+$':
type: object
description:
snoc-mm is a child of snoc, sharing snoc's register address space.
properties:
compatible:
enum:
- qcom,msm8939-snoc-mm
properties:
compatible:
enum:
- qcom,msm8939-snoc-mm
'#interconnect-cells':
const: 1
'#interconnect-cells':
const: 1
clock-names:
items:
- const: bus
- const: bus_a
clock-names:
items:
- const: bus
- const: bus_a
clocks:
items:
- description: Bus Clock
- description: Bus A Clock
clocks:
items:
- description: Bus Clock
- description: Bus A Clock
required:
- compatible
- '#interconnect-cells'
- clock-names
- clocks
required:
- compatible
- '#interconnect-cells'
- clock-names
- clocks
- if:
properties:

6
Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.yaml
View File

@ -7,10 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell MMP/Orion Interrupt controller bindings
maintainers:
- Thomas Gleixner <tglx@linutronix.de>
- Jason Cooper <jason@lakedaemon.net>
- Marc Zyngier <maz@kernel.org>
- Rob Herring <robh+dt@kernel.org>
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
allOf:
- if:

2
Documentation/devicetree/bindings/interrupt-controller/samsung,exynos4210-combiner.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos SoC Interrupt Combiner Controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
Samsung's Exynos4 architecture includes a interrupt combiner controller which

2
Documentation/devicetree/bindings/leds/maxim,max77693.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Maxim MAX77693 MicroUSB and Companion Power Management IC LEDs
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
This is a part of device tree bindings for Maxim MAX77693 MicroUSB Integrated

1
Documentation/devicetree/bindings/media/coda.yaml
View File

@ -65,7 +65,6 @@ properties:
iram:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle pointing to the SRAM device node
maxItems: 1
required:
- compatible

2
Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml
View File

@ -63,13 +63,11 @@ properties:
mediatek,vpu:
$ref: /schemas/types.yaml#/definitions/phandle
maxItems: 1
description:
Describes point to vpu.
mediatek,scp:
$ref: /schemas/types.yaml#/definitions/phandle
maxItems: 1
description:
Describes point to scp.

3
Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
View File

@ -55,13 +55,11 @@ properties:
mediatek,vpu:
$ref: /schemas/types.yaml#/definitions/phandle
maxItems: 1
description:
Describes point to vpu.
mediatek,scp:
$ref: /schemas/types.yaml#/definitions/phandle
maxItems: 1
description:
Describes point to scp.
@ -106,7 +104,6 @@ allOf:
enum:
- mediatek,mt8173-vcodec-enc
- mediatek,mt8192-vcodec-enc
- mediatek,mt8173-vcodec-enc
then:
properties:

1
Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
View File

@ -61,7 +61,6 @@ properties:
mediatek,scp:
$ref: /schemas/types.yaml#/definitions/phandle
maxItems: 1
description: |
The node of system control processor (SCP), using
the remoteproc & rpmsg framework.

2
Documentation/devicetree/bindings/memory-controllers/brcm,dpfe-cpu.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: DDR PHY Front End (DPFE) for Broadcom STB
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Markus Mayer <mmayer@broadcom.com>
properties:

2
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:

2
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:

2
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:

2
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:

2
Documentation/devicetree/bindings/memory-controllers/marvell,mvebu-sdram-controller.yaml
View File

@ -8,7 +8,7 @@ title: Marvell MVEBU SDRAM controller
maintainers:
- Jan Luebbe <jlu@pengutronix.de>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:

2
Documentation/devicetree/bindings/memory-controllers/qca,ath79-ddr-controller.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
The DDR controller of the AR7xxx and AR9xxx families provides an interface to

2
Documentation/devicetree/bindings/memory-controllers/renesas,h8300-bsc.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: H8/300 bus controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Yoshinori Sato <ysato@users.sourceforge.jp>
properties:

2
Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml
View File

@ -9,7 +9,7 @@ title: |
Controller device
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Lukasz Luba <lukasz.luba@arm.com>
description: |

8
Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synopsys IntelliDDR Multi Protocol memory controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Manish Narani <manish.narani@xilinx.com>
- Michal Simek <michal.simek@xilinx.com>
@ -24,9 +24,9 @@ description: |
properties:
compatible:
enum:
- snps,ddrc-3.80a
- xlnx,zynq-ddrc-a05
- xlnx,zynqmp-ddrc-2.40a
- snps,ddrc-3.80a
interrupts:
maxItems: 1
@ -43,7 +43,9 @@ allOf:
properties:
compatible:
contains:
const: xlnx,zynqmp-ddrc-2.40a
enum:
- snps,ddrc-3.80a
- xlnx,zynqmp-ddrc-2.40a
then:
required:
- interrupts

2
Documentation/devicetree/bindings/memory-controllers/ti,da8xx-ddrctl.yaml
View File

@ -8,7 +8,7 @@ title: Texas Instruments da8xx DDR2/mDDR memory controller
maintainers:
- Bartosz Golaszewski <bgolaszewski@baylibre.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
Documentation:

2
Documentation/devicetree/bindings/mfd/atmel-flexcom.txt
View File

@ -54,7 +54,7 @@ flexcom@f8034000 {
clock-names = "spi_clk";
atmel,fifo-size = <32>;
mtd_dataflash@0 {
flash@0 {
compatible = "atmel,at25f512b";
reg = <0>;
spi-max-frequency = <20000000>;

2
Documentation/devicetree/bindings/mfd/maxim,max14577.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Maxim MAX14577/MAX77836 MicroUSB and Companion Power Management IC
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
This is a part of device tree bindings for Maxim MAX14577/MAX77836 MicroUSB

2
Documentation/devicetree/bindings/mfd/maxim,max77686.yaml
View File

@ -8,7 +8,7 @@ title: Maxim MAX77686 Power Management IC
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
This is a part of device tree bindings for Maxim MAX77686 Power Management

2
Documentation/devicetree/bindings/mfd/maxim,max77693.yaml
View File

@ -8,7 +8,7 @@ title: Maxim MAX77693 MicroUSB and Companion Power Management IC
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
This is a part of device tree bindings for Maxim MAX77693 MicroUSB

2
Documentation/devicetree/bindings/mfd/maxim,max77802.yaml
View File

@ -8,7 +8,7 @@ title: Maxim MAX77802 Power Management IC
maintainers:
- Javier Martinez Canillas <javier@dowhile0.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
This is a part of device tree bindings for Maxim MAX77802 Power Management

2
Documentation/devicetree/bindings/mfd/maxim,max77843.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Maxim MAX77843 MicroUSB and Companion Power Management IC
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
This is a part of device tree bindings for Maxim MAX77843 MicroUSB

2
Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos SoC Low Power Audio Subsystem (LPASS)
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
properties:

2
Documentation/devicetree/bindings/mfd/samsung,s2mpa01.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S2MPA01 Power Management IC
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
This is a part of device tree bindings for S2M and S5M family of Power

2
Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S2MPS11/13/14/15 and S2MPU02 Power Management IC
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
This is a part of device tree bindings for S2M and S5M family of Power

2
Documentation/devicetree/bindings/mfd/samsung,s5m8767.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S5M8767 Power Management IC
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
This is a part of device tree bindings for S2M and S5M family of Power

2
Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
View File

@ -197,6 +197,8 @@ allOf:
- nvidia,tegra30-sdhci
- nvidia,tegra114-sdhci
- nvidia,tegra124-sdhci
then:
properties:
clocks:
items:
- description: module clock

35
Documentation/devicetree/bindings/net/dsa/realtek.yaml
View File

@ -27,32 +27,25 @@ description:
The realtek-mdio driver is an MDIO driver and it must be inserted inside
an MDIO node.
The compatible string is only used to identify which (silicon) family the
switch belongs to. Roughly speaking, a family is any set of Realtek switches
whose chip identification register(s) have a common location and semantics.
The different models in a given family can be automatically disambiguated by
parsing the chip identification register(s) according to the given family,
avoiding the need for a unique compatible string for each model.
properties:
compatible:
enum:
- realtek,rtl8365mb
- realtek,rtl8366
- realtek,rtl8366rb
- realtek,rtl8366s
- realtek,rtl8367
- realtek,rtl8367b
- realtek,rtl8367rb
- realtek,rtl8367s
- realtek,rtl8368s
- realtek,rtl8369
- realtek,rtl8370
description: |
realtek,rtl8365mb: 4+1 ports
realtek,rtl8366: 5+1 ports
realtek,rtl8366rb: 5+1 ports
realtek,rtl8366s: 5+1 ports
realtek,rtl8367:
realtek,rtl8367b:
realtek,rtl8367rb: 5+2 ports
realtek,rtl8367s: 5+2 ports
realtek,rtl8368s: 8 ports
realtek,rtl8369: 8+1 ports
realtek,rtl8370: 8+2 ports
realtek,rtl8365mb:
Use with models RTL8363NB, RTL8363NB-VB, RTL8363SC, RTL8363SC-VB,
RTL8364NB, RTL8364NB-VB, RTL8365MB, RTL8366SC, RTL8367RB-VB, RTL8367S,
RTL8367SB, RTL8370MB, RTL8310SR
realtek,rtl8366rb:
Use with models RTL8366RB, RTL8366S
mdc-gpios:
description: GPIO line for the MDC clock line.
@ -335,7 +328,7 @@ examples:
#size-cells = <0>;
switch@29 {
compatible = "realtek,rtl8367s";
compatible = "realtek,rtl8365mb";
reg = <29>;
reset-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;

6
Documentation/devicetree/bindings/net/ethernet-controller.yaml
View File

@ -106,6 +106,12 @@ properties:
phy-mode:
$ref: "#/properties/phy-connection-type"
pcs-handle:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Specifies a reference to a node representing a PCS PHY device on a MDIO
bus to link with an external PHY (phy-handle) if exists.
phy-handle:
$ref: /schemas/types.yaml#/definitions/phandle
description:

17
Documentation/devicetree/bindings/net/micrel.txt
View File

@ -45,20 +45,3 @@ Optional properties:
In fiber mode, auto-negotiation is disabled and the PHY can only work in
100base-fx (full and half duplex) modes.
- lan8814,ignore-ts: If present the PHY will not support timestamping.
This option acts as check whether Timestamping is supported by
hardware or not. LAN8814 phy support hardware tmestamping.
- lan8814,latency_rx_10: Configures Latency value of phy in ingress at 10 Mbps.
- lan8814,latency_tx_10: Configures Latency value of phy in egress at 10 Mbps.
- lan8814,latency_rx_100: Configures Latency value of phy in ingress at 100 Mbps.
- lan8814,latency_tx_100: Configures Latency value of phy in egress at 100 Mbps.
- lan8814,latency_rx_1000: Configures Latency value of phy in ingress at 1000 Mbps.
- lan8814,latency_tx_1000: Configures Latency value of phy in egress at 1000 Mbps.

2
Documentation/devicetree/bindings/net/nfc/marvell,nci.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell International Ltd. NCI NFC controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:

2
Documentation/devicetree/bindings/net/nfc/nxp,nci.yaml
View File

@ -8,7 +8,7 @@ title: NXP Semiconductors NCI NFC controller
maintainers:
- Charles Gorand <charles.gorand@effinnov.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:

2
Documentation/devicetree/bindings/net/nfc/nxp,pn532.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP Semiconductors PN532 NFC controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:

2
Documentation/devicetree/bindings/net/nfc/nxp,pn544.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP Semiconductors PN544 NFC Controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:

2
Documentation/devicetree/bindings/net/nfc/st,st-nci.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics ST NCI NFC controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:

2
Documentation/devicetree/bindings/net/nfc/st,st21nfca.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics SAS ST21NFCA NFC controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:

2
Documentation/devicetree/bindings/net/nfc/st,st95hf.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics ST95HF NFC controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:

2
Documentation/devicetree/bindings/net/nfc/ti,trf7970a.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments TRF7970A RFID/NFC/15693 Transceiver
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Mark Greer <mgreer@animalcreek.com>
properties:

6
Documentation/devicetree/bindings/net/snps,dwmac.yaml
View File

@ -53,20 +53,18 @@ properties:
- allwinner,sun8i-r40-gmac
- allwinner,sun8i-v3s-emac
- allwinner,sun50i-a64-emac
- loongson,ls2k-dwmac
- loongson,ls7a-dwmac
- amlogic,meson6-dwmac
- amlogic,meson8b-dwmac
- amlogic,meson8m2-dwmac
- amlogic,meson-gxbb-dwmac
- amlogic,meson-axg-dwmac
- loongson,ls2k-dwmac
- loongson,ls7a-dwmac
- ingenic,jz4775-mac
- ingenic,x1000-mac
- ingenic,x1600-mac
- ingenic,x1830-mac
- ingenic,x2000-mac
- loongson,ls2k-dwmac
- loongson,ls7a-dwmac
- rockchip,px30-gmac
- rockchip,rk3128-gmac
- rockchip,rk3228-gmac

57
Documentation/devicetree/bindings/net/socionext,uniphier-ave4.yaml
View File

@ -13,9 +13,6 @@ description: |
This describes the devicetree bindings for AVE ethernet controller
implemented on Socionext UniPhier SoCs.
allOf:
- $ref: ethernet-controller.yaml#
properties:
compatible:
enum:
@ -44,25 +41,13 @@ properties:
minItems: 1
maxItems: 4
clock-names:
oneOf:
- items: # for Pro4
- const: gio
- const: ether
- const: ether-gb
- const: ether-phy
- const: ether # for others
clock-names: true
resets:
minItems: 1
maxItems: 2
reset-names:
oneOf:
- items: # for Pro4
- const: gio
- const: ether
- const: ether # for others
reset-names: true
socionext,syscon-phy-mode:
$ref: /schemas/types.yaml#/definitions/phandle-array
@ -78,6 +63,42 @@ properties:
$ref: mdio.yaml#
unevaluatedProperties: false
allOf:
- $ref: ethernet-controller.yaml#
- if:
properties:
compatible:
contains:
const: socionext,uniphier-pro4-ave4
then:
properties:
clocks:
minItems: 4
maxItems: 4
clock-names:
items:
- const: gio
- const: ether
- const: ether-gb
- const: ether-phy
resets:
minItems: 2
maxItems: 2
reset-names:
items:
- const: gio
- const: ether
else:
properties:
clocks:
maxItems: 1
clock-names:
const: ether
resets:
maxItems: 1
reset-names:
const: ether
required:
- compatible
- reg
@ -90,7 +111,7 @@ required:
- reset-names
- mdio
additionalProperties: false
unevaluatedProperties: false
examples:
- |

1
Documentation/devicetree/bindings/net/ti,davinci-mdio.yaml
View File

@ -56,6 +56,7 @@ if:
compatible:
contains:
const: ti,davinci_mdio
then:
required:
- bus_freq

8
Documentation/devicetree/bindings/net/xilinx_axienet.txt
View File

@ -26,7 +26,8 @@ Required properties:
specified, the TX/RX DMA interrupts should be on that node
instead, and only the Ethernet core interrupt is optionally
specified here.
- phy-handle : Should point to the external phy device.
- phy-handle : Should point to the external phy device if exists. Pointing
this to the PCS/PMA PHY is deprecated and should be avoided.
See ethernet.txt file in the same directory.
- xlnx,rxmem : Set to allocated memory buffer for Rx/Tx in the hardware
@ -68,6 +69,11 @@ Optional properties:
required through the core's MDIO interface (i.e. always,
unless the PHY is accessed through a different bus).
- pcs-handle: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
modes, where "pcs-handle" should be used to point
to the PCS/PMA PHY, and "phy-handle" should point to an
external PHY if exists.
Example:
axi_ethernet_eth: ethernet@40c00000 {
compatible = "xlnx,axi-ethernet-1.00.a";

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