mirror of
https://github.com/torvalds/linux.git
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drm/nouveau: move ramht code out of nouveau_object.c, nothing to see here
Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
2a7fdb2bc1
commit
479dcaea09
@ -9,7 +9,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
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nouveau_bo.o nouveau_fence.o nouveau_gem.o nouveau_ttm.o \
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nouveau_hw.o nouveau_calc.o nouveau_bios.o nouveau_i2c.o \
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nouveau_display.o nouveau_connector.o nouveau_fbcon.o \
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nouveau_dp.o \
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nouveau_dp.o nouveau_ramht.o \
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nv04_timer.o \
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nv04_mc.o nv40_mc.o nv50_mc.o \
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nv04_fb.o nv10_fb.o nv30_fb.o nv40_fb.o nv50_fb.o nvc0_fb.o \
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@ -34,6 +34,7 @@
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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#include "nouveau_ramht.h"
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/* NVidia uses context objects to drive drawing operations.
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@ -65,137 +66,6 @@
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The key into the hash table depends on the object handle and channel id and
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is given as:
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*/
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static uint32_t
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nouveau_ramht_hash_handle(struct drm_device *dev, int channel, uint32_t handle)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t hash = 0;
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int i;
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NV_DEBUG(dev, "ch%d handle=0x%08x\n", channel, handle);
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for (i = 32; i > 0; i -= dev_priv->ramht_bits) {
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hash ^= (handle & ((1 << dev_priv->ramht_bits) - 1));
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handle >>= dev_priv->ramht_bits;
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}
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if (dev_priv->card_type < NV_50)
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hash ^= channel << (dev_priv->ramht_bits - 4);
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hash <<= 3;
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NV_DEBUG(dev, "hash=0x%08x\n", hash);
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return hash;
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}
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static int
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nouveau_ramht_entry_valid(struct drm_device *dev, struct nouveau_gpuobj *ramht,
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uint32_t offset)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t ctx = nv_ro32(dev, ramht, (offset + 4)/4);
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if (dev_priv->card_type < NV_40)
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return ((ctx & NV_RAMHT_CONTEXT_VALID) != 0);
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return (ctx != 0);
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}
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static int
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nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
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struct nouveau_channel *chan = ref->channel;
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struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL;
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uint32_t ctx, co, ho;
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if (!ramht) {
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NV_ERROR(dev, "No hash table!\n");
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return -EINVAL;
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}
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if (dev_priv->card_type < NV_40) {
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ctx = NV_RAMHT_CONTEXT_VALID | (ref->instance >> 4) |
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(chan->id << NV_RAMHT_CONTEXT_CHANNEL_SHIFT) |
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(ref->gpuobj->engine << NV_RAMHT_CONTEXT_ENGINE_SHIFT);
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} else
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if (dev_priv->card_type < NV_50) {
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ctx = (ref->instance >> 4) |
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(chan->id << NV40_RAMHT_CONTEXT_CHANNEL_SHIFT) |
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(ref->gpuobj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT);
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} else {
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if (ref->gpuobj->engine == NVOBJ_ENGINE_DISPLAY) {
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ctx = (ref->instance << 10) | 2;
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} else {
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ctx = (ref->instance >> 4) |
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((ref->gpuobj->engine <<
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NV40_RAMHT_CONTEXT_ENGINE_SHIFT));
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}
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}
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co = ho = nouveau_ramht_hash_handle(dev, chan->id, ref->handle);
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do {
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if (!nouveau_ramht_entry_valid(dev, ramht, co)) {
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NV_DEBUG(dev,
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"insert ch%d 0x%08x: h=0x%08x, c=0x%08x\n",
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chan->id, co, ref->handle, ctx);
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nv_wo32(dev, ramht, (co + 0)/4, ref->handle);
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nv_wo32(dev, ramht, (co + 4)/4, ctx);
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list_add_tail(&ref->list, &chan->ramht_refs);
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instmem->flush(dev);
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return 0;
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}
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NV_DEBUG(dev, "collision ch%d 0x%08x: h=0x%08x\n",
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chan->id, co, nv_ro32(dev, ramht, co/4));
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co += 8;
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if (co >= dev_priv->ramht_size)
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co = 0;
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} while (co != ho);
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NV_ERROR(dev, "RAMHT space exhausted. ch=%d\n", chan->id);
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return -ENOMEM;
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}
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static void
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nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
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struct nouveau_channel *chan = ref->channel;
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struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL;
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uint32_t co, ho;
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if (!ramht) {
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NV_ERROR(dev, "No hash table!\n");
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return;
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}
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co = ho = nouveau_ramht_hash_handle(dev, chan->id, ref->handle);
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do {
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if (nouveau_ramht_entry_valid(dev, ramht, co) &&
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(ref->handle == nv_ro32(dev, ramht, (co/4)))) {
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NV_DEBUG(dev,
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"remove ch%d 0x%08x: h=0x%08x, c=0x%08x\n",
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chan->id, co, ref->handle,
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nv_ro32(dev, ramht, (co + 4)));
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nv_wo32(dev, ramht, (co + 0)/4, 0x00000000);
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nv_wo32(dev, ramht, (co + 4)/4, 0x00000000);
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list_del(&ref->list);
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instmem->flush(dev);
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return;
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}
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co += 8;
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if (co >= dev_priv->ramht_size)
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co = 0;
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} while (co != ho);
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list_del(&ref->list);
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NV_ERROR(dev, "RAMHT entry not found. ch=%d, handle=0x%08x\n",
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chan->id, ref->handle);
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}
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int
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nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan,
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160
drivers/gpu/drm/nouveau/nouveau_ramht.c
Normal file
160
drivers/gpu/drm/nouveau/nouveau_ramht.c
Normal file
@ -0,0 +1,160 @@
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/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_ramht.h"
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static uint32_t
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nouveau_ramht_hash_handle(struct drm_device *dev, int channel, uint32_t handle)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t hash = 0;
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int i;
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NV_DEBUG(dev, "ch%d handle=0x%08x\n", channel, handle);
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for (i = 32; i > 0; i -= dev_priv->ramht_bits) {
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hash ^= (handle & ((1 << dev_priv->ramht_bits) - 1));
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handle >>= dev_priv->ramht_bits;
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}
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if (dev_priv->card_type < NV_50)
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hash ^= channel << (dev_priv->ramht_bits - 4);
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hash <<= 3;
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NV_DEBUG(dev, "hash=0x%08x\n", hash);
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return hash;
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}
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static int
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nouveau_ramht_entry_valid(struct drm_device *dev, struct nouveau_gpuobj *ramht,
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uint32_t offset)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t ctx = nv_ro32(dev, ramht, (offset + 4)/4);
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if (dev_priv->card_type < NV_40)
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return ((ctx & NV_RAMHT_CONTEXT_VALID) != 0);
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return (ctx != 0);
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}
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int
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nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
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struct nouveau_channel *chan = ref->channel;
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struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL;
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uint32_t ctx, co, ho;
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if (!ramht) {
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NV_ERROR(dev, "No hash table!\n");
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return -EINVAL;
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}
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if (dev_priv->card_type < NV_40) {
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ctx = NV_RAMHT_CONTEXT_VALID | (ref->instance >> 4) |
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(chan->id << NV_RAMHT_CONTEXT_CHANNEL_SHIFT) |
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(ref->gpuobj->engine << NV_RAMHT_CONTEXT_ENGINE_SHIFT);
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} else
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if (dev_priv->card_type < NV_50) {
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ctx = (ref->instance >> 4) |
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(chan->id << NV40_RAMHT_CONTEXT_CHANNEL_SHIFT) |
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(ref->gpuobj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT);
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} else {
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if (ref->gpuobj->engine == NVOBJ_ENGINE_DISPLAY) {
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ctx = (ref->instance << 10) | 2;
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} else {
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ctx = (ref->instance >> 4) |
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((ref->gpuobj->engine <<
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NV40_RAMHT_CONTEXT_ENGINE_SHIFT));
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}
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}
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co = ho = nouveau_ramht_hash_handle(dev, chan->id, ref->handle);
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do {
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if (!nouveau_ramht_entry_valid(dev, ramht, co)) {
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NV_DEBUG(dev,
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"insert ch%d 0x%08x: h=0x%08x, c=0x%08x\n",
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chan->id, co, ref->handle, ctx);
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nv_wo32(dev, ramht, (co + 0)/4, ref->handle);
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nv_wo32(dev, ramht, (co + 4)/4, ctx);
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list_add_tail(&ref->list, &chan->ramht_refs);
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instmem->flush(dev);
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return 0;
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}
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NV_DEBUG(dev, "collision ch%d 0x%08x: h=0x%08x\n",
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chan->id, co, nv_ro32(dev, ramht, co/4));
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co += 8;
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if (co >= dev_priv->ramht_size)
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co = 0;
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} while (co != ho);
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NV_ERROR(dev, "RAMHT space exhausted. ch=%d\n", chan->id);
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return -ENOMEM;
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}
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void
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nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
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struct nouveau_channel *chan = ref->channel;
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struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL;
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uint32_t co, ho;
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if (!ramht) {
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NV_ERROR(dev, "No hash table!\n");
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return;
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}
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co = ho = nouveau_ramht_hash_handle(dev, chan->id, ref->handle);
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do {
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if (nouveau_ramht_entry_valid(dev, ramht, co) &&
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(ref->handle == nv_ro32(dev, ramht, (co/4)))) {
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NV_DEBUG(dev,
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"remove ch%d 0x%08x: h=0x%08x, c=0x%08x\n",
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chan->id, co, ref->handle,
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nv_ro32(dev, ramht, (co + 4)));
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nv_wo32(dev, ramht, (co + 0)/4, 0x00000000);
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nv_wo32(dev, ramht, (co + 4)/4, 0x00000000);
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list_del(&ref->list);
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instmem->flush(dev);
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return;
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}
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co += 8;
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if (co >= dev_priv->ramht_size)
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co = 0;
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} while (co != ho);
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list_del(&ref->list);
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NV_ERROR(dev, "RAMHT entry not found. ch=%d, handle=0x%08x\n",
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chan->id, ref->handle);
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}
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31
drivers/gpu/drm/nouveau/nouveau_ramht.h
Normal file
31
drivers/gpu/drm/nouveau/nouveau_ramht.h
Normal file
@ -0,0 +1,31 @@
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/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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||||
*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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||||
*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#ifndef __NOUVEAU_RAMHT_H__
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#define __NOUVEAU_RAMHT_H__
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extern int nouveau_ramht_insert(struct drm_device *, struct nouveau_gpuobj_ref *);
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extern void nouveau_ramht_remove(struct drm_device *, struct nouveau_gpuobj_ref *);
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#endif
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Reference in New Issue
Block a user