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ARC: Support for high priority interrupts in the in-core intc
There is a bit of hack/kludge right now where we disable preemption if a L2 (High prio) IRQ is taken while L1 (Low prio) is active. Need to revisit this Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta
parent
769bc1fd7b
commit
4788a5942b
@ -208,6 +208,25 @@ config ARC_PAGE_SIZE_4K
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endchoice
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config ARC_COMPACT_IRQ_LEVELS
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bool "ARCompact IRQ Priorities: High(2)/Low(1)"
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default n
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# Timer HAS to be high priority, for any other high priority config
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select ARC_IRQ3_LV2
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if ARC_COMPACT_IRQ_LEVELS
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config ARC_IRQ3_LV2
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bool
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config ARC_IRQ5_LV2
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bool
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config ARC_IRQ6_LV2
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bool
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endif
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config ARC_FPU_SAVE_RESTORE
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bool "Enable FPU state persistence across context switch"
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default n
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@ -5,6 +5,12 @@
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Vineetg: March 2009 (Supporting 2 levels of Interrupts)
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* Stack switching code can no longer reliably rely on the fact that
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* if we are NOT in user mode, stack is switched to kernel mode.
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* e.g. L2 IRQ interrupted a L1 ISR which had not yet completed
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* it's prologue including stack switching from user mode
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*
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* Vineetg: Aug 28th 2008: Bug #94984
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* -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
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* Normally CPU does this automatically, however when doing FAKE rtie,
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@ -268,6 +274,33 @@
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* assume SP is kernel mode SP. _NO_ need to do any stack switching
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*/
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#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
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/* However....
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* If Level 2 Interrupts enabled, we may end up with a corner case:
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* 1. User Task executing
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* 2. L1 IRQ taken, ISR starts (CPU auto-switched to KERNEL mode)
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* 3. But before it could switch SP from USER to KERNEL stack
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* a L2 IRQ "Interrupts" L1
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* Thay way although L2 IRQ happened in Kernel mode, stack is still
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* not switched.
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* To handle this, we may need to switch stack even if in kernel mode
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* provided SP has values in range of USER mode stack ( < 0x7000_0000 )
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*/
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brlo sp, VMALLOC_START, 88f
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/* TODO: vineetg:
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* We need to be a bit more cautious here. What if a kernel bug in
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* L1 ISR, caused SP to go whaco (some small value which looks like
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* USER stk) and then we take L2 ISR.
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* Above brlo alone would treat it as a valid L1-L2 sceanrio
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* instead of shouting alound
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* The only feasible way is to make sure this L2 happened in
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* L1 prelogue ONLY i.e. ilink2 is less than a pre-set marker in
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* L1 ISR before it switches stack
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*/
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#endif
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/* Save Pre Intr/Exception KERNEL MODE SP on kernel stack
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* safe-keeping not really needed, but it keeps the epilogue code
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* (SP restore) simpler/uniform.
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@ -503,6 +536,42 @@
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sub sp, sp, 4
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.endm
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.macro SAVE_ALL_INT2
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/* TODO-vineetg: SMP we can't use global nor can we use
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* SCRATCH0 as we do for int1 because while int1 is using
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* it, int2 can come
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*/
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/* retsore original r9 , saved in sys_saved_r9 */
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ld r9, [@int2_saved_reg]
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/* now we are ready to save the remaining context :) */
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st orig_r8_IS_IRQ2, [sp, 8] /* Event Type */
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st 0, [sp, 4] /* orig_r0 , N/A for IRQ */
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SAVE_CALLER_SAVED
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st.a r26, [sp, -4] /* gp */
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st.a fp, [sp, -4]
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st.a blink, [sp, -4]
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st.a ilink2, [sp, -4]
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lr r9, [status32_l2]
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st.a r9, [sp, -4]
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st.a lp_count, [sp, -4]
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lr r9, [lp_end]
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st.a r9, [sp, -4]
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lr r9, [lp_start]
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st.a r9, [sp, -4]
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lr r9, [bta_l2]
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st.a r9, [sp, -4]
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#ifdef PT_REGS_CANARY
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mov r9, 0xdeadbee2
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st r9, [sp, -4]
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#endif
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/* move up by 1 word to "create" pt_regs->"stack_place_holder" */
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sub sp, sp, 4
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.endm
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/*--------------------------------------------------------------
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* Restore all registers used by interrupt handlers.
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*
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@ -537,6 +606,32 @@
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/* orig_r0 and orig_r8 skipped automatically */
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.endm
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.macro RESTORE_ALL_INT2
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add sp, sp, 4 /* hop over unused "pt_regs->stack_place_holder" */
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ld.ab r9, [sp, 4]
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sr r9, [bta_l2]
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ld.ab r9, [sp, 4]
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sr r9, [lp_start]
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ld.ab r9, [sp, 4]
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sr r9, [lp_end]
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ld.ab r9, [sp, 4]
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mov lp_count, r9
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ld.ab r9, [sp, 4]
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sr r9, [status32_l2]
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ld.ab r9, [sp, 4]
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mov ilink2, r9
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ld.ab blink, [sp, 4]
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ld.ab fp, [sp, 4]
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ld.ab r26, [sp, 4] /* gp */
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RESTORE_CALLER_SAVED
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ld sp, [sp] /* restore original sp */
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/* orig_r0 and orig_r8 skipped automatically */
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.endm
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/* Get CPU-ID of this core */
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.macro GET_CPU_ID reg
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lr \reg, [identity]
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@ -95,7 +95,11 @@ static inline long arch_local_save_flags(void)
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*/
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static inline int arch_irqs_disabled_flags(unsigned long flags)
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{
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return !(flags & (STATUS_E1_MASK));
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return !(flags & (STATUS_E1_MASK
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#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
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| STATUS_E2_MASK
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#endif
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));
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}
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static inline int arch_irqs_disabled(void)
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@ -31,6 +31,8 @@
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* exception. Thus FAKE RTIE needed in low level Priv-Violation handler.
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* Instr Error could also cause similar scenario, so same there as well.
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*
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* Vineetg: March 2009 (Supporting 2 levels of Interrupts)
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*
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* Vineetg: Aug 28th 2008: Bug #94984
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* -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
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* Normally CPU does this automatically, however when doing FAKE rtie,
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@ -96,13 +98,25 @@ VECTOR mem_service ; 0x8, Mem exception (0x1)
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VECTOR instr_service ; 0x10, Instrn Error (0x2)
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; ******************** Device ISRs **********************
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#ifdef CONFIG_ARC_IRQ3_LV2
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VECTOR handle_interrupt_level2
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#else
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VECTOR handle_interrupt_level1
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#endif
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VECTOR handle_interrupt_level1
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#ifdef CONFIG_ARC_IRQ5_LV2
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VECTOR handle_interrupt_level2
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#else
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VECTOR handle_interrupt_level1
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#endif
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#ifdef CONFIG_ARC_IRQ6_LV2
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VECTOR handle_interrupt_level2
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#else
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VECTOR handle_interrupt_level1
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#endif
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.rept 25
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VECTOR handle_interrupt_level1 ; Other devices
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@ -139,6 +153,17 @@ VECTOR reserved ; Reserved Exceptions
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int1_saved_reg:
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.zero 4
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/* Each Interrupt level needs it's own scratch */
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#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
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.section .data ; NOT .global
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.type int2_saved_reg, @object
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.size int2_saved_reg, 4
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int2_saved_reg:
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.zero 4
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#endif
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; ---------------------------------------------
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.section .text, "ax",@progbits
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@ -152,6 +177,55 @@ reserved: ; processor restart
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;##################### Interrupt Handling ##############################
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#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
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; ---------------------------------------------
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; Level 2 ISR: Can interrupt a Level 1 ISR
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; ---------------------------------------------
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ARC_ENTRY handle_interrupt_level2
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; TODO-vineetg for SMP this wont work
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; free up r9 as scratchpad
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st r9, [@int2_saved_reg]
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;Which mode (user/kernel) was the system in when intr occured
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lr r9, [status32_l2]
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SWITCH_TO_KERNEL_STK
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SAVE_ALL_INT2
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;------------------------------------------------------
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; if L2 IRQ interrupted a L1 ISR, disable preemption
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;------------------------------------------------------
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ld r9, [sp, PT_status32] ; get statu32_l2 (saved in pt_regs)
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bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
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; A1 is set in status32_l2
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; bump thread_info->preempt_count (Disable preemption)
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GET_CURR_THR_INFO_FROM_SP r10
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ld r9, [r10, THREAD_INFO_PREEMPT_COUNT]
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add r9, r9, 1
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st r9, [r10, THREAD_INFO_PREEMPT_COUNT]
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1:
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;------------------------------------------------------
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; setup params for Linux common ISR and invoke it
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;------------------------------------------------------
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lr r0, [icause2]
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and r0, r0, 0x1f
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bl.d @arch_do_IRQ
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mov r1, sp
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mov r8,0x2
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sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg
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b ret_from_exception
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ARC_EXIT handle_interrupt_level2
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#endif
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; ---------------------------------------------
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; Level 1 ISR
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; ---------------------------------------------
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@ -619,6 +693,49 @@ restore_regs :
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not_exception:
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#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
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bbit0 r10, STATUS_A2_BIT, not_level2_interrupt
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;------------------------------------------------------------------
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; if L2 IRQ interrupted a L1 ISR, we'd disbaled preemption earlier
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; so that sched doesnt move to new task, causing L1 to be delayed
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; undeterministically. Now that we've achieved that, lets reset
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; things to what they were, before returning from L2 context
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;----------------------------------------------------------------
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ld r9, [sp, PT_orig_r8] ; get orig_r8 to make sure it is
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brne r9, orig_r8_IS_IRQ2, 149f ; infact a L2 ISR ret path
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ld r9, [sp, PT_status32] ; get statu32_l2 (saved in pt_regs)
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bbit0 r9, STATUS_A1_BIT, 149f ; L1 not active when L2 IRQ, so normal
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; A1 is set in status32_l2
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; decrement thread_info->preempt_count (re-enable preemption)
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GET_CURR_THR_INFO_FROM_SP r10
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ld r9, [r10, THREAD_INFO_PREEMPT_COUNT]
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; paranoid check, given A1 was active when A2 happened, preempt count
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; must not be 0 beccause we would have incremented it.
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; If this does happen we simply HALT as it means a BUG !!!
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cmp r9, 0
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bnz 2f
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flag 1
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2:
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sub r9, r9, 1
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st r9, [r10, THREAD_INFO_PREEMPT_COUNT]
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149:
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;return from level 2
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RESTORE_ALL_INT2
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debug_marker_l2:
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rtie
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not_level2_interrupt:
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#endif
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bbit0 r10, STATUS_A1_BIT, not_level1_interrupt
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;return from level 1
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@ -23,15 +23,32 @@
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* what it does ?
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* -setup Vector Table Base Reg - in case Linux not linked at 0x8000_0000
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* -Disable all IRQs (on CPU side)
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* -Optionally, setup the High priority Interrupts as Level 2 IRQs
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*/
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void __init arc_init_IRQ(void)
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{
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int level_mask = level_mask;
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int level_mask = 0;
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write_aux_reg(AUX_INTR_VEC_BASE, _int_vec_base_lds);
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/* Disable all IRQs: enable them as devices request */
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write_aux_reg(AUX_IENABLE, 0);
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/* setup any high priority Interrupts (Level2 in ARCompact jargon) */
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#ifdef CONFIG_ARC_IRQ3_LV2
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level_mask |= (1 << 3);
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#endif
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#ifdef CONFIG_ARC_IRQ5_LV2
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level_mask |= (1 << 5);
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#endif
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#ifdef CONFIG_ARC_IRQ6_LV2
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level_mask |= (1 << 6);
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#endif
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if (level_mask) {
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pr_info("Level-2 interrupts bitset %x\n", level_mask);
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write_aux_reg(AUX_IRQ_LEV, level_mask);
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}
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}
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/*
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@ -141,6 +158,90 @@ int __init get_hw_config_num_irq(void)
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return 0;
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}
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/*
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* arch_local_irq_enable - Enable interrupts.
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*
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* 1. Explicitly called to re-enable interrupts
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* 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc
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* which maybe in hard ISR itself
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*
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* Semantics of this function change depending on where it is called from:
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*
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* -If called from hard-ISR, it must not invert interrupt priorities
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* e.g. suppose TIMER is high priority (Level 2) IRQ
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* Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times.
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* Here local_irq_enable( ) shd not re-enable lower priority interrupts
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* -If called from soft-ISR, it must re-enable all interrupts
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* soft ISR are low prioity jobs which can be very slow, thus all IRQs
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* must be enabled while they run.
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* Now hardware context wise we may still be in L2 ISR (not done rtie)
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* still we must re-enable both L1 and L2 IRQs
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* Another twist is prev scenario with flow being
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* L1 ISR ==> interrupted by L2 ISR ==> L2 soft ISR
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* here we must not re-enable Ll as prev Ll Interrupt's h/w context will get
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* over-written (this is deficiency in ARC700 Interrupt mechanism)
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*/
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#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS /* Complex version for 2 IRQ levels */
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void arch_local_irq_enable(void)
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{
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unsigned long flags;
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flags = arch_local_save_flags();
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/* Allow both L1 and L2 at the onset */
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flags |= (STATUS_E1_MASK | STATUS_E2_MASK);
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/* Called from hard ISR (between irq_enter and irq_exit) */
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if (in_irq()) {
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/* If in L2 ISR, don't re-enable any further IRQs as this can
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* cause IRQ priorities to get upside down. e.g. it could allow
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* L1 be taken while in L2 hard ISR which is wrong not only in
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* theory, it can also cause the dreaded L1-L2-L1 scenario
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*/
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if (flags & STATUS_A2_MASK)
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flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK);
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/* Even if in L1 ISR, allowe Higher prio L2 IRQs */
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else if (flags & STATUS_A1_MASK)
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flags &= ~(STATUS_E1_MASK);
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}
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/* called from soft IRQ, ideally we want to re-enable all levels */
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else if (in_softirq()) {
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/* However if this is case of L1 interrupted by L2,
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* re-enabling both may cause whaco L1-L2-L1 scenario
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* because ARC700 allows level 1 to interrupt an active L2 ISR
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* Thus we disable both
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* However some code, executing in soft ISR wants some IRQs
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* to be enabled so we re-enable L2 only
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*
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* How do we determine L1 intr by L2
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* -A2 is set (means in L2 ISR)
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* -E1 is set in this ISR's pt_regs->status32 which is
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* saved copy of status32_l2 when l2 ISR happened
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*/
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struct pt_regs *pt = get_irq_regs();
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if ((flags & STATUS_A2_MASK) && pt &&
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(pt->status32 & STATUS_A1_MASK)) {
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/*flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK); */
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flags &= ~(STATUS_E1_MASK);
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}
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}
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arch_local_irq_restore(flags);
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}
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#else /* ! CONFIG_ARC_COMPACT_IRQ_LEVELS */
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/*
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* Simpler version for only 1 level of interrupt
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* Here we only Worry about Level 1 Bits
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*/
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void arch_local_irq_enable(void)
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{
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unsigned long flags;
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@ -158,4 +259,5 @@ void arch_local_irq_enable(void)
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flags |= (STATUS_E1_MASK | STATUS_E2_MASK);
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arch_local_irq_restore(flags);
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}
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#endif
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EXPORT_SYMBOL(arch_local_irq_enable);
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