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mtd: nand/fsmc: Add DMA support
The fsmc_nand driver uses cpu to read/write onto the device. This is inefficient because of two reasons - the cpu gets locked on AHB bus while reading from NAND - the cpu is unnecessarily used when dma can do the job This patch adds the support for accessing the device through DMA Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Reviewed-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Vipin Kumar
David Woodhouse
parent
604e75444f
commit
4774fb0a48
@ -17,6 +17,10 @@
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*/
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-direction.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/module.h>
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@ -282,6 +286,11 @@ static struct fsmc_eccplace fsmc_ecc4_sp_place = {
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* @bank: Bank number for probed device.
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* @clk: Clock structure for FSMC.
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*
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* @read_dma_chan: DMA channel for read access
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* @write_dma_chan: DMA channel for write access to NAND
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* @dma_access_complete: Completion structure
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*
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* @data_pa: NAND Physical port for Data.
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* @data_va: NAND port for Data.
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* @cmd_va: NAND port for Command.
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* @addr_va: NAND port for Address.
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@ -297,10 +306,17 @@ struct fsmc_nand_data {
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struct fsmc_eccplace *ecc_place;
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unsigned int bank;
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struct device *dev;
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enum access_mode mode;
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struct clk *clk;
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/* DMA related objects */
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struct dma_chan *read_dma_chan;
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struct dma_chan *write_dma_chan;
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struct completion dma_access_complete;
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struct fsmc_nand_timings *dev_timings;
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dma_addr_t data_pa;
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void __iomem *data_va;
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void __iomem *cmd_va;
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void __iomem *addr_va;
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@ -523,6 +539,77 @@ static int count_written_bits(uint8_t *buff, int size, int max_bits)
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return written_bits;
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}
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static void dma_complete(void *param)
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{
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struct fsmc_nand_data *host = param;
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complete(&host->dma_access_complete);
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}
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static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
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enum dma_data_direction direction)
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{
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struct dma_chan *chan;
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struct dma_device *dma_dev;
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struct dma_async_tx_descriptor *tx;
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dma_addr_t dma_dst, dma_src, dma_addr;
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dma_cookie_t cookie;
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unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
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int ret;
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if (direction == DMA_TO_DEVICE)
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chan = host->write_dma_chan;
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else if (direction == DMA_FROM_DEVICE)
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chan = host->read_dma_chan;
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else
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return -EINVAL;
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dma_dev = chan->device;
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dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
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if (direction == DMA_TO_DEVICE) {
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dma_src = dma_addr;
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dma_dst = host->data_pa;
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flags |= DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_SKIP_DEST_UNMAP;
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} else {
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dma_src = host->data_pa;
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dma_dst = dma_addr;
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flags |= DMA_COMPL_DEST_UNMAP_SINGLE | DMA_COMPL_SKIP_SRC_UNMAP;
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}
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tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
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len, flags);
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if (!tx) {
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dev_err(host->dev, "device_prep_dma_memcpy error\n");
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dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
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return -EIO;
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}
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tx->callback = dma_complete;
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tx->callback_param = host;
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cookie = tx->tx_submit(tx);
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ret = dma_submit_error(cookie);
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if (ret) {
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dev_err(host->dev, "dma_submit_error %d\n", cookie);
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return ret;
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}
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dma_async_issue_pending(chan);
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ret =
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wait_for_completion_interruptible_timeout(&host->dma_access_complete,
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msecs_to_jiffies(3000));
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if (ret <= 0) {
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chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
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dev_err(host->dev, "wait_for_completion_timeout\n");
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return ret ? ret : -ETIMEDOUT;
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}
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return 0;
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}
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/*
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* fsmc_write_buf - write buffer to chip
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* @mtd: MTD device structure
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@ -569,6 +656,35 @@ static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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}
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}
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/*
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* fsmc_read_buf_dma - read chip data into buffer
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* @mtd: MTD device structure
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* @buf: buffer to store date
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* @len: number of bytes to read
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*/
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static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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struct fsmc_nand_data *host;
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host = container_of(mtd, struct fsmc_nand_data, mtd);
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dma_xfer(host, buf, len, DMA_FROM_DEVICE);
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}
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/*
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* fsmc_write_buf_dma - write buffer to chip
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* @mtd: MTD device structure
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* @buf: data buffer
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* @len: number of bytes to write
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*/
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static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
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int len)
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{
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struct fsmc_nand_data *host;
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host = container_of(mtd, struct fsmc_nand_data, mtd);
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dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
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}
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/*
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* fsmc_read_page_hwecc
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* @mtd: mtd info structure
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@ -731,6 +847,12 @@ static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
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return i;
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}
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static bool filter(struct dma_chan *chan, void *slave)
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{
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chan->private = slave;
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return true;
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}
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/*
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* fsmc_nand_probe - Probe function
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* @pdev: platform device structure
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@ -743,6 +865,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
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struct nand_chip *nand;
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struct fsmc_regs *regs;
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struct resource *res;
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dma_cap_mask_t mask;
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int ret = 0;
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u32 pid;
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int i;
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@ -769,6 +892,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
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return -ENOENT;
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}
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host->data_pa = (dma_addr_t)res->start;
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host->data_va = devm_ioremap(&pdev->dev, res->start,
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resource_size(res));
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if (!host->data_va) {
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@ -847,6 +971,11 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
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host->nr_partitions = pdata->nr_partitions;
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host->dev = &pdev->dev;
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host->dev_timings = pdata->nand_timings;
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host->mode = pdata->mode;
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if (host->mode == USE_DMA_ACCESS)
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init_completion(&host->dma_access_complete);
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regs = host->regs_va;
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/* Link all private pointers */
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@ -871,13 +1000,31 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
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if (pdata->width == FSMC_NAND_BW16)
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nand->options |= NAND_BUSWIDTH_16;
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/*
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* use customized (word by word) version of read_buf, write_buf if
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* access_with_dev_width is reset supported
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*/
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if (pdata->mode == USE_WORD_ACCESS) {
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switch (host->mode) {
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case USE_DMA_ACCESS:
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dma_cap_zero(mask);
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dma_cap_set(DMA_MEMCPY, mask);
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host->read_dma_chan = dma_request_channel(mask, filter,
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pdata->read_dma_priv);
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if (!host->read_dma_chan) {
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dev_err(&pdev->dev, "Unable to get read dma channel\n");
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goto err_req_read_chnl;
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}
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host->write_dma_chan = dma_request_channel(mask, filter,
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pdata->write_dma_priv);
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if (!host->write_dma_chan) {
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dev_err(&pdev->dev, "Unable to get write dma channel\n");
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goto err_req_write_chnl;
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}
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nand->read_buf = fsmc_read_buf_dma;
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nand->write_buf = fsmc_write_buf_dma;
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break;
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default:
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case USE_WORD_ACCESS:
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nand->read_buf = fsmc_read_buf;
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nand->write_buf = fsmc_write_buf;
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break;
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}
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fsmc_nand_setup(regs, host->bank, nand->options & NAND_BUSWIDTH_16,
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@ -978,6 +1125,12 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
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err_probe:
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err_scan_ident:
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if (host->mode == USE_DMA_ACCESS)
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dma_release_channel(host->write_dma_chan);
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err_req_write_chnl:
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if (host->mode == USE_DMA_ACCESS)
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dma_release_channel(host->read_dma_chan);
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err_req_read_chnl:
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clk_disable(host->clk);
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err_clk_enable:
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clk_put(host->clk);
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@ -995,6 +1148,11 @@ static int fsmc_nand_remove(struct platform_device *pdev)
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if (host) {
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nand_release(&host->mtd);
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if (host->mode == USE_DMA_ACCESS) {
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dma_release_channel(host->write_dma_chan);
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dma_release_channel(host->read_dma_chan);
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}
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clk_disable(host->clk);
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clk_put(host->clk);
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}
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@ -172,6 +172,10 @@ struct fsmc_nand_platform_data {
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enum access_mode mode;
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void (*select_bank)(uint32_t bank, uint32_t busw);
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/* priv structures for dma accesses */
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void *read_dma_priv;
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void *write_dma_priv;
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};
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extern int __init fsmc_nor_init(struct platform_device *pdev,
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