Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-12-25 20:32:22 +00:00
Code Issues Packages Projects Releases Wiki Activity

i.MX device tree update for 4.20:

Browse Source 
- New board support: Engicam's i.Core MX6 CPU module v1.5; ConnectCore
    6UL Single Board Computer (SBC) Pro; i.MX6 ULZ based EVK board.
  - Add Add SFF interface support for vf610-zii board.
  - Disable unneeded devices like VPU and internal watchdog for imx51-zii
    boards.
  - Add 'no-sdio' and 'no-sd' property for vf610-zii-cfu1 board.
  - Improve i.MX6 SLL GPIO support by adding gpio-ranges property and
    clocks information.
  - Update iomux header for i.MX7 Solo and i.MX6 ULL.
  - Enable GPIO buttons as wakeup source for imx7d-sdb and imx6sx-sdb.
  - Add GPIO keys and egalax touch screen support for imx6qdl-sabreauto.
  - Switch to use SPDX-License-Identifier for more boards - vf610-twr,
    imx7s-warp, Engicam boards.
  - Add device tree bindings of 'fsl,pmic-stby-poweroff' property and add
    the support for i.MX6 RIoTboard.
  - DTC has new checks for SPI buses which will be landed on 4.20.
    A patch from Rob to fix those 100+ warnings on i.MX boards. (Thanks!)
  - Switch i.MX7 device tree to use updated coresight binding for
    hardware ports.
  - Misc small or random update and cleanup.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJbsb9RAAoJEFBXWFqHsHzObO8H/Al83K27UxL8XjKMOUsMooWX
 BG5FfS9mDKOe8bN0BwZnUmrjuOOkNWooMxyahBXP9e0CWZnK/4G3OvTS83PNpA34
 zE+Nm1oJia9zoUsWoCpBrvLrBJpjJqVajQiXzddUDgYLhbNXPXkiwBBEZqrwAJBK
 CsgwRCj4qJA1WCetvwjYVVwtcVTCCnYcpx73YQMLK1sSbi0oVqtSMynSF3spzDVC
 iduF+ur88lkjo0IK1PaWMOi8+G6E5bOV//4JJky5hNcTuMsmAAywmUEALoIYQjLr
 EitPoTNi2FDnFDpGPqvsf51Cez6e+3iCAk0F5V6D+6nIvNDF9mGRdyqSnDhIyBY=
 =B0Zy
 -----END PGP SIGNATURE-----

Merge tag 'imx-dt-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt

i.MX device tree update for 4.20:
 - New board support: Engicam's i.Core MX6 CPU module v1.5; ConnectCore
   6UL Single Board Computer (SBC) Pro; i.MX6 ULZ based EVK board.
 - Add Add SFF interface support for vf610-zii board.
 - Disable unneeded devices like VPU and internal watchdog for imx51-zii
   boards.
 - Add 'no-sdio' and 'no-sd' property for vf610-zii-cfu1 board.
 - Improve i.MX6 SLL GPIO support by adding gpio-ranges property and
   clocks information.
 - Update iomux header for i.MX7 Solo and i.MX6 ULL.
 - Enable GPIO buttons as wakeup source for imx7d-sdb and imx6sx-sdb.
 - Add GPIO keys and egalax touch screen support for imx6qdl-sabreauto.
 - Switch to use SPDX-License-Identifier for more boards - vf610-twr,
   imx7s-warp, Engicam boards.
 - Add device tree bindings of 'fsl,pmic-stby-poweroff' property and add
   the support for i.MX6 RIoTboard.
 - DTC has new checks for SPI buses which will be landed on 4.20.
   A patch from Rob to fix those 100+ warnings on i.MX boards. (Thanks!)
 - Switch i.MX7 device tree to use updated coresight binding for
   hardware ports.
 - Misc small or random update and cleanup.

* tag 'imx-dt-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (50 commits)
  ARM: dts: imx: add i.mx6ulz and i.mx6ulz 14x14 evk support
  dt-bindings: arm: add compatible for i.MX6ULZ 14x14 EVK board
  ARM: dts: imx53-ppd: Remove 'num-chipselects' property
  ARM: dts: vf610-twr: Switch to SPDX identifier
  ARM: dts: vf: Switch to SPDX identifier
  ARM: dts: imx6qdl-zii-rdu2: Disable the internal RTC
  ARM: dts: imx51-zii-rdu1: Fix the rtc compatible string
  ARM: dts: imx6ul: use nvmem-cells for cpu speed grading
  ARM: dts: imx: Fix SPI bus warnings
  ARM: dts: imx7: Update coresight binding for hardware ports
  ARM: dts: vf610-zii-cfu1: Pass the 'no-sd' property
  ARM: dts: vf610-zii-cfu1: Pass the 'no-sdio' property
  ARM: dts: imx51-zii-scu2-mezz: Disable the internal watchdog
  ARM: dts: imx51-zii-scu2-mezz: Disable VPU
  ARM: dts: imx51-zii-scu3-esb: Disable VPU
  ARM: dts: imx51: Add label for VPU node
  ARM: dts: imx6ull: update vdd_soc voltage for 900MHz operating point
  ARM: dts: imx6ul: Add DTS for ConnectCore 6UL SBC Pro
  ARM: dts: imx6: RIoTboard provide standby on power off option
  dt-bindings: imx6q-clock: add new fsl,pmic-stby-poweroff property
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2018-10-02 11:36:53 +02:00
commit 476ca77f0f
87 changed files with 1081 additions and 889 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
Documentation/devicetree/bindings/arm/fsl.txt
View File

@ -57,6 +57,50 @@ i.MX6SLL EVK board
Required root node properties:
- compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
i.MX6 Quad Plus SABRE Smart Device Board
Required root node properties:
- compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
i.MX6 Quad Plus SABRE Automotive Board
Required root node properties:
- compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp";
i.MX6 DualLite SABRE Smart Device Board
Required root node properties:
- compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
i.MX6 DualLite/Solo SABRE Automotive Board
Required root node properties:
- compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
i.MX6 SoloLite EVK Board
Required root node properties:
- compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
i.MX6 UltraLite 14x14 EVK Board
Required root node properties:
- compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
i.MX6 UltraLiteLite 14x14 EVK Board
Required root node properties:
- compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
i.MX6 ULZ 14x14 EVK Board
Required root node properties:
- compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull", "fsl,imx6ulz";
i.MX6 SoloX SDB Board
Required root node properties:
- compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
i.MX6 SoloX Sabre Auto Board
Required root node properties:
- compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
i.MX7 SabreSD Board
Required root node properties:
- compatible = "fsl,imx7d-sdb", "fsl,imx7d";
Generic i.MX boards
-------------------

8
Documentation/devicetree/bindings/clock/imx6q-clock.txt
View File

@ -6,6 +6,14 @@ Required properties:
- interrupts: Should contain CCM interrupt
- #clock-cells: Should be <1>
Optional properties:
- fsl,pmic-stby-poweroff: Configure CCM to assert PMIC_STBY_REQ signal
on power off.
Use this property if the SoC should be powered off by external power
management IC (PMIC) triggered via PMIC_STBY_REQ signal.
Boards that are designed to initiate poweroff on PMIC_ON_REQ signal should
be using "syscon-poweroff" driver instead.
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h
for the full list of i.MX6 Quad and DualLite clock IDs.

4
arch/arm/boot/dts/Makefile
View File

@ -550,6 +550,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-14x14-evk.dtb \
imx6ul-ccimx6ulsbcexpress.dtb \
imx6ul-ccimx6ulsbcpro.dtb \
imx6ul-geam.dtb \
imx6ul-isiot-emmc.dtb \
imx6ul-isiot-nand.dtb \
@ -561,7 +562,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-tx6ul-mainboard.dtb \
imx6ull-14x14-evk.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-wifi-eval-v3.dtb
imx6ull-colibri-wifi-eval-v3.dtb \
imx6ulz-14x14-evk.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
imx7d-colibri-emmc-eval-v3.dtb \

4
arch/arm/boot/dts/imx1.dtsi
View File

@ -164,7 +164,7 @@
reg = <0x00210000 0x10000>;
ranges;
cspi1: cspi@213000 {
cspi1: spi@213000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx1-cspi";
@ -186,7 +186,7 @@
status = "disabled";
};
cspi2: cspi@219000 {
cspi2: spi@219000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx1-cspi";

2
arch/arm/boot/dts/imx23-evk.dts
View File

@ -58,7 +58,7 @@
status = "okay";
};
ssp0: ssp@80010000 {
ssp0: spi@80010000 {
compatible = "fsl,imx23-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;

4
arch/arm/boot/dts/imx23-olinuxino.dts
View File

@ -25,7 +25,7 @@
apb@80000000 {
apbh@80000000 {
ssp0: ssp@80010000 {
ssp0: spi@80010000 {
compatible = "fsl,imx23-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
@ -59,7 +59,7 @@
};
};
ssp1: ssp@80034000 {
ssp1: spi@80034000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx23-spi";

4
arch/arm/boot/dts/imx23-sansa.dts
View File

@ -55,7 +55,7 @@
apb@80000000 {
apbh@80000000 {
ssp0: ssp@80010000 {
ssp0: spi@80010000 {
compatible = "fsl,imx23-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
@ -65,7 +65,7 @@
status = "okay";
};
ssp1: ssp@80034000 {
ssp1: spi@80034000 {
compatible = "fsl,imx23-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc1_8bit_pins_a>;

2
arch/arm/boot/dts/imx23-stmp378x_devb.dts
View File

@ -22,7 +22,7 @@
apb@80000000 {
apbh@80000000 {
ssp0: ssp@80010000 {
ssp0: spi@80010000 {
compatible = "fsl,imx23-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;

4
arch/arm/boot/dts/imx23-xfi3.dts
View File

@ -54,7 +54,7 @@
apb@80000000 {
apbh@80000000 {
ssp0: ssp@80010000 {
ssp0: spi@80010000 {
compatible = "fsl,imx23-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
@ -64,7 +64,7 @@
status = "okay";
};
ssp1: ssp@80034000 {
ssp1: spi@80034000 {
compatible = "fsl,imx23-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc1_4bit_pins_a>;

4
arch/arm/boot/dts/imx23.dtsi
View File

@ -93,7 +93,7 @@
status = "disabled";
};
ssp0: ssp@80010000 {
ssp0: spi@80010000 {
reg = <0x80010000 0x2000>;
interrupts = <15>;
clocks = <&clks 33>;
@ -457,7 +457,7 @@
status = "disabled";
};
ssp1: ssp@80034000 {
ssp1: spi@80034000 {
reg = <0x80034000 0x2000>;
interrupts = <2>;
clocks = <&clks 33>;

6
arch/arm/boot/dts/imx25.dtsi
View File

@ -168,7 +168,7 @@
status = "disabled";
};
spi1: cspi@43fa4000 {
spi1: spi@43fa4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
@ -209,7 +209,7 @@
reg = <0x50000000 0x40000>;
ranges;
spi3: cspi@50004000 {
spi3: spi@50004000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
@ -238,7 +238,7 @@
status = "disabled";
};
spi2: cspi@50010000 {
spi2: spi@50010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";

6
arch/arm/boot/dts/imx27.dtsi
View File

@ -209,7 +209,7 @@
status = "disabled";
};
cspi1: cspi@1000e000 {
cspi1: spi@1000e000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx27-cspi";
@ -221,7 +221,7 @@
status = "disabled";
};
cspi2: cspi@1000f000 {
cspi2: spi@1000f000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx27-cspi";
@ -373,7 +373,7 @@
status = "disabled";
};
cspi3: cspi@10017000 {
cspi3: spi@10017000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx27-cspi";

4
arch/arm/boot/dts/imx28-apf28dev.dts
View File

@ -18,7 +18,7 @@
apb@80000000 {
apbh@80000000 {
ssp0: ssp@80010000 {
ssp0: spi@80010000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_4bit_pins_a
@ -27,7 +27,7 @@
status = "okay";
};
ssp2: ssp@80014000 {
ssp2: spi@80014000 {
compatible = "fsl,imx28-spi";
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_a>;

4
arch/arm/boot/dts/imx28-apx4devkit.dts
View File

@ -18,7 +18,7 @@
status = "okay";
};
ssp0: ssp@80010000 {
ssp0: spi@80010000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>;
@ -26,7 +26,7 @@
status = "okay";
};
ssp2: ssp@80014000 {
ssp2: spi@80014000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc2_4bit_pins_apx4 &mmc2_sck_cfg_apx4>;

2
arch/arm/boot/dts/imx28-cfa10036.dts
View File

@ -66,7 +66,7 @@
};
ssp0: ssp@80010000 {
ssp0: spi@80010000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_4bit_pins_a

4
arch/arm/boot/dts/imx28-duckbill-2-485.dts
View File

@ -25,7 +25,7 @@
apb@80000000 {
apbh@80000000 {
ssp0: ssp@80010000 {
ssp0: spi@80010000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_8bit_pins_a
@ -36,7 +36,7 @@
non-removable;
};
ssp2: ssp@80014000 {
ssp2: spi@80014000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc2_4bit_pins_b

4
arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
View File

@ -26,7 +26,7 @@
apb@80000000 {
apbh@80000000 {
ssp0: ssp@80010000 {
ssp0: spi@80010000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_8bit_pins_a
@ -37,7 +37,7 @@
non-removable;
};
ssp2: ssp@80014000 {
ssp2: spi@80014000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc2_4bit_pins_b

4
arch/arm/boot/dts/imx28-duckbill-2-spi.dts
View File

@ -29,7 +29,7 @@
apb@80000000 {
apbh@80000000 {
ssp0: ssp@80010000 {
ssp0: spi@80010000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_8bit_pins_a
@ -40,7 +40,7 @@
non-removable;
};
ssp2: ssp@80014000 {
ssp2: spi@80014000 {
compatible = "fsl,imx28-spi";
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_a>;

4
arch/arm/boot/dts/imx28-duckbill-2.dts
View File

@ -25,7 +25,7 @@
apb@80000000 {
apbh@80000000 {
ssp0: ssp@80010000 {
ssp0: spi@80010000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_8bit_pins_a
@ -36,7 +36,7 @@
non-removable;
};
ssp2: ssp@80014000 {
ssp2: spi@80014000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc2_4bit_pins_b

4
arch/arm/boot/dts/imx28-duckbill.dts
View File

@ -24,7 +24,7 @@
apb@80000000 {
apbh@80000000 {
ssp0: ssp@80010000 {
ssp0: spi@80010000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_4bit_pins_a
@ -34,7 +34,7 @@
status = "okay";
};
ssp2: ssp@80014000 {
ssp2: spi@80014000 {
compatible = "fsl,imx28-spi";
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_a>;

6
arch/arm/boot/dts/imx28-evk.dts
View File

@ -103,7 +103,7 @@
status = "okay";
};
ssp0: ssp@80010000 {
ssp0: spi@80010000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_8bit_pins_a
@ -114,13 +114,13 @@
status = "okay";
};
ssp1: ssp@80012000 {
ssp1: spi@80012000 {
compatible = "fsl,imx28-mmc";
bus-width = <8>;
wp-gpios = <&gpio0 28 0>;
};
ssp2: ssp@80014000 {
ssp2: spi@80014000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx28-spi";

4
arch/arm/boot/dts/imx28-m28cu3.dts
View File

@ -41,7 +41,7 @@
};
};
ssp0: ssp@80010000 {
ssp0: spi@80010000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_4bit_pins_a
@ -52,7 +52,7 @@
status = "okay";
};
ssp2: ssp@80014000 {
ssp2: spi@80014000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc2_4bit_pins_a

4
arch/arm/boot/dts/imx28-m28evk.dts
View File

@ -18,7 +18,7 @@
apb@80000000 {
apbh@80000000 {
ssp0: ssp@80010000 {
ssp0: spi@80010000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_8bit_pins_a
@ -30,7 +30,7 @@
status = "okay";
};
ssp2: ssp@80014000 {
ssp2: spi@80014000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx28-spi";

4
arch/arm/boot/dts/imx28-sps1.dts
View File

@ -40,7 +40,7 @@
};
ssp0: ssp@80010000 {
ssp0: spi@80010000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_4bit_pins_a>;
@ -48,7 +48,7 @@
status = "okay";
};
ssp2: ssp@80014000 {
ssp2: spi@80014000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx28-spi";

2
arch/arm/boot/dts/imx28-ts4600.dts
View File

@ -25,7 +25,7 @@
apb@80000000 {
apbh@80000000 {
ssp0: ssp@80010000 {
ssp0: spi@80010000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_4bit_pins_a

8
arch/arm/boot/dts/imx28.dtsi
View File

@ -117,7 +117,7 @@
status = "disabled";
};
ssp0: ssp@80010000 {
ssp0: spi@80010000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x80010000 0x2000>;
@ -128,7 +128,7 @@
status = "disabled";
};
ssp1: ssp@80012000 {
ssp1: spi@80012000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x80012000 0x2000>;
@ -139,7 +139,7 @@
status = "disabled";
};
ssp2: ssp@80014000 {
ssp2: spi@80014000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x80014000 0x2000>;
@ -150,7 +150,7 @@
status = "disabled";
};
ssp3: ssp@80016000 {
ssp3: spi@80016000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x80016000 0x2000>;

4
arch/arm/boot/dts/imx31.dtsi
View File

@ -206,7 +206,7 @@
status = "disabled";
};
spi2: cspi@50010000 {
spi2: spi@50010000 {
compatible = "fsl,imx31-cspi";
reg = <0x50010000 0x4000>;
interrupts = <13>;
@ -241,7 +241,7 @@
#clock-cells = <1>;
};
spi3: cspi@53f84000 {
spi3: spi@53f84000 {
compatible = "fsl,imx31-cspi";
reg = <0x53f84000 0x4000>;
interrupts = <17>;

4
arch/arm/boot/dts/imx35.dtsi
View File

@ -133,7 +133,7 @@
status = "disabled";
};
spi1: cspi@43fa4000 {
spi1: spi@43fa4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx35-cspi";
@ -174,7 +174,7 @@
status = "disabled";
};
spi2: cspi@50010000 {
spi2: spi@50010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx35-cspi";

6
arch/arm/boot/dts/imx50.dtsi
View File

@ -140,7 +140,7 @@
status = "disabled";
};
ecspi1: ecspi@50010000 {
ecspi1: spi@50010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
@ -403,7 +403,7 @@
status = "disabled";
};
ecspi2: ecspi@63fac000 {
ecspi2: spi@63fac000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
@ -426,7 +426,7 @@
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
};
cspi: cspi@63fc0000 {
cspi: spi@63fc0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";

1
arch/arm/boot/dts/imx51-babbage.dts
View File

@ -204,6 +204,7 @@
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
fsl,mc13xxx-uses-adc;
fsl,mc13xxx-uses-rtc;
regulators {

2
arch/arm/boot/dts/imx51-zii-rdu1.dts
View File

@ -508,7 +508,7 @@
};
ds1341: rtc@68 {
compatible = "maxim,ds1341";
compatible = "dallas,ds1341";
reg = <0x68>;
};

8
arch/arm/boot/dts/imx51-zii-scu2-mezz.dts
View File

@ -342,6 +342,14 @@
vcc-supply = <&vusb2_reg>;
};
&vpu {
status = "disabled";
};
&wdog1 {
status = "disabled";
};
&iomuxc {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <

4
arch/arm/boot/dts/imx51-zii-scu3-esb.dts
View File

@ -350,6 +350,10 @@
vcc-supply = <&vusb2_reg>;
};
&vpu {
status = "disabled";
};
&wdog1 {
status = "disabled";
};

8
arch/arm/boot/dts/imx51.dtsi
View File

@ -197,7 +197,7 @@
status = "disabled";
};
ecspi1: ecspi@70010000 {
ecspi1: spi@70010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-ecspi";
@ -464,7 +464,7 @@
status = "disabled";
};
ecspi2: ecspi@83fac000 {
ecspi2: spi@83fac000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-ecspi";
@ -487,7 +487,7 @@
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
};
cspi: cspi@83fc0000 {
cspi: spi@83fc0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
@ -608,7 +608,7 @@
status = "disabled";
};
vpu@83ff4000 {
vpu: vpu@83ff4000 {
compatible = "fsl,imx51-vpu", "cnm,codahx4";
reg = <0x83ff4000 0x1000>;
interrupts = <9>;

1
arch/arm/boot/dts/imx53-ppd.dts
View File

@ -319,7 +319,6 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
num-chipselects = <1>;
cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
status = "okay";

6
arch/arm/boot/dts/imx53.dtsi
View File

@ -259,7 +259,7 @@
status = "disabled";
};
ecspi1: ecspi@50010000 {
ecspi1: spi@50010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
@ -684,7 +684,7 @@
status = "disabled";
};
ecspi2: ecspi@63fac000 {
ecspi2: spi@63fac000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
@ -707,7 +707,7 @@
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
};
cspi: cspi@63fc0000 {
cspi: spi@63fc0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";

2
arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
View File

@ -146,7 +146,7 @@
&ecspi4 {
status = "okay";
mcp251x0: mcp251x@1 {
mcp251x0: mcp251x@0 {
compatible = "microchip,mcp2515";
reg = <0>;
clocks = <&clk16m>;

2
arch/arm/boot/dts/imx6dl-icore-mipi.dts
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Copyright (C) 2018 Engicam S.r.l.
* Copyright (C) 2018 Amarula Solutions B.V.

38
arch/arm/boot/dts/imx6dl-icore-rqs.dts
View File

@ -1,43 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;

38
arch/arm/boot/dts/imx6dl-icore.dts
View File

@ -1,43 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;

5
arch/arm/boot/dts/imx6dl-riotboard.dts
View File

@ -84,6 +84,10 @@
status = "okay";
};
&clks {
fsl,pmic-stby-poweroff;
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
@ -164,6 +168,7 @@
reg = <0x08>;
interrupt-parent = <&gpio5>;
interrupts = <16 8>;
fsl,pmic-stby-poweroff;
regulators {
reg_vddcore: sw1ab { /* VDDARM_IN */

2
arch/arm/boot/dts/imx6q-apalis-eval.dts
View File

@ -196,6 +196,8 @@
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reset_moci>;
/* active-high meaning opposite of regular PERST# active-low polarity */
reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
reset-gpio-active-high;

2
arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
View File

@ -196,6 +196,8 @@
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reset_moci>;
/* active-high meaning opposite of regular PERST# active-low polarity */
reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
reset-gpio-active-high;

2
arch/arm/boot/dts/imx6q-apalis-ixora.dts
View File

@ -200,6 +200,8 @@
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reset_moci>;
/* active-high meaning opposite of regular PERST# active-low polarity */
reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
reset-gpio-active-high;

6
arch/arm/boot/dts/imx6q-icore-mipi.dts
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Copyright (C) 2017 Engicam S.r.l.
* Copyright (C) 2017 Amarula Solutions B.V.
@ -8,10 +8,10 @@
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-icore.dtsi"
#include "imx6qdl-icore-1.5.dtsi"
/ {
model = "Engicam i.CoreM6 Quad/Dual MIPI Starter Kit";
model = "Engicam i.CoreM6 1.5 Quad/Dual MIPI Starter Kit";
compatible = "engicam,imx6-icore", "fsl,imx6q";
};

38
arch/arm/boot/dts/imx6q-icore-ofcap10.dts
View File

@ -1,43 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;

38
arch/arm/boot/dts/imx6q-icore-ofcap12.dts
View File

@ -1,43 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;

39
arch/arm/boot/dts/imx6q-icore-rqs.dts
View File

@ -1,42 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2015 Amarula Solutions B.V.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
* Copyright (C) 2015 Engicam S.r.l.
*/
/dts-v1/;

38
arch/arm/boot/dts/imx6q-icore.dts
View File

@ -1,43 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;

2
arch/arm/boot/dts/imx6q.dtsi
View File

@ -163,7 +163,7 @@
aips-bus@2000000 { /* AIPS1 */
spba-bus@2000000 {
ecspi5: ecspi@2018000 {
ecspi5: spi@2018000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";

4
arch/arm/boot/dts/imx6qdl-apalis.dtsi
View File

@ -482,10 +482,6 @@
};
&iomuxc {
/* pins used on module */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reset_moci>;
pinctrl_apalis_gpio1: gpio2io04grp {
fsl,pins = <
MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0

34
arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi Normal file
View File

@ -0,0 +1,34 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Jacopo Mondi <jacopo@jmondi.org>
*/
#include "imx6qdl-icore.dtsi"
&iomuxc {
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
clocks = <&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET_REF>;
phy-mode = "rmii";
status = "okay";
};

41
arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
View File

@ -1,42 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Copyright (C) 2015 Amarula Solutions B.V.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
* Copyright (C) 2015 Engicam S.r.l.
*/
#include <dt-bindings/gpio/gpio.h>
@ -316,7 +281,7 @@
};
&iomuxc {
pinctrl_audmux: audmux {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0

42
arch/arm/boot/dts/imx6qdl-icore.dtsi
View File

@ -1,43 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
@ -310,7 +274,7 @@
};
&iomuxc {
pinctrl_audmux: audmux {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
@ -349,7 +313,7 @@
>;
};
pinctrl_gpmi_nand: gpmi-nand {
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1

67
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
View File

@ -4,6 +4,7 @@
// Copyright 2011 Linaro Ltd.
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
chosen {
@ -25,6 +26,47 @@
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
home {
label = "Home";
gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
wakeup-source;
};
back {
label = "Back";
gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
wakeup-source;
};
program {
label = "Program";
gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PROGRAM>;
wakeup-source;
};
volume-up {
label = "Volume Up";
gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
wakeup-source;
};
volume-down {
label = "Volume Down";
gpios = <&gpio5 14 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
wakeup-source;
};
};
clocks {
codec_osc: anaclk2 {
compatible = "fixed-clock";
@ -375,6 +417,15 @@
VLC-supply = <&reg_audio>;
};
touchscreen@4 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_egalax_int>;
interrupt-parent = <&gpio2>;
interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
};
};
&i2c3 {
@ -410,6 +461,12 @@
>;
};
pinctrl_egalax_int: egalax-intgrp {
fsl,pins = <
MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
@ -446,6 +503,16 @@
>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0
MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0
MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000

4
arch/arm/boot/dts/imx6qdl-wandboard.dtsi
View File

@ -8,6 +8,10 @@
#include <dt-bindings/gpio/gpio.h>
/ {
chosen {
stdout-path = &uart1;
};
sound {
compatible = "fsl,imx6-wandboard-sgtl5000",
"fsl,imx-audio-sgtl5000";

4
arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
View File

@ -813,6 +813,10 @@
status = "okay";
};
&snvs_rtc {
status = "disabled";
};
&ssi1 {
status = "okay";
};

8
arch/arm/boot/dts/imx6qdl.dtsi
View File

@ -317,7 +317,7 @@
status = "disabled";
};
ecspi1: ecspi@2008000 {
ecspi1: spi@2008000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@ -331,7 +331,7 @@
status = "disabled";
};
ecspi2: ecspi@200c000 {
ecspi2: spi@200c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@ -345,7 +345,7 @@
status = "disabled";
};
ecspi3: ecspi@2010000 {
ecspi3: spi@2010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@ -359,7 +359,7 @@
status = "disabled";
};
ecspi4: ecspi@2014000 {
ecspi4: spi@2014000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";

8
arch/arm/boot/dts/imx6sl.dtsi
View File

@ -168,7 +168,7 @@
status = "disabled";
};
ecspi1: ecspi@2008000 {
ecspi1: spi@2008000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
@ -180,7 +180,7 @@
status = "disabled";
};
ecspi2: ecspi@200c000 {
ecspi2: spi@200c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
@ -192,7 +192,7 @@
status = "disabled";
};
ecspi3: ecspi@2010000 {
ecspi3: spi@2010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
@ -204,7 +204,7 @@
status = "disabled";
};
ecspi4: ecspi@2014000 {
ecspi4: spi@2014000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";

31
arch/arm/boot/dts/imx6sll.dtsi
View File

@ -375,10 +375,12 @@
reg = <0x0209c000 0x4000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>;
};
gpio2: gpio@20a0000 {
@ -386,10 +388,12 @@
reg = <0x020a0000 0x4000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 50 32>;
};
gpio3: gpio@20a4000 {
@ -397,10 +401,14 @@
reg = <0x020a4000 0x4000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>,
<&iomuxc 16 101 2>, <&iomuxc 18 5 1>,
<&iomuxc 21 6 11>;
};
gpio4: gpio@20a8000 {
@ -408,10 +416,20 @@
reg = <0x020a8000 0x4000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_GPIO4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>,
<&iomuxc 16 151 1>, <&iomuxc 17 149 1>,
<&iomuxc 18 146 1>, <&iomuxc 19 144 1>,
<&iomuxc 20 142 1>, <&iomuxc 21 143 1>,
<&iomuxc 22 150 1>, <&iomuxc 23 148 1>,
<&iomuxc 24 147 1>, <&iomuxc 25 145 1>,
<&iomuxc 26 152 1>, <&iomuxc 27 125 1>,
<&iomuxc 28 131 1>, <&iomuxc 29 134 1>,
<&iomuxc 30 129 1>, <&iomuxc 31 133 1>;
};
gpio5: gpio@20ac000 {
@ -419,10 +437,22 @@
reg = <0x020ac000 0x4000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_GPIO5>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>,
<&iomuxc 2 132 1>, <&iomuxc 3 130 1>,
<&iomuxc 4 127 1>, <&iomuxc 5 126 1>,
<&iomuxc 6 120 1>, <&iomuxc 7 123 1>,
<&iomuxc 8 118 1>, <&iomuxc 9 122 1>,
<&iomuxc 10 124 1>, <&iomuxc 11 117 1>,
<&iomuxc 12 121 1>, <&iomuxc 13 119 1>,
<&iomuxc 14 116 1>, <&iomuxc 15 115 1>,
<&iomuxc 16 140 2>, <&iomuxc 18 136 1>,
<&iomuxc 19 138 1>, <&iomuxc 20 139 1>,
<&iomuxc 21 137 1>;
};
gpio6: gpio@20b0000 {
@ -430,6 +460,7 @@
reg = <0x020b0000 0x4000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_GPIO6>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;

2
arch/arm/boot/dts/imx6sx-sdb.dtsi
View File

@ -40,12 +40,14 @@
label = "Volume Up";
gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
wakeup-source;
};
volume-down {
label = "Volume Down";
gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
wakeup-source;
};
};

14
arch/arm/boot/dts/imx6sx.dtsi
View File

@ -268,7 +268,7 @@
status = "disabled";
};
ecspi1: ecspi@2008000 {
ecspi1: spi@2008000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
@ -280,7 +280,7 @@
status = "disabled";
};
ecspi2: ecspi@200c000 {
ecspi2: spi@200c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
@ -292,7 +292,7 @@
status = "disabled";
};
ecspi3: ecspi@2010000 {
ecspi3: spi@2010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
@ -304,7 +304,7 @@
status = "disabled";
};
ecspi4: ecspi@2014000 {
ecspi4: spi@2014000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
@ -1079,7 +1079,7 @@
status = "disabled";
};
qspi1: qspi@21e0000 {
qspi1: spi@21e0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-qspi";
@ -1092,7 +1092,7 @@
status = "disabled";
};
qspi2: qspi@21e4000 {
qspi2: spi@21e4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-qspi";
@ -1273,7 +1273,7 @@
status = "disabled";
};
ecspi5: ecspi@228c000 {
ecspi5: spi@228c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";

390
arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts Normal file
View File

@ -0,0 +1,390 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Digi International's ConnectCore6UL SBC Pro board device tree source
*
* Copyright 2018 Digi International, Inc.
*
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6ul.dtsi"
#include "imx6ul-ccimx6ulsom.dtsi"
/ {
model = "Digi International ConnectCore 6UL SBC Pro.";
compatible = "digi,ccimx6ulsbcpro", "digi,ccimx6ulsom", "fsl,imx6ul";
lcd_backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm5 0 50000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
status = "okay";
};
reg_usb_otg1_vbus: regulator-usb-otg1 {
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&adc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc1>;
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&ext_3v3>;
status = "okay";
};
/* CAN2 is multiplexed with UART2 RTS/CTS */
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&ext_3v3>;
status = "disabled";
};
&ecspi1 {
cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_master>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
status = "okay";
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
phy-reset-duration = <26>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
smsc,disable-energy-detect;
reg = <0>;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
smsc,disable-energy-detect;
reg = <1>;
};
};
};
&gpio5 {
emmc-usd-mux {
gpio-hog;
gpios = <1 GPIO_ACTIVE_LOW>;
output-high;
};
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat0_17
&pinctrl_lcdif_clken
&pinctrl_lcdif_hvsync>;
lcd-supply = <&ldo4_ext>; /* BU90T82 LVDS bridge power */
status = "okay";
};
&ldo4_ext {
regulator-max-microvolt = <1800000>;
};
&pwm1 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&pwm3 {
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&pwm5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm5>;
status = "okay";
};
&pwm6 {
status = "okay";
};
&pwm7 {
status = "okay";
};
&pwm8 {
status = "okay";
};
&sai2 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_sai2>;
pinctrl-1 = <&pinctrl_sai2_sleep>;
assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
<&clks IMX6UL_CLK_PLL4_AUDIO_DIV>,
<&clks IMX6UL_CLK_SAI2>;
assigned-clock-rates = <0>, <786432000>, <12288000>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
status = "okay";
};
/* UART2 RTS/CTS muxed with CAN2 */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_4wires>;
uart-has-rtscts;
status = "okay";
};
/* UART3 RTS/CTS muxed with CAN 1 */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_2wires>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
vbus-supply = <&reg_usb_otg1_vbus>;
pinctrl-0 = <&pinctrl_usbotg1>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
/* USDHC2 (microSD conflicts with eMMC) */
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
no-1-8-v;
broken-cd; /* no carrier detect line (use polling) */
status = "okay";
};
&iomuxc {
pinctrl_adc1: adc1grp {
fsl,pins = <
/* EXP_GPIO_2 -> GPIO1_3/ADC1_IN3 */
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
>;
};
pinctrl_ecspi1_master: ecspi1grp1 {
fsl,pins = <
MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x10b0
MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x10b0
MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x10b0
MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40017051
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x40017051
>;
};
pinctrl_enet2_mdio: mdioenet2grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
>;
};
pinctrl_flexcan1: flexcan1grp{
fsl,pins = <
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
>;
};
pinctrl_flexcan2: flexcan2grp{
fsl,pins = <
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
>;
};
pinctrl_lcdif_dat0_17: lcdifdatgrp0-17 {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
>;
};
pinctrl_lcdif_clken: lcdifctrlgrp1 {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x17050
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
>;
};
pinctrl_lcdif_hvsync: lcdifctrlgrp2 {
fsl,pins = <
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0
>;
};
pinctrl_pwm5: pwm5grp {
fsl,pins = <
MX6UL_PAD_NAND_DQS__PWM5_OUT 0x110b0
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
/* Interrupt */
MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10b0
>;
};
pinctrl_sai2_sleep: sai2grp-sleep {
fsl,pins = <
MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x3000
MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x3000
MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x3000
MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x3000
/* Interrupt */
MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x3000
>;
};
pinctrl_uart2_4wires: uart2grp-4wires {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1
>;
};
pinctrl_uart3_2wires: uart3grp-2wires {
fsl,pins = <
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10039
MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059
/* Mux selector between eMMC/SD# */
MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x79
>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x17059
MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x17059
>;
};
};

40
arch/arm/boot/dts/imx6ul-geam.dts
View File

@ -1,43 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@ -328,7 +292,7 @@
>;
};
pinctrl_gpmi_nand: gpmi-nand {
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1

61
arch/arm/boot/dts/imx6ul-isiot-emmc.dts
View File

@ -1,43 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@ -50,28 +14,5 @@
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
bus-width = <8>;
no-1-8-v;
status = "okay";
};
&iomuxc {
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17070
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17070
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17070
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17070
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17070
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17070
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17070
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17070
MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17070
>;
};
};

63
arch/arm/boot/dts/imx6ul-isiot-nand.dts
View File

@ -1,43 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@ -50,30 +14,5 @@
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
};
&iomuxc {
pinctrl_gpmi_nand: gpmi-nand {
fsl,pins = <
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
>;
};
};

90
arch/arm/boot/dts/imx6ul-isiot.dtsi
View File

@ -1,43 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
@ -133,6 +97,13 @@
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "disabled";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
@ -243,6 +214,15 @@
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
bus-width = <8>;
no-1-8-v;
status = "disabled";
};
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
@ -259,6 +239,26 @@
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
@ -366,4 +366,20 @@
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17070
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17070
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17070
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17070
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17070
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17070
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17070
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17070
MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17070
>;
};
};

28
arch/arm/boot/dts/imx6ul.dtsi
View File

@ -89,6 +89,8 @@
"pll1_sys";
arm-supply = <&reg_arm>;
soc-supply = <&reg_soc>;
nvmem-cells = <&cpu_speed_grade>;
nvmem-cell-names = "speed_grade";
};
};
@ -156,7 +158,6 @@
compatible = "arm,cortex-a7-pmu";
interrupt-parent = <&gpc>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
soc {
@ -218,7 +219,7 @@
reg = <0x02000000 0x40000>;
ranges;
ecspi1: ecspi@2008000 {
ecspi1: spi@2008000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
@ -230,7 +231,7 @@
status = "disabled";
};
ecspi2: ecspi@200c000 {
ecspi2: spi@200c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
@ -242,7 +243,7 @@
status = "disabled";
};
ecspi3: ecspi@2010000 {
ecspi3: spi@2010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
@ -254,7 +255,7 @@
status = "disabled";
};
ecspi4: ecspi@2014000 {
ecspi4: spi@2014000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
@ -918,6 +919,17 @@
reg = <0x021b0000 0x4000>;
};
weim: weim@21b8000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
reg = <0x021b8000 0x4000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_EIM>;
fsl,weim-cs-gpr = <&gpr>;
status = "disabled";
};
ocotp: ocotp-ctrl@21bc000 {
#address-cells = <1>;
#size-cells = <1>;
@ -932,6 +944,10 @@
tempmon_temp_grade: temp-grade@20 {
reg = <0x20 4>;
};
cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>;
};
};
lcdif: lcdif@21c8000 {
@ -945,7 +961,7 @@
status = "disabled";
};
qspi: qspi@21e0000 {
qspi: spi@21e0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";

2
arch/arm/boot/dts/imx6ull-14x14-evk.dts
View File

@ -45,7 +45,7 @@
#include "imx6ul-14x14-evk.dtsi"
/ {
model = "Freescale i.MX6 UlltraLite 14x14 EVK Board";
model = "Freescale i.MX6 UltraLiteLite 14x14 EVK Board";
compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
};

39
arch/arm/boot/dts/imx6ull-pinfunc.h
View File

@ -14,14 +14,38 @@
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
/* signals common for i.MX6UL and i.MX6ULL */
#undef MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX
#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6
#undef MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX
#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7
#undef MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS
#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5
#undef MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS
#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6
#undef MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS
#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7
/* signals for i.MX6ULL only */
#define MX6ULL_PAD_UART1_TX_DATA__UART5_DCE_TX 0x0084 0x0310 0x0000 0x9 0x0
#define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4
#define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5
#define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_RTS 0x008C 0x0318 0x0640 0x9 0x3
#define MX6ULL_PAD_UART1_RTS_B__UART5_DTE_RTS 0x0090 0x031C 0x0640 0x9 0x4
#define MX6ULL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6
#define MX6ULL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7
#define MX6ULL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5
#define MX6ULL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6
#define MX6ULL_PAD_UART1_RX_DATA__UART5_DTE_TX 0x0088 0x0314 0x0000 0x9 0x0
#define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_CTS 0x008C 0x0318 0x0000 0x9 0x0
#define MX6ULL_PAD_UART1_CTS_B__UART5_DTE_RTS 0x008C 0x0318 0x0640 0x9 0x3
#define MX6ULL_PAD_UART1_RTS_B__UART5_DCE_RTS 0x0090 0x031C 0x0640 0x9 0x4
#define MX6ULL_PAD_UART1_RTS_B__UART5_DTE_CTS 0x0090 0x031C 0x0000 0x9 0x0
#define MX6ULL_PAD_UART4_RX_DATA__EPDC_PWRCTRL01 0x00B8 0x0344 0x0000 0x9 0x0
#define MX6ULL_PAD_UART5_TX_DATA__EPDC_PWRCTRL02 0x00BC 0x0348 0x0000 0x9 0x0
#define MX6ULL_PAD_UART5_RX_DATA__EPDC_PWRCTRL03 0x00C0 0x034C 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_RX_DATA0__EPDC_SDCE04 0x00C4 0x0350 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_RX_DATA1__EPDC_SDCE05 0x00C8 0x0354 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_RX_EN__EPDC_SDCE06 0x00CC 0x0358 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_TX_DATA0__EPDC_SDCE07 0x00D0 0x035C 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_TX_DATA1__EPDC_SDCE08 0x00D4 0x0360 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_TX_EN__EPDC_SDCE09 0x00D8 0x0364 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_TX_CLK__EPDC_SDOED 0x00DC 0x0368 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_RX_ER__EPDC_SDOEZ 0x00E0 0x036C 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0
@ -48,6 +72,8 @@
#define MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK 0x0158 0x03E4 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA22__EPDC_SDCE02 0x0170 0x03FC 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA23__EPDC_SDCE03 0x0174 0x0400 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0
@ -55,7 +81,6 @@
#define MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7
#define MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0

2
arch/arm/boot/dts/imx6ull.dtsi
View File

@ -22,7 +22,7 @@
>;
fsl,soc-operating-points = <
/* KHz uV */
900000 1175000
900000 1250000
792000 1175000
528000 1175000
396000 1175000

20
arch/arm/boot/dts/imx6ulz-14x14-evk.dts Normal file
View File

@ -0,0 +1,20 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright 2018 NXP.
/dts-v1/;
#include "imx6ulz.dtsi"
#include "imx6ul-14x14-evk.dtsi"
/delete-node/ &fec1;
/delete-node/ &fec2;
/delete-node/ &lcdif;
/delete-node/ &tsc;
/ {
model = "Freescale i.MX6 ULZ 14x14 EVK Board";
compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull", "fsl,imx6ulz";
/delete-node/ panel;
};

38
arch/arm/boot/dts/imx6ulz.dtsi Normal file
View File

@ -0,0 +1,38 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright 2018 NXP.
#include "imx6ull.dtsi"
/ {
aliases {
/delete-property/ ethernet0;
/delete-property/ ethernet1;
/delete-property/ i2c2;
/delete-property/ i2c3;
/delete-property/ serial4;
/delete-property/ serial5;
/delete-property/ serial6;
/delete-property/ serial7;
/delete-property/ spi2;
/delete-property/ spi3;
};
};
/delete-node/ &adc1;
/delete-node/ &can1;
/delete-node/ &can2;
/delete-node/ &ecspi3;
/delete-node/ &ecspi4;
/delete-node/ &epit2;
/delete-node/ &gpt2;
/delete-node/ &i2c3;
/delete-node/ &i2c4;
/delete-node/ &pwm5;
/delete-node/ &pwm6;
/delete-node/ &pwm7;
/delete-node/ &pwm8;
/delete-node/ &uart5;
/delete-node/ &uart6;
/delete-node/ &uart7;
/delete-node/ &uart8;

2
arch/arm/boot/dts/imx7d-sdb.dts
View File

@ -27,12 +27,14 @@
label = "Volume Up";
gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
wakeup-source;
};
volume-down {
label = "Volume Down";
gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
wakeup-source;
};
};

15
arch/arm/boot/dts/imx7d.dtsi
View File

@ -20,6 +20,7 @@
reg = <1>;
clock-frequency = <996000000>;
operating-points-v2 = <&cpu0_opp_table>;
cpu-idle-states = <&cpu_sleep_wait>;
};
};
@ -63,9 +64,11 @@
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
port {
etm1_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port1>;
out-ports {
port {
etm1_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port1>;
};
};
};
};
@ -152,11 +155,13 @@
};
};
&ca_funnel_ports {
&ca_funnel_in_ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
ca_funnel_in_port1: endpoint {
slave-mode;
remote-endpoint = <&etm1_out_port>;
};
};

53
arch/arm/boot/dts/imx7s-warp.dts
View File

@ -1,44 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2016 NXP Semiconductors.
* Author: Fabio Estevam <fabio.estevam@nxp.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@ -216,6 +179,13 @@
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
@ -346,6 +316,13 @@
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f

131
arch/arm/boot/dts/imx7s.dtsi
View File

@ -54,6 +54,19 @@
#address-cells = <1>;
#size-cells = <0>;
idle-states {
entry-method = "psci";
cpu_sleep_wait: cpu-sleep-wait {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <100>;
exit-latency-us = <50>;
min-residency-us = <1000>;
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
@ -61,6 +74,7 @@
clock-frequency = <792000000>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX7D_CLK_ARM>;
cpu-idle-states = <&cpu_sleep_wait>;
};
};
@ -106,7 +120,7 @@
*/
compatible = "arm,coresight-replicator";
ports {
out-ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
@ -123,12 +137,11 @@
remote-endpoint = <&etr_in_port>;
};
};
};
/* replicator input port */
port@2 {
reg = <0>;
in-ports {
port {
replicator_in_port0: endpoint {
slave-mode;
remote-endpoint = <&etf_out_port>;
};
};
@ -168,28 +181,23 @@
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
ca_funnel_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
/* funnel input ports */
port@0 {
reg = <0>;
ca_funnel_in_ports: in-ports {
port {
ca_funnel_in_port0: endpoint {
slave-mode;
remote-endpoint = <&etm0_out_port>;
};
};
/* funnel output port */
port@2 {
reg = <0>;
/* the other input ports are not connect to anything */
};
out-ports {
port {
ca_funnel_out_port0: endpoint {
remote-endpoint = <&hugo_funnel_in_port0>;
};
};
/* the other input ports are not connect to anything */
};
};
@ -200,9 +208,11 @@
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
port {
etm0_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port0>;
out-ports {
port {
etm0_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port0>;
};
};
};
};
@ -213,15 +223,13 @@
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
ports {
in-ports {
#address-cells = <1>;
#size-cells = <0>;
/* funnel input ports */
port@0 {
reg = <0>;
hugo_funnel_in_port0: endpoint {
slave-mode;
remote-endpoint = <&ca_funnel_out_port0>;
};
};
@ -229,18 +237,18 @@
port@1 {
reg = <1>;
hugo_funnel_in_port1: endpoint {
slave-mode; /* M4 input */
/* M4 input */
};
};
/* the other input ports are not connect to anything */
};
port@2 {
reg = <0>;
out-ports {
port {
hugo_funnel_out_port0: endpoint {
remote-endpoint = <&etf_in_port>;
};
};
/* the other input ports are not connect to anything */
};
};
@ -250,20 +258,16 @@
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
in-ports {
port {
etf_in_port: endpoint {
slave-mode;
remote-endpoint = <&hugo_funnel_out_port0>;
};
};
};
port@1 {
reg = <0>;
out-ports {
port {
etf_out_port: endpoint {
remote-endpoint = <&replicator_in_port0>;
};
@ -277,10 +281,11 @@
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
port {
etr_in_port: endpoint {
slave-mode;
remote-endpoint = <&replicator_out_port1>;
in-ports {
port {
etr_in_port: endpoint {
remote-endpoint = <&replicator_out_port1>;
};
};
};
};
@ -291,10 +296,11 @@
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
port {
tpiu_in_port: endpoint {
slave-mode;
remote-endpoint = <&replicator_out_port0>;
in-ports {
port {
tpiu_in_port: endpoint {
remote-endpoint = <&replicator_out_port0>;
};
};
};
};
@ -563,14 +569,6 @@
clock-names = "snvs-rtc";
};
snvs_poweroff: snvs-poweroff {
compatible = "syscon-poweroff";
regmap = <&snvs>;
offset = <0x38>;
value = <0x60>;
mask = <0x60>;
};
snvs_pwrkey: snvs-powerkey {
compatible = "fsl,sec-v4.0-pwrkey";
regmap = <&snvs>;
@ -644,7 +642,7 @@
status = "disabled";
};
ecspi4: ecspi@30630000 {
ecspi4: spi@30630000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
@ -725,7 +723,7 @@
reg = <0x30800000 0x100000>;
ranges;
ecspi1: ecspi@30820000 {
ecspi1: spi@30820000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
@ -737,7 +735,7 @@
status = "disabled";
};
ecspi2: ecspi@30830000 {
ecspi2: spi@30830000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
@ -749,7 +747,7 @@
status = "disabled";
};
ecspi3: ecspi@30840000 {
ecspi3: spi@30840000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
@ -974,6 +972,25 @@
status = "disabled";
};
mu0a: mailbox@30aa0000 {
compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
reg = <0x30aa0000 0x10000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_MU_ROOT_CLK>;
#mbox-cells = <2>;
status = "disabled";
};
mu0b: mailbox@30ab0000 {
compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
reg = <0x30ab0000 0x10000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_MU_ROOT_CLK>;
#mbox-cells = <2>;
fsl,mu-side-b;
status = "disabled";
};
usbotg1: usb@30b10000 {
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x30b10000 0x200>;

16
arch/arm/boot/dts/imx7ulp-pinfunc.h
View File

@ -116,6 +116,7 @@
#define IMX7ULP_PAD_PTC13__LPI2C7_SDA 0x0034 0x030c 0x5 0x1
#define IMX7ULP_PAD_PTC13__TPM7_CLKIN 0x0034 0x02f4 0x6 0x1
#define IMX7ULP_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC13__USB0_ID 0x0034 0x0338 0xb 0x1
#define IMX7ULP_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC14__FXIO1_D10 0x0038 0x022c 0x2 0x1
@ -136,6 +137,7 @@
#define IMX7ULP_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1
#define IMX7ULP_PAD_PTC16__TPM7_CH2 0x0040 0x02e4 0x6 0x1
#define IMX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC16__USB1_OC2 0x0040 0x0334 0xb 0x1
#define IMX7ULP_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1
#define IMX7ULP_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1
@ -146,11 +148,16 @@
#define IMX7ULP_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1
#define IMX7ULP_PAD_PTC18__TPM6_CH0 0x0048 0x02d0 0x6 0x1
#define IMX7ULP_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC18__USB0_ID 0x0048 0x0338 0xb 0x2
#define IMX7ULP_PAD_PTC18__VIU_DE 0x0048 0x033c 0xc 0x1
#define IMX7ULP_PAD_PTC19__PTC19 0x004c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC19__FXIO1_D15 0x004c 0x0240 0x2 0x1
#define IMX7ULP_PAD_PTC19__LPSPI3_PCS0 0x004c 0x0310 0x3 0x1
#define IMX7ULP_PAD_PTC19__TPM6_CH1 0x004c 0x02d4 0x6 0x1
#define IMX7ULP_PAD_PTC19__FB_A16 0x004c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC19__USB0_ID 0x004c 0x0338 0xa 0x3
#define IMX7ULP_PAD_PTC19__USB1_PWR2 0x004c 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTC19__VIU_DE 0x004c 0x033c 0xc 0x3
#define IMX7ULP_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0
@ -218,6 +225,7 @@
#define IMX7ULP_PAD_PTE5__LPI2C5_SDA 0x0114 0x02c0 0x5 0x2
#define IMX7ULP_PAD_PTE5__TPM5_CH0 0x0114 0x02c4 0x6 0x2
#define IMX7ULP_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE5__VIU_DE 0x0114 0x033c 0xc 0x2
#define IMX7ULP_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE6__LPSPI2_SCK 0x0118 0x02ac 0x3 0x2
@ -226,8 +234,10 @@
#define IMX7ULP_PAD_PTE6__TPM7_CH3 0x0118 0x02e8 0x6 0x2
#define IMX7ULP_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE6__USB0_OC 0x0118 0x0330 0xb 0x1
#define IMX7ULP_PAD_PTE7__PTE7 0x011c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE7__TRACE_D7 0x011c 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE7__USB0_PWR 0x011c 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTE7__VIU_FID 0x011c 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE7__FXIO1_D24 0x011c 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE7__LPSPI2_PCS0 0x011c 0x029c 0x3 0x2
@ -278,6 +288,7 @@
#define IMX7ULP_PAD_PTE11__FB_A20 0x012c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE12__USB1_OC2 0x0130 0x0334 0xb 0x2
#define IMX7ULP_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2
@ -288,6 +299,7 @@
#define IMX7ULP_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE13__USB1_PWR2 0x0134 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2
@ -298,6 +310,7 @@
#define IMX7ULP_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE14__USB0_OC 0x0138 0x0330 0xb 0x2
#define IMX7ULP_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2
@ -308,6 +321,7 @@
#define IMX7ULP_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE15__PTE15 0x013c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE15__TRACE_CLKOUT 0x013c 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE15__USB0_PWR 0x013c 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTE15__VIU_D23 0x013c 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE15__FXIO1_D16 0x013c 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE15__LPSPI3_PCS0 0x013c 0x0310 0x3 0x2
@ -315,7 +329,7 @@
#define IMX7ULP_PAD_PTE15__TPM6_CH1 0x013c 0x02d4 0x6 0x2
#define IMX7ULP_PAD_PTE15__FB_A24 0x013c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF0__VIU_DE 0x0180 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF0__VIU_DE 0x0180 0x033c 0xc 0x0
#define IMX7ULP_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3
#define IMX7ULP_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3
#define IMX7ULP_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3

2
arch/arm/boot/dts/ls1021a-qds.dts
View File

@ -1,5 +1,6 @@
/*
* Copyright 2013-2014 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@ -235,6 +236,7 @@
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
big-endian;
bank-width = <2>;
device-width = <1>;
};

2
arch/arm/boot/dts/ls1021a-twr.dts
View File

@ -1,5 +1,6 @@
/*
* Copyright 2013-2014 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@ -203,6 +204,7 @@
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
big-endian;
bank-width = <2>;
device-width = <1>;
};

12
arch/arm/boot/dts/ls1021a.dtsi
View File

@ -163,7 +163,7 @@
big-endian;
};
qspi: quadspi@1550000 {
qspi: spi@1550000 {
compatible = "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
@ -330,7 +330,7 @@
};
};
dspi0: dspi@2100000 {
dspi0: spi@2100000 {
compatible = "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
#size-cells = <0>;
@ -343,7 +343,7 @@
status = "disabled";
};
dspi1: dspi@2110000 {
dspi1: spi@2110000 {
compatible = "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
#size-cells = <0>;
@ -364,6 +364,8 @@
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 1>;
dma-names = "tx", "rx";
dmas = <&edma0 1 39>, <&edma0 1 38>;
status = "disabled";
};
@ -375,6 +377,8 @@
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 1>;
dma-names = "tx", "rx";
dmas = <&edma0 1 37>, <&edma0 1 36>;
status = "disabled";
};
@ -386,6 +390,8 @@
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 1>;
dma-names = "tx", "rx";
dmas = <&edma0 1 35>, <&edma0 1 34>;
status = "disabled";
};

43
arch/arm/boot/dts/vf500.dtsi
View File

@ -1,43 +1,6 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright 2013 Freescale Semiconductor, Inc.
#include "vfxxx.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>

43
arch/arm/boot/dts/vf610-twr.dts
View File

@ -1,43 +1,6 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright 2013 Freescale Semiconductor, Inc.
/dts-v1/;
#include "vf610.dtsi"

30
arch/arm/boot/dts/vf610-zii-cfu1.dts
View File

@ -66,6 +66,15 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
sff: sfp {
compatible = "sff,sff";
pinctrl-0 = <&pinctrl_optical>;
pinctrl-names = "default";
i2c-bus = <&i2c0>;
los-gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
tx-disable-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
};
};
&adc0 {
@ -113,6 +122,8 @@
non-removable;
no-1-8-v;
keep-power-in-suspend;
no-sdio;
no-sd;
status = "okay";
};
@ -120,6 +131,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
bus-width = <4>;
no-sdio;
status = "okay";
};
@ -170,6 +182,14 @@
label = "eth_cu_1000_3";
};
port@5 {
reg = <5>;
label = "eth_fc_1000_1";
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sff>;
};
port@6 {
reg = <6>;
label = "cpu";
@ -289,6 +309,16 @@
>;
};
pinctrl_optical: optical-grp {
fsl,pins = <
/* SFF SD input */
VF610_PAD_PTE27__GPIO_132 0x3061
/* SFF Transmit disable output */
VF610_PAD_PTE13__GPIO_118 0x3043
>;
};
pinctrl_switch: switch-grp {
fsl,pins = <
VF610_PAD_PTB28__GPIO_98 0x3061

44
arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
View File

@ -200,6 +200,13 @@
phy-handle = <&switch1phy4>;
};
port@9 {
reg = <9>;
label = "sff2";
phy-mode = "sgmii";
managed = "in-band-status";
sfp = <&sff2>;
};
switch1port10: port@10 {
reg = <10>;
@ -245,6 +252,22 @@
#size-cells = <0>;
};
};
sff2: sff2 {
/* lower */
compatible = "sff,sff";
i2c-bus = <&sff2_i2c>;
los-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
tx-disable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>;
};
sff3: sff3 {
/* upper */
compatible = "sff,sff";
i2c-bus = <&sff3_i2c>;
los-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
tx-disable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
};
};
&dspi0 {
@ -329,13 +352,6 @@
interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
interrupt-controller;
enet_swr_en {
gpio-hog;
gpios = <0 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "enet-swr-en";
};
};
/*
@ -378,26 +394,16 @@
reg = <0>;
};
i2c@1 {
sff2_i2c: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
sfp2: at24c04@50 {
compatible = "atmel,24c02";
reg = <0x50>;
};
};
i2c@2 {
sff3_i2c: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
sfp3: at24c04@50 {
compatible = "atmel,24c02";
reg = <0x50>;
};
};
i2c@3 {

44
arch/arm/boot/dts/vf610.dtsi
View File

@ -1,43 +1,7 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright 2013 Freescale Semiconductor, Inc.
#include "vf500.dtsi"

55
arch/arm/boot/dts/vfxxx.dtsi
View File

@ -1,43 +1,6 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright 2013 Freescale Semiconductor, Inc.
#include "vf610-pinfunc.h"
#include <dt-bindings/clock/vf610-clock.h>
@ -190,7 +153,7 @@
status = "disabled";
};
dspi0: dspi0@4002c000 {
dspi0: spi@4002c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
@ -205,7 +168,7 @@
status = "disabled";
};
dspi1: dspi1@4002d000 {
dspi1: spi@4002d000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
@ -339,7 +302,7 @@
status = "disabled";
};
qspi0: quadspi@40044000 {
qspi0: spi@40044000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-qspi";
@ -569,7 +532,7 @@
status = "disabled";
};
dspi2: dspi2@400ac000 {
dspi2: spi@400ac000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
@ -584,7 +547,7 @@
status = "disabled";
};
dspi3: dspi3@400ad000 {
dspi3: spi@400ad000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
@ -665,7 +628,7 @@
status = "disabled";
};
qspi1: quadspi@400c4000 {
qspi1: spi@400c4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-qspi";