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intel-pinctrl for v5.17-4
* Couple of fixes on how Intel driver handles an interrupt * Revert pin renaming change in ZynqMQ as it appears to be part of the Device Tree bindings * Fix ordering of the files in the Makefile The following is an automated git shortlog grouped by driver: intel: - Fix a glitch when updating IRQ flags on a preconfigured line - fix unexpected interrupt Place correctly CONFIG_PINCTRL_ST in the Makefile: - Place correctly CONFIG_PINCTRL_ST in the Makefile zynqmp: - Revert "Unify pin naming" -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAmH0HOUACgkQb7wzTHR8 rCimng/+PpXu4kAi70sI8NMfAma0LT2LggFDaknWvX4GXB+FzlzTGHNTIma67pqS hfBZ4+VPO2Fb96sH+cIgMGPozph9hPlOO6QuaaUuCej9BRhqASuPVwOK9TCHYs2T 6qAiUpqgqMd2zj9GyQ3oxZfQdSB1vvcQ/4pkMBusYwH/TTOnVN4MTD8jMaqPT1Zn 66kzoFo3Pq8ajM/eWzRvsimhJ9ql1VFTChWoCknvBBwWDX3YlG/3jiWQPxG5wJ5t vshhCMGgO/fglsQtTsDQysL3oa6SAqx6jeEekbu9XqirHJiwv0V3YG3tXccGGKs+ YqhYeqSc124Xw7pA7TAmvcksCX9R76Tgbr9crJkhDUqMA++UpP9xTIdQqRpldotd IunmA0JLkE2PK/VX+ZDI3fsj2tPU3wIUci1tfJegr6MICoLfxiGoIxhXd7x0qvaF GV8u2YJ0sOqp4S5pGZOz9MmSihTC5ScoNDuyg1dZbFI1juibIDPkOtkdO0G92Pyg 84x8Tuicg2cJKgINUeJsnis2m05hG0ZrEES2FUKEOxAHJd9UIj5bi5b1J3UxCafj U2dtBOXPNXk+jTN7Uwtbc2XCt0M66nZBXIEl2AOvrY/KDmRAycZSoV452bOxZqtE pKXLfv/qGAm3wSNfuqwMqSqpLRYCf04V1uMc9Rgh8W2F9QIGYhI= =RX4p -----END PGP SIGNATURE----- Merge tag 'intel-pinctrl-v5.17-4' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into fixes intel-pinctrl for v5.17-4 * Couple of fixes on how Intel driver handles an interrupt * Revert pin renaming change in ZynqMQ as it appears to be part of the Device Tree bindings * Fix ordering of the files in the Makefile The following is an automated git shortlog grouped by driver: intel: - Fix a glitch when updating IRQ flags on a preconfigured line - fix unexpected interrupt Place correctly CONFIG_PINCTRL_ST in the Makefile: - Place correctly CONFIG_PINCTRL_ST in the Makefile zynqmp: - Revert "Unify pin naming"
This commit is contained in:
commit
474932a3b2
@ -42,9 +42,9 @@ obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
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obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o
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obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
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obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
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obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
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obj-$(CONFIG_PINCTRL_STARFIVE) += pinctrl-starfive.o
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obj-$(CONFIG_PINCTRL_STMFX) += pinctrl-stmfx.o
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obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
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obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
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obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
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obj-$(CONFIG_PINCTRL_THUNDERBAY) += pinctrl-thunderbay.o
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@ -451,8 +451,8 @@ static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
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value &= ~PADCFG0_PMODE_MASK;
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value |= PADCFG0_PMODE_GPIO;
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/* Disable input and output buffers */
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value |= PADCFG0_GPIORXDIS;
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/* Disable TX buffer and enable RX (this will be input) */
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value &= ~PADCFG0_GPIORXDIS;
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value |= PADCFG0_GPIOTXDIS;
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/* Disable SCI/SMI/NMI generation */
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@ -497,9 +497,6 @@ static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
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intel_gpio_set_gpio_mode(padcfg0);
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/* Disable TX buffer and enable RX (this will be input) */
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__intel_gpio_set_direction(padcfg0, true);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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return 0;
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@ -1115,9 +1112,6 @@ static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
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intel_gpio_set_gpio_mode(reg);
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/* Disable TX buffer and enable RX (this will be input) */
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__intel_gpio_set_direction(reg, true);
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value = readl(reg);
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value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
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@ -1216,6 +1210,39 @@ static irqreturn_t intel_gpio_irq(int irq, void *data)
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return IRQ_RETVAL(ret);
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}
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static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
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{
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int i;
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for (i = 0; i < pctrl->ncommunities; i++) {
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const struct intel_community *community;
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void __iomem *base;
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unsigned int gpp;
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community = &pctrl->communities[i];
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base = community->regs;
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for (gpp = 0; gpp < community->ngpps; gpp++) {
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/* Mask and clear all interrupts */
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writel(0, base + community->ie_offset + gpp * 4);
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writel(0xffff, base + community->is_offset + gpp * 4);
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}
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}
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}
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static int intel_gpio_irq_init_hw(struct gpio_chip *gc)
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{
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struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
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/*
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* Make sure the interrupt lines are in a proper state before
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* further configuration.
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*/
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intel_gpio_irq_init(pctrl);
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return 0;
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}
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static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl,
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const struct intel_community *community)
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{
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@ -1320,6 +1347,7 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
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girq->num_parents = 0;
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_bad_irq;
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girq->init_hw = intel_gpio_irq_init_hw;
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ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
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if (ret) {
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@ -1695,26 +1723,6 @@ int intel_pinctrl_suspend_noirq(struct device *dev)
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}
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EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq);
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static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
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{
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size_t i;
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for (i = 0; i < pctrl->ncommunities; i++) {
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const struct intel_community *community;
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void __iomem *base;
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unsigned int gpp;
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community = &pctrl->communities[i];
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base = community->regs;
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for (gpp = 0; gpp < community->ngpps; gpp++) {
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/* Mask and clear all interrupts */
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writel(0, base + community->ie_offset + gpp * 4);
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writel(0xffff, base + community->is_offset + gpp * 4);
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}
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}
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}
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static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value)
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{
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u32 curr, updated;
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@ -809,7 +809,6 @@ static int zynqmp_pinctrl_prepare_pin_desc(struct device *dev,
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unsigned int *npins)
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{
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struct pinctrl_pin_desc *pins, *pin;
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char **pin_names;
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int ret;
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int i;
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@ -821,14 +820,13 @@ static int zynqmp_pinctrl_prepare_pin_desc(struct device *dev,
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if (!pins)
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return -ENOMEM;
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pin_names = devm_kasprintf_strarray(dev, ZYNQMP_PIN_PREFIX, *npins);
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if (IS_ERR(pin_names))
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return PTR_ERR(pin_names);
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for (i = 0; i < *npins; i++) {
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pin = &pins[i];
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pin->number = i;
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pin->name = pin_names[i];
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pin->name = devm_kasprintf(dev, GFP_KERNEL, "%s%d",
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ZYNQMP_PIN_PREFIX, i);
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if (!pin->name)
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return -ENOMEM;
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}
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*zynqmp_pins = pins;
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