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Merge branch 'exynos-dp-next' of git://github.com/jingoo/linux into for-linus
Exynos DP changes for the 3.8 merge window. - Device Tree support for Samsung Exynos DP - SW Link training is cleaned up. - HPD interrupt is supported. * 'exynos-dp-next' of git://github.com/jingoo/linux: video: exynos_dp: remove redundant parameters video: exynos_dp: Fix incorrect setting for INT_CTL video: exynos_dp: Reset and initialize DP before requesting irq video: exynos_dp: Enable hotplug interrupts video: exynos_dp: Move hotplug into a workqueue video: exynos_dp: Remove sink control to D0 video: exynos_dp: Fix bug when checking dp->irq video: exynos_dp: Improve EDID error handling video: exynos_dp: Get pll lock before pattern set video: exynos_dp: Clean up SW link training video: exynos_dp: Check DPCD return codes video: exynos_dp: device tree documentation video: exynos_dp: Add device tree support to DP driver
This commit is contained in:
Tomi Valkeinen
commit
473af20f70
80
Documentation/devicetree/bindings/video/exynos_dp.txt
Normal file
80
Documentation/devicetree/bindings/video/exynos_dp.txt
Normal file
@ -0,0 +1,80 @@
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The Exynos display port interface should be configured based on
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the type of panel connected to it.
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We use two nodes:
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-dp-controller node
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-dptx-phy node(defined inside dp-controller node)
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For the DP-PHY initialization, we use the dptx-phy node.
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Required properties for dptx-phy:
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-reg:
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Base address of DP PHY register.
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-samsung,enable-mask:
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The bit-mask used to enable/disable DP PHY.
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For the Panel initialization, we read data from dp-controller node.
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Required properties for dp-controller:
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-compatible:
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should be "samsung,exynos5-dp".
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-reg:
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physical base address of the controller and length
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of memory mapped region.
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-interrupts:
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interrupt combiner values.
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-interrupt-parent:
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phandle to Interrupt combiner node.
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-samsung,color-space:
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input video data format.
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COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
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-samsung,dynamic-range:
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dynamic range for input video data.
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VESA = 0, CEA = 1
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-samsung,ycbcr-coeff:
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YCbCr co-efficients for input video.
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COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
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-samsung,color-depth:
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number of bits per colour component.
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COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
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-samsung,link-rate:
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link rate supported by the panel.
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LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
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-samsung,lane-count:
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number of lanes supported by the panel.
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LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
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Optional properties for dp-controller:
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-interlaced:
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interlace scan mode.
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Progressive if defined, Interlaced if not defined
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-vsync-active-high:
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VSYNC polarity configuration.
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High if defined, Low if not defined
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-hsync-active-high:
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HSYNC polarity configuration.
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High if defined, Low if not defined
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Example:
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SOC specific portion:
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dp-controller {
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compatible = "samsung,exynos5-dp";
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reg = <0x145b0000 0x10000>;
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interrupts = <10 3>;
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interrupt-parent = <&combiner>;
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dptx-phy {
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reg = <0x10040720>;
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samsung,enable-mask = <1>;
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};
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};
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Board Specific portion:
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dp-controller {
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samsung,color-space = <0>;
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samsung,dynamic-range = <0>;
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samsung,ycbcr-coeff = <0>;
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samsung,color-depth = <1>;
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samsung,link-rate = <0x0a>;
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samsung,lane-count = <4>;
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};
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@ -18,6 +18,7 @@
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <video/exynos_dp.h>
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@ -48,10 +49,6 @@ static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
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{
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int timeout_loop = 0;
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exynos_dp_init_hpd(dp);
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usleep_range(200, 210);
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while (exynos_dp_get_plug_in_status(dp) != 0) {
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timeout_loop++;
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if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
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@ -90,9 +87,11 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
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*/
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/* Read Extension Flag, Number of 128-byte EDID extension blocks */
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exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
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retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
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EDID_EXTENSION_FLAG,
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&extend_block);
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if (retval)
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return retval;
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if (extend_block > 0) {
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dev_dbg(dp->dev, "EDID data includes a single extension!\n");
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@ -181,14 +180,15 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
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int retval;
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/* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
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exynos_dp_read_bytes_from_dpcd(dp,
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DPCD_ADDR_DPCD_REV,
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12, buf);
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retval = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_DPCD_REV,
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12, buf);
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if (retval)
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return retval;
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/* Read EDID */
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for (i = 0; i < 3; i++) {
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retval = exynos_dp_read_edid(dp);
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if (retval == 0)
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if (!retval)
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break;
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}
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@ -261,11 +261,10 @@ static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
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}
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}
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static void exynos_dp_link_start(struct exynos_dp_device *dp)
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static int exynos_dp_link_start(struct exynos_dp_device *dp)
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{
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u8 buf[4];
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int lane;
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int lane_count;
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int lane, lane_count, pll_tries, retval;
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lane_count = dp->link_train.lane_count;
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@ -275,10 +274,6 @@ static void exynos_dp_link_start(struct exynos_dp_device *dp)
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for (lane = 0; lane < lane_count; lane++)
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dp->link_train.cr_loop[lane] = 0;
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/* Set sink to D0 (Sink Not Ready) mode. */
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exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE,
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DPCD_SET_POWER_STATE_D0);
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/* Set link rate and count as you want to establish*/
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exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
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exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
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@ -286,29 +281,46 @@ static void exynos_dp_link_start(struct exynos_dp_device *dp)
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/* Setup RX configuration */
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buf[0] = dp->link_train.link_rate;
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buf[1] = dp->link_train.lane_count;
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exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET,
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retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET,
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2, buf);
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if (retval)
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return retval;
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/* Set TX pre-emphasis to minimum */
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for (lane = 0; lane < lane_count; lane++)
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exynos_dp_set_lane_lane_pre_emphasis(dp,
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PRE_EMPHASIS_LEVEL_0, lane);
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/* Wait for PLL lock */
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pll_tries = 0;
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while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
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if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
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dev_err(dp->dev, "Wait for PLL lock timed out\n");
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return -ETIMEDOUT;
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}
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pll_tries++;
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usleep_range(90, 120);
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}
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/* Set training pattern 1 */
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exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
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/* Set RX training pattern */
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exynos_dp_write_byte_to_dpcd(dp,
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DPCD_ADDR_TRAINING_PATTERN_SET,
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DPCD_SCRAMBLING_DISABLED |
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DPCD_TRAINING_PATTERN_1);
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retval = exynos_dp_write_byte_to_dpcd(dp,
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DPCD_ADDR_TRAINING_PATTERN_SET,
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DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1);
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if (retval)
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return retval;
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for (lane = 0; lane < lane_count; lane++)
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buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
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DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
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exynos_dp_write_bytes_to_dpcd(dp,
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DPCD_ADDR_TRAINING_LANE0_SET,
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lane_count, buf);
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retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET,
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lane_count, buf);
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return retval;
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}
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static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
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@ -332,18 +344,17 @@ static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
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return 0;
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}
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static int exynos_dp_channel_eq_ok(u8 link_align[3], int lane_count)
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static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
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int lane_count)
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{
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int lane;
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u8 lane_align;
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u8 lane_status;
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lane_align = link_align[2];
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if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
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if ((link_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
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return -EINVAL;
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for (lane = 0; lane < lane_count; lane++) {
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lane_status = exynos_dp_get_lane_status(link_align, lane);
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lane_status = exynos_dp_get_lane_status(link_status, lane);
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lane_status &= DPCD_CHANNEL_EQ_BITS;
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if (lane_status != DPCD_CHANNEL_EQ_BITS)
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return -EINVAL;
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@ -427,60 +438,60 @@ static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
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dp->link_train.lt_state = FAILED;
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}
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static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
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u8 adjust_request[2])
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{
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int lane, lane_count;
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u8 voltage_swing, pre_emphasis, training_lane;
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lane_count = dp->link_train.lane_count;
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for (lane = 0; lane < lane_count; lane++) {
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voltage_swing = exynos_dp_get_adjust_request_voltage(
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adjust_request, lane);
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pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
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adjust_request, lane);
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training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
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DPCD_PRE_EMPHASIS_SET(pre_emphasis);
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if (voltage_swing == VOLTAGE_LEVEL_3)
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training_lane |= DPCD_MAX_SWING_REACHED;
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if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
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training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
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dp->link_train.training_lane[lane] = training_lane;
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}
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}
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static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
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{
|
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u8 link_status[2];
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int lane;
|
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int lane_count;
|
||||
|
||||
u8 adjust_request[2];
|
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u8 voltage_swing;
|
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u8 pre_emphasis;
|
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u8 training_lane;
|
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int lane, lane_count, retval;
|
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u8 voltage_swing, pre_emphasis, training_lane;
|
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u8 link_status[2], adjust_request[2];
|
||||
|
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usleep_range(100, 101);
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|
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lane_count = dp->link_train.lane_count;
|
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|
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exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
|
||||
2, link_status);
|
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retval = exynos_dp_read_bytes_from_dpcd(dp,
|
||||
DPCD_ADDR_LANE0_1_STATUS, 2, link_status);
|
||||
if (retval)
|
||||
return retval;
|
||||
|
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retval = exynos_dp_read_bytes_from_dpcd(dp,
|
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DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
|
||||
if (retval)
|
||||
return retval;
|
||||
|
||||
if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
|
||||
/* set training pattern 2 for EQ */
|
||||
exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
|
||||
|
||||
for (lane = 0; lane < lane_count; lane++) {
|
||||
exynos_dp_read_bytes_from_dpcd(dp,
|
||||
DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
|
||||
2, adjust_request);
|
||||
voltage_swing = exynos_dp_get_adjust_request_voltage(
|
||||
adjust_request, lane);
|
||||
pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
|
||||
adjust_request, lane);
|
||||
training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
|
||||
DPCD_PRE_EMPHASIS_SET(pre_emphasis);
|
||||
|
||||
if (voltage_swing == VOLTAGE_LEVEL_3)
|
||||
training_lane |= DPCD_MAX_SWING_REACHED;
|
||||
if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
|
||||
training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
|
||||
|
||||
dp->link_train.training_lane[lane] = training_lane;
|
||||
|
||||
exynos_dp_set_lane_link_training(dp,
|
||||
dp->link_train.training_lane[lane],
|
||||
lane);
|
||||
}
|
||||
|
||||
exynos_dp_write_byte_to_dpcd(dp,
|
||||
DPCD_ADDR_TRAINING_PATTERN_SET,
|
||||
DPCD_SCRAMBLING_DISABLED |
|
||||
DPCD_TRAINING_PATTERN_2);
|
||||
|
||||
exynos_dp_write_bytes_to_dpcd(dp,
|
||||
DPCD_ADDR_TRAINING_LANE0_SET,
|
||||
lane_count,
|
||||
dp->link_train.training_lane);
|
||||
retval = exynos_dp_write_byte_to_dpcd(dp,
|
||||
DPCD_ADDR_TRAINING_PATTERN_SET,
|
||||
DPCD_SCRAMBLING_DISABLED |
|
||||
DPCD_TRAINING_PATTERN_2);
|
||||
if (retval)
|
||||
return retval;
|
||||
|
||||
dev_info(dp->dev, "Link Training Clock Recovery success\n");
|
||||
dp->link_train.lt_state = EQUALIZER_TRAINING;
|
||||
@ -488,152 +499,116 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
|
||||
for (lane = 0; lane < lane_count; lane++) {
|
||||
training_lane = exynos_dp_get_lane_link_training(
|
||||
dp, lane);
|
||||
exynos_dp_read_bytes_from_dpcd(dp,
|
||||
DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
|
||||
2, adjust_request);
|
||||
voltage_swing = exynos_dp_get_adjust_request_voltage(
|
||||
adjust_request, lane);
|
||||
pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
|
||||
adjust_request, lane);
|
||||
|
||||
if (voltage_swing == VOLTAGE_LEVEL_3 ||
|
||||
pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
|
||||
dev_err(dp->dev, "voltage or pre emphasis reached max level\n");
|
||||
goto reduce_link_rate;
|
||||
}
|
||||
|
||||
if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
|
||||
voltage_swing) &&
|
||||
(DPCD_PRE_EMPHASIS_GET(training_lane) ==
|
||||
pre_emphasis)) {
|
||||
if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
|
||||
voltage_swing &&
|
||||
DPCD_PRE_EMPHASIS_GET(training_lane) ==
|
||||
pre_emphasis)
|
||||
dp->link_train.cr_loop[lane]++;
|
||||
if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP) {
|
||||
dev_err(dp->dev, "CR Max loop\n");
|
||||
goto reduce_link_rate;
|
||||
}
|
||||
|
||||
if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
|
||||
voltage_swing == VOLTAGE_LEVEL_3 ||
|
||||
pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
|
||||
dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
|
||||
dp->link_train.cr_loop[lane],
|
||||
voltage_swing, pre_emphasis);
|
||||
exynos_dp_reduce_link_rate(dp);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
|
||||
DPCD_PRE_EMPHASIS_SET(pre_emphasis);
|
||||
|
||||
if (voltage_swing == VOLTAGE_LEVEL_3)
|
||||
training_lane |= DPCD_MAX_SWING_REACHED;
|
||||
if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
|
||||
training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
|
||||
|
||||
dp->link_train.training_lane[lane] = training_lane;
|
||||
|
||||
exynos_dp_set_lane_link_training(dp,
|
||||
dp->link_train.training_lane[lane], lane);
|
||||
}
|
||||
|
||||
exynos_dp_write_bytes_to_dpcd(dp,
|
||||
DPCD_ADDR_TRAINING_LANE0_SET,
|
||||
lane_count,
|
||||
dp->link_train.training_lane);
|
||||
}
|
||||
|
||||
return 0;
|
||||
exynos_dp_get_adjust_training_lane(dp, adjust_request);
|
||||
|
||||
reduce_link_rate:
|
||||
exynos_dp_reduce_link_rate(dp);
|
||||
return -EIO;
|
||||
for (lane = 0; lane < lane_count; lane++)
|
||||
exynos_dp_set_lane_link_training(dp,
|
||||
dp->link_train.training_lane[lane], lane);
|
||||
|
||||
retval = exynos_dp_write_bytes_to_dpcd(dp,
|
||||
DPCD_ADDR_TRAINING_LANE0_SET, lane_count,
|
||||
dp->link_train.training_lane);
|
||||
if (retval)
|
||||
return retval;
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
|
||||
{
|
||||
u8 link_status[2];
|
||||
u8 link_align[3];
|
||||
int lane;
|
||||
int lane_count;
|
||||
int lane, lane_count, retval;
|
||||
u32 reg;
|
||||
|
||||
u8 adjust_request[2];
|
||||
u8 voltage_swing;
|
||||
u8 pre_emphasis;
|
||||
u8 training_lane;
|
||||
u8 link_align, link_status[2], adjust_request[2];
|
||||
|
||||
usleep_range(400, 401);
|
||||
|
||||
lane_count = dp->link_train.lane_count;
|
||||
|
||||
exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
|
||||
2, link_status);
|
||||
retval = exynos_dp_read_bytes_from_dpcd(dp,
|
||||
DPCD_ADDR_LANE0_1_STATUS, 2, link_status);
|
||||
if (retval)
|
||||
return retval;
|
||||
|
||||
if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
|
||||
link_align[0] = link_status[0];
|
||||
link_align[1] = link_status[1];
|
||||
|
||||
exynos_dp_read_byte_from_dpcd(dp,
|
||||
DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED,
|
||||
&link_align[2]);
|
||||
|
||||
for (lane = 0; lane < lane_count; lane++) {
|
||||
exynos_dp_read_bytes_from_dpcd(dp,
|
||||
DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
|
||||
2, adjust_request);
|
||||
voltage_swing = exynos_dp_get_adjust_request_voltage(
|
||||
adjust_request, lane);
|
||||
pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
|
||||
adjust_request, lane);
|
||||
training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
|
||||
DPCD_PRE_EMPHASIS_SET(pre_emphasis);
|
||||
|
||||
if (voltage_swing == VOLTAGE_LEVEL_3)
|
||||
training_lane |= DPCD_MAX_SWING_REACHED;
|
||||
if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
|
||||
training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
|
||||
|
||||
dp->link_train.training_lane[lane] = training_lane;
|
||||
}
|
||||
|
||||
if (exynos_dp_channel_eq_ok(link_align, lane_count) == 0) {
|
||||
/* traing pattern Set to Normal */
|
||||
exynos_dp_training_pattern_dis(dp);
|
||||
|
||||
dev_info(dp->dev, "Link Training success!\n");
|
||||
|
||||
exynos_dp_get_link_bandwidth(dp, ®);
|
||||
dp->link_train.link_rate = reg;
|
||||
dev_dbg(dp->dev, "final bandwidth = %.2x\n",
|
||||
dp->link_train.link_rate);
|
||||
|
||||
exynos_dp_get_lane_count(dp, ®);
|
||||
dp->link_train.lane_count = reg;
|
||||
dev_dbg(dp->dev, "final lane count = %.2x\n",
|
||||
dp->link_train.lane_count);
|
||||
|
||||
/* set enhanced mode if available */
|
||||
exynos_dp_set_enhanced_mode(dp);
|
||||
dp->link_train.lt_state = FINISHED;
|
||||
} else {
|
||||
/* not all locked */
|
||||
dp->link_train.eq_loop++;
|
||||
|
||||
if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
|
||||
dev_err(dp->dev, "EQ Max loop\n");
|
||||
goto reduce_link_rate;
|
||||
}
|
||||
|
||||
for (lane = 0; lane < lane_count; lane++)
|
||||
exynos_dp_set_lane_link_training(dp,
|
||||
dp->link_train.training_lane[lane],
|
||||
lane);
|
||||
|
||||
exynos_dp_write_bytes_to_dpcd(dp,
|
||||
DPCD_ADDR_TRAINING_LANE0_SET,
|
||||
lane_count,
|
||||
dp->link_train.training_lane);
|
||||
}
|
||||
} else {
|
||||
goto reduce_link_rate;
|
||||
if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
|
||||
exynos_dp_reduce_link_rate(dp);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
retval = exynos_dp_read_bytes_from_dpcd(dp,
|
||||
DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
|
||||
if (retval)
|
||||
return retval;
|
||||
|
||||
reduce_link_rate:
|
||||
exynos_dp_reduce_link_rate(dp);
|
||||
return -EIO;
|
||||
retval = exynos_dp_read_byte_from_dpcd(dp,
|
||||
DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED, &link_align);
|
||||
if (retval)
|
||||
return retval;
|
||||
|
||||
exynos_dp_get_adjust_training_lane(dp, adjust_request);
|
||||
|
||||
if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) {
|
||||
/* traing pattern Set to Normal */
|
||||
exynos_dp_training_pattern_dis(dp);
|
||||
|
||||
dev_info(dp->dev, "Link Training success!\n");
|
||||
|
||||
exynos_dp_get_link_bandwidth(dp, ®);
|
||||
dp->link_train.link_rate = reg;
|
||||
dev_dbg(dp->dev, "final bandwidth = %.2x\n",
|
||||
dp->link_train.link_rate);
|
||||
|
||||
exynos_dp_get_lane_count(dp, ®);
|
||||
dp->link_train.lane_count = reg;
|
||||
dev_dbg(dp->dev, "final lane count = %.2x\n",
|
||||
dp->link_train.lane_count);
|
||||
|
||||
/* set enhanced mode if available */
|
||||
exynos_dp_set_enhanced_mode(dp);
|
||||
dp->link_train.lt_state = FINISHED;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* not all locked */
|
||||
dp->link_train.eq_loop++;
|
||||
|
||||
if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
|
||||
dev_err(dp->dev, "EQ Max loop\n");
|
||||
exynos_dp_reduce_link_rate(dp);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
for (lane = 0; lane < lane_count; lane++)
|
||||
exynos_dp_set_lane_link_training(dp,
|
||||
dp->link_train.training_lane[lane], lane);
|
||||
|
||||
retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET,
|
||||
lane_count, dp->link_train.training_lane);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
|
||||
@ -701,16 +676,17 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp,
|
||||
|
||||
static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
|
||||
{
|
||||
int retval = 0;
|
||||
int training_finished = 0;
|
||||
int retval = 0, training_finished = 0;
|
||||
|
||||
dp->link_train.lt_state = START;
|
||||
|
||||
/* Process here */
|
||||
while (!training_finished) {
|
||||
while (!retval && !training_finished) {
|
||||
switch (dp->link_train.lt_state) {
|
||||
case START:
|
||||
exynos_dp_link_start(dp);
|
||||
retval = exynos_dp_link_start(dp);
|
||||
if (retval)
|
||||
dev_err(dp->dev, "LT link start failed!\n");
|
||||
break;
|
||||
case CLOCK_RECOVERY:
|
||||
retval = exynos_dp_process_clock_recovery(dp);
|
||||
@ -729,6 +705,8 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
|
||||
return -EREMOTEIO;
|
||||
}
|
||||
}
|
||||
if (retval)
|
||||
dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
|
||||
|
||||
return retval;
|
||||
}
|
||||
@ -752,19 +730,15 @@ static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int exynos_dp_config_video(struct exynos_dp_device *dp,
|
||||
struct video_info *video_info)
|
||||
static int exynos_dp_config_video(struct exynos_dp_device *dp)
|
||||
{
|
||||
int retval = 0;
|
||||
int timeout_loop = 0;
|
||||
int done_count = 0;
|
||||
|
||||
exynos_dp_config_video_slave_mode(dp, video_info);
|
||||
exynos_dp_config_video_slave_mode(dp);
|
||||
|
||||
exynos_dp_set_video_color_format(dp, video_info->color_depth,
|
||||
video_info->color_space,
|
||||
video_info->dynamic_range,
|
||||
video_info->ycbcr_coeff);
|
||||
exynos_dp_set_video_color_format(dp);
|
||||
|
||||
if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
|
||||
dev_err(dp->dev, "PLL is not locked yet.\n");
|
||||
@ -852,10 +826,213 @@ static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
|
||||
{
|
||||
struct exynos_dp_device *dp = arg;
|
||||
|
||||
dev_err(dp->dev, "exynos_dp_irq_handler\n");
|
||||
enum dp_irq_type irq_type;
|
||||
|
||||
irq_type = exynos_dp_get_irq_type(dp);
|
||||
switch (irq_type) {
|
||||
case DP_IRQ_TYPE_HP_CABLE_IN:
|
||||
dev_dbg(dp->dev, "Received irq - cable in\n");
|
||||
schedule_work(&dp->hotplug_work);
|
||||
exynos_dp_clear_hotplug_interrupts(dp);
|
||||
break;
|
||||
case DP_IRQ_TYPE_HP_CABLE_OUT:
|
||||
dev_dbg(dp->dev, "Received irq - cable out\n");
|
||||
exynos_dp_clear_hotplug_interrupts(dp);
|
||||
break;
|
||||
case DP_IRQ_TYPE_HP_CHANGE:
|
||||
/*
|
||||
* We get these change notifications once in a while, but there
|
||||
* is nothing we can do with them. Just ignore it for now and
|
||||
* only handle cable changes.
|
||||
*/
|
||||
dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
|
||||
exynos_dp_clear_hotplug_interrupts(dp);
|
||||
break;
|
||||
default:
|
||||
dev_err(dp->dev, "Received irq - unknown type!\n");
|
||||
break;
|
||||
}
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void exynos_dp_hotplug(struct work_struct *work)
|
||||
{
|
||||
struct exynos_dp_device *dp;
|
||||
int ret;
|
||||
|
||||
dp = container_of(work, struct exynos_dp_device, hotplug_work);
|
||||
|
||||
ret = exynos_dp_detect_hpd(dp);
|
||||
if (ret) {
|
||||
/* Cable has been disconnected, we're done */
|
||||
return;
|
||||
}
|
||||
|
||||
ret = exynos_dp_handle_edid(dp);
|
||||
if (ret) {
|
||||
dev_err(dp->dev, "unable to handle edid\n");
|
||||
return;
|
||||
}
|
||||
|
||||
ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
|
||||
dp->video_info->link_rate);
|
||||
if (ret) {
|
||||
dev_err(dp->dev, "unable to do link train\n");
|
||||
return;
|
||||
}
|
||||
|
||||
exynos_dp_enable_scramble(dp, 1);
|
||||
exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
|
||||
exynos_dp_enable_enhanced_mode(dp, 1);
|
||||
|
||||
exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
|
||||
exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
|
||||
|
||||
exynos_dp_init_video(dp);
|
||||
ret = exynos_dp_config_video(dp);
|
||||
if (ret)
|
||||
dev_err(dp->dev, "unable to config video\n");
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static struct exynos_dp_platdata *exynos_dp_dt_parse_pdata(struct device *dev)
|
||||
{
|
||||
struct device_node *dp_node = dev->of_node;
|
||||
struct exynos_dp_platdata *pd;
|
||||
struct video_info *dp_video_config;
|
||||
|
||||
pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
|
||||
if (!pd) {
|
||||
dev_err(dev, "memory allocation for pdata failed\n");
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
dp_video_config = devm_kzalloc(dev,
|
||||
sizeof(*dp_video_config), GFP_KERNEL);
|
||||
|
||||
if (!dp_video_config) {
|
||||
dev_err(dev, "memory allocation for video config failed\n");
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
pd->video_info = dp_video_config;
|
||||
|
||||
dp_video_config->h_sync_polarity =
|
||||
of_property_read_bool(dp_node, "hsync-active-high");
|
||||
|
||||
dp_video_config->v_sync_polarity =
|
||||
of_property_read_bool(dp_node, "vsync-active-high");
|
||||
|
||||
dp_video_config->interlaced =
|
||||
of_property_read_bool(dp_node, "interlaced");
|
||||
|
||||
if (of_property_read_u32(dp_node, "samsung,color-space",
|
||||
&dp_video_config->color_space)) {
|
||||
dev_err(dev, "failed to get color-space\n");
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
if (of_property_read_u32(dp_node, "samsung,dynamic-range",
|
||||
&dp_video_config->dynamic_range)) {
|
||||
dev_err(dev, "failed to get dynamic-range\n");
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
|
||||
&dp_video_config->ycbcr_coeff)) {
|
||||
dev_err(dev, "failed to get ycbcr-coeff\n");
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
if (of_property_read_u32(dp_node, "samsung,color-depth",
|
||||
&dp_video_config->color_depth)) {
|
||||
dev_err(dev, "failed to get color-depth\n");
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
if (of_property_read_u32(dp_node, "samsung,link-rate",
|
||||
&dp_video_config->link_rate)) {
|
||||
dev_err(dev, "failed to get link-rate\n");
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
if (of_property_read_u32(dp_node, "samsung,lane-count",
|
||||
&dp_video_config->lane_count)) {
|
||||
dev_err(dev, "failed to get lane-count\n");
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
return pd;
|
||||
}
|
||||
|
||||
static int exynos_dp_dt_parse_phydata(struct exynos_dp_device *dp)
|
||||
{
|
||||
struct device_node *dp_phy_node;
|
||||
u32 phy_base;
|
||||
|
||||
dp_phy_node = of_find_node_by_name(dp->dev->of_node, "dptx-phy");
|
||||
if (!dp_phy_node) {
|
||||
dev_err(dp->dev, "could not find dptx-phy node\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (of_property_read_u32(dp_phy_node, "reg", &phy_base)) {
|
||||
dev_err(dp->dev, "faild to get reg for dptx-phy\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (of_property_read_u32(dp_phy_node, "samsung,enable-mask",
|
||||
&dp->enable_mask)) {
|
||||
dev_err(dp->dev, "faild to get enable-mask for dptx-phy\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
dp->phy_addr = ioremap(phy_base, SZ_4);
|
||||
if (!dp->phy_addr) {
|
||||
dev_err(dp->dev, "failed to ioremap dp-phy\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void exynos_dp_phy_init(struct exynos_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
reg = __raw_readl(dp->phy_addr);
|
||||
reg |= dp->enable_mask;
|
||||
__raw_writel(reg, dp->phy_addr);
|
||||
}
|
||||
|
||||
static void exynos_dp_phy_exit(struct exynos_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
reg = __raw_readl(dp->phy_addr);
|
||||
reg &= ~(dp->enable_mask);
|
||||
__raw_writel(reg, dp->phy_addr);
|
||||
}
|
||||
#else
|
||||
static struct exynos_dp_platdata *exynos_dp_dt_parse_pdata(struct device *dev)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int exynos_dp_dt_parse_phydata(struct exynos_dp_device *dp)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static void exynos_dp_phy_init(struct exynos_dp_device *dp)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
static void exynos_dp_phy_exit(struct exynos_dp_device *dp)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif /* CONFIG_OF */
|
||||
|
||||
static int __devinit exynos_dp_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
@ -864,12 +1041,6 @@ static int __devinit exynos_dp_probe(struct platform_device *pdev)
|
||||
|
||||
int ret = 0;
|
||||
|
||||
pdata = pdev->dev.platform_data;
|
||||
if (!pdata) {
|
||||
dev_err(&pdev->dev, "no platform data\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
|
||||
GFP_KERNEL);
|
||||
if (!dp) {
|
||||
@ -879,6 +1050,22 @@ static int __devinit exynos_dp_probe(struct platform_device *pdev)
|
||||
|
||||
dp->dev = &pdev->dev;
|
||||
|
||||
if (pdev->dev.of_node) {
|
||||
pdata = exynos_dp_dt_parse_pdata(&pdev->dev);
|
||||
if (IS_ERR(pdata))
|
||||
return PTR_ERR(pdata);
|
||||
|
||||
ret = exynos_dp_dt_parse_phydata(dp);
|
||||
if (ret)
|
||||
return ret;
|
||||
} else {
|
||||
pdata = pdev->dev.platform_data;
|
||||
if (!pdata) {
|
||||
dev_err(&pdev->dev, "no platform data\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
dp->clock = devm_clk_get(&pdev->dev, "dp");
|
||||
if (IS_ERR(dp->clock)) {
|
||||
dev_err(&pdev->dev, "failed to get clock\n");
|
||||
@ -896,11 +1083,25 @@ static int __devinit exynos_dp_probe(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
dp->irq = platform_get_irq(pdev, 0);
|
||||
if (!dp->irq) {
|
||||
if (dp->irq == -ENXIO) {
|
||||
dev_err(&pdev->dev, "failed to get irq\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
|
||||
|
||||
dp->video_info = pdata->video_info;
|
||||
|
||||
if (pdev->dev.of_node) {
|
||||
if (dp->phy_addr)
|
||||
exynos_dp_phy_init(dp);
|
||||
} else {
|
||||
if (pdata->phy_init)
|
||||
pdata->phy_init();
|
||||
}
|
||||
|
||||
exynos_dp_init_dp(dp);
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler, 0,
|
||||
"exynos-dp", dp);
|
||||
if (ret) {
|
||||
@ -908,41 +1109,6 @@ static int __devinit exynos_dp_probe(struct platform_device *pdev)
|
||||
return ret;
|
||||
}
|
||||
|
||||
dp->video_info = pdata->video_info;
|
||||
if (pdata->phy_init)
|
||||
pdata->phy_init();
|
||||
|
||||
exynos_dp_init_dp(dp);
|
||||
|
||||
ret = exynos_dp_detect_hpd(dp);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "unable to detect hpd\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
exynos_dp_handle_edid(dp);
|
||||
|
||||
ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
|
||||
dp->video_info->link_rate);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "unable to do link train\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
exynos_dp_enable_scramble(dp, 1);
|
||||
exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
|
||||
exynos_dp_enable_enhanced_mode(dp, 1);
|
||||
|
||||
exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
|
||||
exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
|
||||
|
||||
exynos_dp_init_video(dp);
|
||||
ret = exynos_dp_config_video(dp, dp->video_info);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "unable to config video\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, dp);
|
||||
|
||||
return 0;
|
||||
@ -953,23 +1119,41 @@ static int __devexit exynos_dp_remove(struct platform_device *pdev)
|
||||
struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
|
||||
struct exynos_dp_device *dp = platform_get_drvdata(pdev);
|
||||
|
||||
if (pdata && pdata->phy_exit)
|
||||
pdata->phy_exit();
|
||||
disable_irq(dp->irq);
|
||||
|
||||
if (work_pending(&dp->hotplug_work))
|
||||
flush_work(&dp->hotplug_work);
|
||||
|
||||
if (pdev->dev.of_node) {
|
||||
if (dp->phy_addr)
|
||||
exynos_dp_phy_exit(dp);
|
||||
} else {
|
||||
if (pdata->phy_exit)
|
||||
pdata->phy_exit();
|
||||
}
|
||||
|
||||
clk_disable_unprepare(dp->clock);
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int exynos_dp_suspend(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
|
||||
struct exynos_dp_device *dp = platform_get_drvdata(pdev);
|
||||
struct exynos_dp_platdata *pdata = dev->platform_data;
|
||||
struct exynos_dp_device *dp = dev_get_drvdata(dev);
|
||||
|
||||
if (pdata && pdata->phy_exit)
|
||||
pdata->phy_exit();
|
||||
if (work_pending(&dp->hotplug_work))
|
||||
flush_work(&dp->hotplug_work);
|
||||
|
||||
if (dev->of_node) {
|
||||
if (dp->phy_addr)
|
||||
exynos_dp_phy_exit(dp);
|
||||
} else {
|
||||
if (pdata->phy_exit)
|
||||
pdata->phy_exit();
|
||||
}
|
||||
|
||||
clk_disable_unprepare(dp->clock);
|
||||
|
||||
@ -978,32 +1162,22 @@ static int exynos_dp_suspend(struct device *dev)
|
||||
|
||||
static int exynos_dp_resume(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
|
||||
struct exynos_dp_device *dp = platform_get_drvdata(pdev);
|
||||
struct exynos_dp_platdata *pdata = dev->platform_data;
|
||||
struct exynos_dp_device *dp = dev_get_drvdata(dev);
|
||||
|
||||
if (pdata && pdata->phy_init)
|
||||
pdata->phy_init();
|
||||
if (dev->of_node) {
|
||||
if (dp->phy_addr)
|
||||
exynos_dp_phy_init(dp);
|
||||
} else {
|
||||
if (pdata->phy_init)
|
||||
pdata->phy_init();
|
||||
}
|
||||
|
||||
clk_prepare_enable(dp->clock);
|
||||
|
||||
exynos_dp_init_dp(dp);
|
||||
|
||||
exynos_dp_detect_hpd(dp);
|
||||
exynos_dp_handle_edid(dp);
|
||||
|
||||
exynos_dp_set_link_train(dp, dp->video_info->lane_count,
|
||||
dp->video_info->link_rate);
|
||||
|
||||
exynos_dp_enable_scramble(dp, 1);
|
||||
exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
|
||||
exynos_dp_enable_enhanced_mode(dp, 1);
|
||||
|
||||
exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
|
||||
exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
|
||||
|
||||
exynos_dp_init_video(dp);
|
||||
exynos_dp_config_video(dp, dp->video_info);
|
||||
enable_irq(dp->irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1013,6 +1187,12 @@ static const struct dev_pm_ops exynos_dp_pm_ops = {
|
||||
SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
|
||||
};
|
||||
|
||||
static const struct of_device_id exynos_dp_match[] = {
|
||||
{ .compatible = "samsung,exynos5-dp" },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, exynos_dp_match);
|
||||
|
||||
static struct platform_driver exynos_dp_driver = {
|
||||
.probe = exynos_dp_probe,
|
||||
.remove = __devexit_p(exynos_dp_remove),
|
||||
@ -1020,6 +1200,7 @@ static struct platform_driver exynos_dp_driver = {
|
||||
.name = "exynos-dp",
|
||||
.owner = THIS_MODULE,
|
||||
.pm = &exynos_dp_pm_ops,
|
||||
.of_match_table = of_match_ptr(exynos_dp_match),
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
@ -13,6 +13,13 @@
|
||||
#ifndef _EXYNOS_DP_CORE_H
|
||||
#define _EXYNOS_DP_CORE_H
|
||||
|
||||
enum dp_irq_type {
|
||||
DP_IRQ_TYPE_HP_CABLE_IN,
|
||||
DP_IRQ_TYPE_HP_CABLE_OUT,
|
||||
DP_IRQ_TYPE_HP_CHANGE,
|
||||
DP_IRQ_TYPE_UNKNOWN,
|
||||
};
|
||||
|
||||
struct link_train {
|
||||
int eq_loop;
|
||||
int cr_loop[4];
|
||||
@ -29,9 +36,12 @@ struct exynos_dp_device {
|
||||
struct clk *clock;
|
||||
unsigned int irq;
|
||||
void __iomem *reg_base;
|
||||
void __iomem *phy_addr;
|
||||
unsigned int enable_mask;
|
||||
|
||||
struct video_info *video_info;
|
||||
struct link_train link_train;
|
||||
struct work_struct hotplug_work;
|
||||
};
|
||||
|
||||
/* exynos_dp_reg.c */
|
||||
@ -50,6 +60,8 @@ void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
|
||||
bool enable);
|
||||
void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
|
||||
void exynos_dp_init_hpd(struct exynos_dp_device *dp);
|
||||
enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
|
||||
void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp);
|
||||
void exynos_dp_reset_aux(struct exynos_dp_device *dp);
|
||||
void exynos_dp_init_aux(struct exynos_dp_device *dp);
|
||||
int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
|
||||
@ -107,11 +119,7 @@ u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
|
||||
void exynos_dp_reset_macro(struct exynos_dp_device *dp);
|
||||
void exynos_dp_init_video(struct exynos_dp_device *dp);
|
||||
|
||||
void exynos_dp_set_video_color_format(struct exynos_dp_device *dp,
|
||||
u32 color_depth,
|
||||
u32 color_space,
|
||||
u32 dynamic_range,
|
||||
u32 ycbcr_coeff);
|
||||
void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
|
||||
int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
|
||||
void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
|
||||
enum clock_recovery_m_value_type type,
|
||||
@ -121,8 +129,7 @@ void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
|
||||
void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
|
||||
void exynos_dp_start_video(struct exynos_dp_device *dp);
|
||||
int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
|
||||
void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp,
|
||||
struct video_info *video_info);
|
||||
void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp);
|
||||
void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
|
||||
void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
|
||||
|
||||
|
||||
@ -19,11 +19,11 @@
|
||||
#include "exynos_dp_core.h"
|
||||
#include "exynos_dp_reg.h"
|
||||
|
||||
#define COMMON_INT_MASK_1 (0)
|
||||
#define COMMON_INT_MASK_2 (0)
|
||||
#define COMMON_INT_MASK_3 (0)
|
||||
#define COMMON_INT_MASK_4 (0)
|
||||
#define INT_STA_MASK (0)
|
||||
#define COMMON_INT_MASK_1 0
|
||||
#define COMMON_INT_MASK_2 0
|
||||
#define COMMON_INT_MASK_3 0
|
||||
#define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG)
|
||||
#define INT_STA_MASK INT_HPD
|
||||
|
||||
void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
|
||||
{
|
||||
@ -88,7 +88,7 @@ void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
|
||||
void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
|
||||
{
|
||||
/* Set interrupt pin assertion polarity as high */
|
||||
writel(INT_POL, dp->reg_base + EXYNOS_DP_INT_CTL);
|
||||
writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL);
|
||||
|
||||
/* Clear pending regisers */
|
||||
writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
|
||||
@ -324,7 +324,7 @@ void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
|
||||
writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
|
||||
}
|
||||
|
||||
void exynos_dp_init_hpd(struct exynos_dp_device *dp)
|
||||
void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
@ -333,12 +333,38 @@ void exynos_dp_init_hpd(struct exynos_dp_device *dp)
|
||||
|
||||
reg = INT_HPD;
|
||||
writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
|
||||
}
|
||||
|
||||
void exynos_dp_init_hpd(struct exynos_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
exynos_dp_clear_hotplug_interrupts(dp);
|
||||
|
||||
reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
|
||||
reg &= ~(F_HPD | HPD_CTRL);
|
||||
writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
|
||||
}
|
||||
|
||||
enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
/* Parse hotplug interrupt status register */
|
||||
reg = readl(dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
|
||||
|
||||
if (reg & PLUG)
|
||||
return DP_IRQ_TYPE_HP_CABLE_IN;
|
||||
|
||||
if (reg & HPD_LOST)
|
||||
return DP_IRQ_TYPE_HP_CABLE_OUT;
|
||||
|
||||
if (reg & HOTPLUG_CHG)
|
||||
return DP_IRQ_TYPE_HP_CHANGE;
|
||||
|
||||
return DP_IRQ_TYPE_UNKNOWN;
|
||||
}
|
||||
|
||||
void exynos_dp_reset_aux(struct exynos_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
@ -491,7 +517,7 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
|
||||
int i;
|
||||
int retval;
|
||||
|
||||
for (i = 0; i < 10; i++) {
|
||||
for (i = 0; i < 3; i++) {
|
||||
/* Clear AUX CH data buffer */
|
||||
reg = BUF_CLR;
|
||||
writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
|
||||
@ -552,7 +578,7 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
|
||||
else
|
||||
cur_data_count = count - start_offset;
|
||||
|
||||
for (i = 0; i < 10; i++) {
|
||||
for (i = 0; i < 3; i++) {
|
||||
/* Select DPCD device address */
|
||||
reg = AUX_ADDR_7_0(reg_addr + start_offset);
|
||||
writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
|
||||
@ -617,7 +643,7 @@ int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
|
||||
cur_data_count = count - start_offset;
|
||||
|
||||
/* AUX CH Request Transaction process */
|
||||
for (i = 0; i < 10; i++) {
|
||||
for (i = 0; i < 3; i++) {
|
||||
/* Select DPCD device address */
|
||||
reg = AUX_ADDR_7_0(reg_addr + start_offset);
|
||||
writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
|
||||
@ -700,17 +726,15 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
|
||||
int i;
|
||||
int retval;
|
||||
|
||||
for (i = 0; i < 10; i++) {
|
||||
for (i = 0; i < 3; i++) {
|
||||
/* Clear AUX CH data buffer */
|
||||
reg = BUF_CLR;
|
||||
writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
|
||||
|
||||
/* Select EDID device */
|
||||
retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
|
||||
if (retval != 0) {
|
||||
dev_err(dp->dev, "Select EDID device fail!\n");
|
||||
if (retval != 0)
|
||||
continue;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set I2C transaction and read data
|
||||
@ -750,7 +774,7 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
|
||||
int retval = 0;
|
||||
|
||||
for (i = 0; i < count; i += 16) {
|
||||
for (j = 0; j < 100; j++) {
|
||||
for (j = 0; j < 3; j++) {
|
||||
/* Clear AUX CH data buffer */
|
||||
reg = BUF_CLR;
|
||||
writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
|
||||
@ -1034,24 +1058,20 @@ void exynos_dp_init_video(struct exynos_dp_device *dp)
|
||||
writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
|
||||
}
|
||||
|
||||
void exynos_dp_set_video_color_format(struct exynos_dp_device *dp,
|
||||
u32 color_depth,
|
||||
u32 color_space,
|
||||
u32 dynamic_range,
|
||||
u32 ycbcr_coeff)
|
||||
void exynos_dp_set_video_color_format(struct exynos_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
/* Configure the input color depth, color space, dynamic range */
|
||||
reg = (dynamic_range << IN_D_RANGE_SHIFT) |
|
||||
(color_depth << IN_BPC_SHIFT) |
|
||||
(color_space << IN_COLOR_F_SHIFT);
|
||||
reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
|
||||
(dp->video_info->color_depth << IN_BPC_SHIFT) |
|
||||
(dp->video_info->color_space << IN_COLOR_F_SHIFT);
|
||||
writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2);
|
||||
|
||||
/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
|
||||
reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
|
||||
reg &= ~IN_YC_COEFFI_MASK;
|
||||
if (ycbcr_coeff)
|
||||
if (dp->video_info->ycbcr_coeff)
|
||||
reg |= IN_YC_COEFFI_ITU709;
|
||||
else
|
||||
reg |= IN_YC_COEFFI_ITU601;
|
||||
@ -1178,8 +1198,7 @@ int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
|
||||
return 0;
|
||||
}
|
||||
|
||||
void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp,
|
||||
struct video_info *video_info)
|
||||
void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
@ -1190,17 +1209,17 @@ void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp,
|
||||
|
||||
reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
|
||||
reg &= ~INTERACE_SCAN_CFG;
|
||||
reg |= (video_info->interlaced << 2);
|
||||
reg |= (dp->video_info->interlaced << 2);
|
||||
writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
|
||||
|
||||
reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
|
||||
reg &= ~VSYNC_POLARITY_CFG;
|
||||
reg |= (video_info->v_sync_polarity << 1);
|
||||
reg |= (dp->video_info->v_sync_polarity << 1);
|
||||
writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
|
||||
|
||||
reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
|
||||
reg &= ~HSYNC_POLARITY_CFG;
|
||||
reg |= (video_info->h_sync_polarity << 0);
|
||||
reg |= (dp->video_info->h_sync_polarity << 0);
|
||||
writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
|
||||
|
||||
reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
|
||||
|
||||
@ -242,7 +242,8 @@
|
||||
|
||||
/* EXYNOS_DP_INT_CTL */
|
||||
#define SOFT_INT_CTRL (0x1 << 2)
|
||||
#define INT_POL (0x1 << 0)
|
||||
#define INT_POL1 (0x1 << 1)
|
||||
#define INT_POL0 (0x1 << 0)
|
||||
|
||||
/* EXYNOS_DP_SYS_CTL_1 */
|
||||
#define DET_STA (0x1 << 2)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user