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ARM: EXYNOS: Fix the incorrect hierarchy of spi controller bus clock

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The sclk_spi clock is derived currently from the first level divider
(MMCx_RATIO) which is incorrect. The output of the first level clock
is divided by a second level divider (MMCx_PRE_RATIO), the output of
which is used as the spi bus clock (sclk_spi). Fix the clock hierarchy
issues for the sclk_spi clock.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Jaswinder Singh <jaswinder.singh@linaro.org>
[kgene.kim@samsung.com: changed the name of clk for consensus]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Thomas Abraham 2012-07-14 10:53:08 +09:00 committed by Kukjin Kim
parent 4922972eca
commit 46fda15c0c
1 changed files with 42 additions and 13 deletions
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55
arch/arm/mach-exynos/clock-exynos4.c
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@ -1242,42 +1242,69 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
};
static struct clksrc_clk exynos4_clk_sclk_spi0 = {
static struct clksrc_clk exynos4_clk_mdout_spi0 = {
.clk = {
.name = "sclk_spi",
.name = "mdout_spi",
.devname = "exynos4210-spi.0",
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 16),
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
};
static struct clksrc_clk exynos4_clk_sclk_spi1 = {
static struct clksrc_clk exynos4_clk_mdout_spi1 = {
.clk = {
.name = "sclk_spi",
.name = "mdout_spi",
.devname = "exynos4210-spi.1",
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 20),
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
};
static struct clksrc_clk exynos4_clk_sclk_spi2 = {
static struct clksrc_clk exynos4_clk_mdout_spi2 = {
.clk = {
.name = "sclk_spi",
.name = "mdout_spi",
.devname = "exynos4210-spi.2",
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 24),
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
};
static struct clksrc_clk exynos4_clk_sclk_spi0 = {
.clk = {
.name = "sclk_spi",
.devname = "exynos4210-spi.0",
.parent = &exynos4_clk_mdout_spi0.clk,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 16),
},
.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
};
static struct clksrc_clk exynos4_clk_sclk_spi1 = {
.clk = {
.name = "sclk_spi",
.devname = "exynos4210-spi.1",
.parent = &exynos4_clk_mdout_spi1.clk,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 20),
},
.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
};
static struct clksrc_clk exynos4_clk_sclk_spi2 = {
.clk = {
.name = "sclk_spi",
.devname = "exynos4210-spi.2",
.parent = &exynos4_clk_mdout_spi2.clk,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 24),
},
.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
};
/* Clock initialization code */
static struct clksrc_clk *exynos4_sysclks[] = {
&exynos4_clk_mout_apll,
@ -1331,7 +1358,9 @@ static struct clksrc_clk *exynos4_clksrc_cdev[] = {
&exynos4_clk_sclk_spi0,
&exynos4_clk_sclk_spi1,
&exynos4_clk_sclk_spi2,
&exynos4_clk_mdout_spi0,
&exynos4_clk_mdout_spi1,
&exynos4_clk_mdout_spi2,
};
static struct clk_lookup exynos4_clk_lookup[] = {