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[PATCH] m32r: Update _port2addr to use NONCACHE_OFFSET
Modify _port2addr*() routines in arch/m32r/kernel/io_*.c to use NONCACHE_OFFSET instead of hard-coding of a constant address. This modification is also required to support an M3A-ZA36 FPGA eva board in case an MMU-less synthesizable m32r core is used. Signed-off-by: Hirokazu Takata <takata@linux-m32r.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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@ -32,7 +32,7 @@ extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
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static inline void *_port2addr(unsigned long port)
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{
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return (void *)(port + NONCACHE_OFFSET);
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return (void *)(port | NONCACHE_OFFSET);
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}
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#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
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@ -41,15 +41,15 @@ static inline void *__port2addr_ata(unsigned long port)
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static int dummy_reg;
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switch (port) {
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case 0x1f0: return (void *)0xac002000;
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case 0x1f1: return (void *)0xac012800;
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case 0x1f2: return (void *)0xac012002;
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case 0x1f3: return (void *)0xac012802;
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case 0x1f4: return (void *)0xac012004;
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case 0x1f5: return (void *)0xac012804;
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case 0x1f6: return (void *)0xac012006;
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case 0x1f7: return (void *)0xac012806;
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case 0x3f6: return (void *)0xac01200e;
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case 0x1f0: return (void *)(0x0c002000 | NONCACHE_OFFSET);
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case 0x1f1: return (void *)(0x0c012800 | NONCACHE_OFFSET);
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case 0x1f2: return (void *)(0x0c012002 | NONCACHE_OFFSET);
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case 0x1f3: return (void *)(0x0c012802 | NONCACHE_OFFSET);
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case 0x1f4: return (void *)(0x0c012004 | NONCACHE_OFFSET);
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case 0x1f5: return (void *)(0x0c012804 | NONCACHE_OFFSET);
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case 0x1f6: return (void *)(0x0c012006 | NONCACHE_OFFSET);
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case 0x1f7: return (void *)(0x0c012806 | NONCACHE_OFFSET);
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case 0x3f6: return (void *)(0x0c01200e | NONCACHE_OFFSET);
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default: return (void *)&dummy_reg;
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}
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}
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@ -60,8 +60,8 @@ static inline void *__port2addr_ata(unsigned long port)
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* from 0x01000000 to 0x01ffffff on physical address.
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* The base address of LAN controller(LAN91C111) is 0x300.
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*/
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#define LAN_IOSTART 0x300
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#define LAN_IOEND 0x320
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#define LAN_IOSTART (0x300 | NONCACHE_OFFSET)
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#define LAN_IOEND (0x320 | NONCACHE_OFFSET)
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static inline void *_port2addr_ne(unsigned long port)
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{
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return (void *)(port + NONCACHE_OFFSET + 0x01000000);
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@ -36,7 +36,7 @@ extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
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static inline void *_port2addr(unsigned long port)
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{
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return (void *)(port + NONCACHE_OFFSET);
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return (void *)(port | NONCACHE_OFFSET);
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}
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#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
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@ -45,15 +45,15 @@ static inline void *__port2addr_ata(unsigned long port)
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static int dummy_reg;
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switch (port) {
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case 0x1f0: return (void *)0xac002000;
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case 0x1f1: return (void *)0xac012800;
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case 0x1f2: return (void *)0xac012002;
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case 0x1f3: return (void *)0xac012802;
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case 0x1f4: return (void *)0xac012004;
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case 0x1f5: return (void *)0xac012804;
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case 0x1f6: return (void *)0xac012006;
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case 0x1f7: return (void *)0xac012806;
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case 0x3f6: return (void *)0xac01200e;
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case 0x1f0: return (void *)(0x0c002000 | NONCACHE_OFFSET);
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case 0x1f1: return (void *)(0x0c012800 | NONCACHE_OFFSET);
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case 0x1f2: return (void *)(0x0c012002 | NONCACHE_OFFSET);
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case 0x1f3: return (void *)(0x0c012802 | NONCACHE_OFFSET);
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case 0x1f4: return (void *)(0x0c012004 | NONCACHE_OFFSET);
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case 0x1f5: return (void *)(0x0c012804 | NONCACHE_OFFSET);
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case 0x1f6: return (void *)(0x0c012006 | NONCACHE_OFFSET);
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case 0x1f7: return (void *)(0x0c012806 | NONCACHE_OFFSET);
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case 0x3f6: return (void *)(0x0c01200e | NONCACHE_OFFSET);
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default: return (void *)&dummy_reg;
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}
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}
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@ -64,8 +64,8 @@ static inline void *__port2addr_ata(unsigned long port)
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* from 0x10000000 to 0x13ffffff on physical address.
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* The base address of LAN controller(LAN91C111) is 0x300.
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*/
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#define LAN_IOSTART 0xa0000300
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#define LAN_IOEND 0xa0000320
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#define LAN_IOSTART (0x300 | NONCACHE_OFFSET)
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#define LAN_IOEND (0x320 | NONCACHE_OFFSET)
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static inline void *_port2addr_ne(unsigned long port)
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{
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return (void *)(port + 0x10000000);
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@ -31,7 +31,7 @@ extern void pcc_iowrite(int, unsigned long, void *, size_t, size_t, int);
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static inline void *_port2addr(unsigned long port)
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{
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return (void *)(port | (NONCACHE_OFFSET));
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return (void *)(port | NONCACHE_OFFSET);
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}
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static inline void *_port2addr_ne(unsigned long port)
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@ -33,7 +33,7 @@ extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
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static inline void *_port2addr(unsigned long port)
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{
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return (void *)(port | (NONCACHE_OFFSET));
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return (void *)(port | NONCACHE_OFFSET);
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}
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#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
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@ -42,22 +42,22 @@ static inline void *__port2addr_ata(unsigned long port)
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static int dummy_reg;
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switch (port) {
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case 0x1f0: return (void *)0xac002000;
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case 0x1f1: return (void *)0xac012800;
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case 0x1f2: return (void *)0xac012002;
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case 0x1f3: return (void *)0xac012802;
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case 0x1f4: return (void *)0xac012004;
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case 0x1f5: return (void *)0xac012804;
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case 0x1f6: return (void *)0xac012006;
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case 0x1f7: return (void *)0xac012806;
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case 0x3f6: return (void *)0xac01200e;
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case 0x1f0: return (void *)(0x0c002000 | NONCACHE_OFFSET);
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case 0x1f1: return (void *)(0x0c012800 | NONCACHE_OFFSET);
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case 0x1f2: return (void *)(0x0c012002 | NONCACHE_OFFSET);
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case 0x1f3: return (void *)(0x0c012802 | NONCACHE_OFFSET);
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case 0x1f4: return (void *)(0x0c012004 | NONCACHE_OFFSET);
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case 0x1f5: return (void *)(0x0c012804 | NONCACHE_OFFSET);
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case 0x1f6: return (void *)(0x0c012006 | NONCACHE_OFFSET);
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case 0x1f7: return (void *)(0x0c012806 | NONCACHE_OFFSET);
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case 0x3f6: return (void *)(0x0c01200e | NONCACHE_OFFSET);
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default: return (void *)&dummy_reg;
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}
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}
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#endif
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#define LAN_IOSTART 0xa0000300
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#define LAN_IOEND 0xa0000320
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#define LAN_IOSTART (0x300 | NONCACHE_OFFSET)
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#define LAN_IOEND (0x320 | NONCACHE_OFFSET)
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#ifdef CONFIG_CHIP_OPSP
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static inline void *_port2addr_ne(unsigned long port)
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{
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@ -33,7 +33,7 @@ extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
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static inline void *_port2addr(unsigned long port)
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{
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return (void *)(port + NONCACHE_OFFSET);
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return (void *)(port | NONCACHE_OFFSET);
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}
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#if defined(CONFIG_IDE)
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@ -43,33 +43,42 @@ static inline void *__port2addr_ata(unsigned long port)
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switch (port) {
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/* IDE0 CF */
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case 0x1f0: return (void *)0xb4002000;
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case 0x1f1: return (void *)0xb4012800;
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case 0x1f2: return (void *)0xb4012002;
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case 0x1f3: return (void *)0xb4012802;
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case 0x1f4: return (void *)0xb4012004;
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case 0x1f5: return (void *)0xb4012804;
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case 0x1f6: return (void *)0xb4012006;
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case 0x1f7: return (void *)0xb4012806;
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case 0x3f6: return (void *)0xb401200e;
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case 0x1f0: return (void *)(0x14002000 | NONCACHE_OFFSET);
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case 0x1f1: return (void *)(0x14012800 | NONCACHE_OFFSET);
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case 0x1f2: return (void *)(0x14012002 | NONCACHE_OFFSET);
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case 0x1f3: return (void *)(0x14012802 | NONCACHE_OFFSET);
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case 0x1f4: return (void *)(0x14012004 | NONCACHE_OFFSET);
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case 0x1f5: return (void *)(0x14012804 | NONCACHE_OFFSET);
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case 0x1f6: return (void *)(0x14012006 | NONCACHE_OFFSET);
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case 0x1f7: return (void *)(0x14012806 | NONCACHE_OFFSET);
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case 0x3f6: return (void *)(0x1401200e | NONCACHE_OFFSET);
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/* IDE1 IDE */
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case 0x170: return (void *)0xb4810000; /* Data 16bit */
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case 0x171: return (void *)0xb4810002; /* Features / Error */
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case 0x172: return (void *)0xb4810004; /* Sector count */
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case 0x173: return (void *)0xb4810006; /* Sector number */
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case 0x174: return (void *)0xb4810008; /* Cylinder low */
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case 0x175: return (void *)0xb481000a; /* Cylinder high */
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case 0x176: return (void *)0xb481000c; /* Device head */
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case 0x177: return (void *)0xb481000e; /* Command */
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case 0x376: return (void *)0xb480800c; /* Device control / Alt status */
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case 0x170: /* Data 16bit */
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return (void *)(0x14810000 | NONCACHE_OFFSET);
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case 0x171: /* Features / Error */
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return (void *)(0x14810002 | NONCACHE_OFFSET);
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case 0x172: /* Sector count */
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return (void *)(0x14810004 | NONCACHE_OFFSET);
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case 0x173: /* Sector number */
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return (void *)(0x14810006 | NONCACHE_OFFSET);
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case 0x174: /* Cylinder low */
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return (void *)(0x14810008 | NONCACHE_OFFSET);
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case 0x175: /* Cylinder high */
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return (void *)(0x1481000a | NONCACHE_OFFSET);
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case 0x176: /* Device head */
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return (void *)(0x1481000c | NONCACHE_OFFSET);
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case 0x177: /* Command */
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return (void *)(0x1481000e | NONCACHE_OFFSET);
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case 0x376: /* Device control / Alt status */
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return (void *)(0x1480800c | NONCACHE_OFFSET);
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default: return (void *)&dummy_reg;
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}
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}
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#endif
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#define LAN_IOSTART 0xa0000300
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#define LAN_IOEND 0xa0000320
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#define LAN_IOSTART (0x300 | NONCACHE_OFFSET)
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#define LAN_IOEND (0x320 | NONCACHE_OFFSET)
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static inline void *_port2addr_ne(unsigned long port)
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{
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return (void *)(port + 0x10000000);
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@ -16,7 +16,7 @@
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static inline void *_port2addr(unsigned long port)
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{
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return (void *)(port | (NONCACHE_OFFSET));
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return (void *)(port | NONCACHE_OFFSET);
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}
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static inline void *_port2addr_ne(unsigned long port)
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@ -36,7 +36,7 @@ extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
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static inline void *_port2addr(unsigned long port)
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{
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return (void *)(port | (NONCACHE_OFFSET));
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return (void *)(port | NONCACHE_OFFSET);
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}
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/*
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@ -44,8 +44,8 @@ static inline void *_port2addr(unsigned long port)
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* from 0x10000000 to 0x13ffffff on physical address.
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* The base address of LAN controller(LAN91C111) is 0x300.
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*/
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#define LAN_IOSTART 0xa0000300
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#define LAN_IOEND 0xa0000320
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#define LAN_IOSTART (0x300 | NONCACHE_OFFSET)
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#define LAN_IOEND (0x320 | NONCACHE_OFFSET)
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static inline void *_port2addr_ne(unsigned long port)
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{
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return (void *)(port + 0x10000000);
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@ -126,7 +126,7 @@
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#include <asm/page.h>
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#ifdef CONFIG_MMU
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#define NONCACHE_OFFSET __PAGE_OFFSET+0x20000000
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#define NONCACHE_OFFSET (__PAGE_OFFSET + 0x20000000)
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#else
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#define NONCACHE_OFFSET __PAGE_OFFSET
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#endif /* CONFIG_MMU */
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