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media: hantro: add support for STM32MP25 VDEC

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Add support for STM32MP25 VDEC video hardware decoder.
Support of H264/VP8 decoding.
No post-processor support.
VDEC has its own reset/clock/irq.

Successfully tested up to full HD.

Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Hugues Fruchet <hugues.fruchet@foss.st.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
This commit is contained in:
Hugues Fruchet 2024-01-10 11:46:39 +01:00 committed by Mauro Carvalho Chehab
parent 60314831d2
commit 46c4dffb74
5 changed files with 114 additions and 3 deletions
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14
drivers/media/platform/verisilicon/Kconfig
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@ -4,7 +4,7 @@ comment "Verisilicon media platform drivers"
config VIDEO_HANTRO
tristate "Hantro VPU driver"
depends on ARCH_MXC || ARCH_ROCKCHIP || ARCH_AT91 || ARCH_SUNXI || COMPILE_TEST
depends on ARCH_MXC || ARCH_ROCKCHIP || ARCH_AT91 || ARCH_SUNXI || ARCH_STM32 || COMPILE_TEST
depends on V4L_MEM2MEM_DRIVERS
depends on VIDEO_DEV
select MEDIA_CONTROLLER
@ -15,8 +15,8 @@ config VIDEO_HANTRO
select V4L2_VP9
help
Support for the Hantro IP based Video Processing Units present on
Rockchip and NXP i.MX8M SoCs, which accelerate video and image
encoding and decoding.
Rockchip, NXP i.MX8M and STM32MP25 SoCs, which accelerate video
and image encoding and decoding.
To compile this driver as a module, choose M here: the module
will be called hantro-vpu.
@ -51,3 +51,11 @@ config VIDEO_HANTRO_SUNXI
default y
help
Enable support for H6 SoC.
config VIDEO_HANTRO_STM32MP25
bool "Hantro STM32MP25 support"
depends on VIDEO_HANTRO
depends on ARCH_STM32 || COMPILE_TEST
default y
help
Enable support for STM32MP25 SoCs.

3
drivers/media/platform/verisilicon/Makefile
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@ -39,3 +39,6 @@ hantro-vpu-$(CONFIG_VIDEO_HANTRO_ROCKCHIP) += \
hantro-vpu-$(CONFIG_VIDEO_HANTRO_SUNXI) += \
sunxi_vpu_hw.o
hantro-vpu-$(CONFIG_VIDEO_HANTRO_STM32MP25) += \
stm32mp25_vpu_hw.o

3
drivers/media/platform/verisilicon/hantro_drv.c
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@ -735,6 +735,9 @@ static const struct of_device_id of_hantro_match[] = {
#endif
#ifdef CONFIG_VIDEO_HANTRO_SUNXI
{ .compatible = "allwinner,sun50i-h6-vpu-g2", .data = &sunxi_vpu_variant, },
#endif
#ifdef CONFIG_VIDEO_HANTRO_STM32MP25
{ .compatible = "st,stm32mp25-vdec", .data = &stm32mp25_vdec_variant, },
#endif
{ /* sentinel */ }
};

1
drivers/media/platform/verisilicon/hantro_hw.h
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@ -408,6 +408,7 @@ extern const struct hantro_variant rk3568_vpu_variant;
extern const struct hantro_variant rk3588_vpu981_variant;
extern const struct hantro_variant sama5d4_vdec_variant;
extern const struct hantro_variant sunxi_vpu_variant;
extern const struct hantro_variant stm32mp25_vdec_variant;
extern const struct hantro_postproc_ops hantro_g1_postproc_ops;
extern const struct hantro_postproc_ops hantro_g2_postproc_ops;

96
drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c Normal file
View File

@ -0,0 +1,96 @@
// SPDX-License-Identifier: GPL-2.0
/*
* STM32MP25 video codec driver
*
* Copyright (C) STMicroelectronics SA 2024
* Authors: Hugues Fruchet <hugues.fruchet@foss.st.com>
* for STMicroelectronics.
*
*/
#include "hantro.h"
/*
* Supported formats.
*/
static const struct hantro_fmt stm32mp25_vdec_fmts[] = {
{
.fourcc = V4L2_PIX_FMT_NV12,
.codec_mode = HANTRO_MODE_NONE,
.frmsize = {
.min_width = FMT_MIN_WIDTH,
.max_width = FMT_FHD_WIDTH,
.step_width = MB_DIM,
.min_height = FMT_MIN_HEIGHT,
.max_height = FMT_FHD_HEIGHT,
.step_height = MB_DIM,
},
},
{
.fourcc = V4L2_PIX_FMT_VP8_FRAME,
.codec_mode = HANTRO_MODE_VP8_DEC,
.max_depth = 2,
.frmsize = {
.min_width = FMT_MIN_WIDTH,
.max_width = FMT_FHD_WIDTH,
.step_width = MB_DIM,
.min_height = FMT_MIN_HEIGHT,
.max_height = FMT_FHD_HEIGHT,
.step_height = MB_DIM,
},
},
{
.fourcc = V4L2_PIX_FMT_H264_SLICE,
.codec_mode = HANTRO_MODE_H264_DEC,
.max_depth = 2,
.frmsize = {
.min_width = FMT_MIN_WIDTH,
.max_width = FMT_FHD_WIDTH,
.step_width = MB_DIM,
.min_height = FMT_MIN_HEIGHT,
.max_height = FMT_FHD_HEIGHT,
.step_height = MB_DIM,
},
},
};
/*
* Supported codec ops.
*/
static const struct hantro_codec_ops stm32mp25_vdec_codec_ops[] = {
[HANTRO_MODE_VP8_DEC] = {
.run = hantro_g1_vp8_dec_run,
.reset = hantro_g1_reset,
.init = hantro_vp8_dec_init,
.exit = hantro_vp8_dec_exit,
},
[HANTRO_MODE_H264_DEC] = {
.run = hantro_g1_h264_dec_run,
.reset = hantro_g1_reset,
.init = hantro_h264_dec_init,
.exit = hantro_h264_dec_exit,
},
};
/*
* Variants.
*/
static const struct hantro_irq stm32mp25_vdec_irqs[] = {
{ "vdec", hantro_g1_irq },
};
static const char * const stm32mp25_vdec_clk_names[] = { "vdec-clk" };
const struct hantro_variant stm32mp25_vdec_variant = {
.dec_fmts = stm32mp25_vdec_fmts,
.num_dec_fmts = ARRAY_SIZE(stm32mp25_vdec_fmts),
.codec = HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
.codec_ops = stm32mp25_vdec_codec_ops,
.irqs = stm32mp25_vdec_irqs,
.num_irqs = ARRAY_SIZE(stm32mp25_vdec_irqs),
.clk_names = stm32mp25_vdec_clk_names,
.num_clocks = ARRAY_SIZE(stm32mp25_vdec_clk_names),
};