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ARM: dts: r8a73a4: Correct mask for GIC PPI interrupts

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R-Mobile APE6 (r8a73a4) contains four Cortex-A15 and four Cortex-A7
cores, hence the second interrupt specifier cell for Private Peripheral
Interrupts should use "GIC_CPU_MASK_SIMPLE(8)", so GIC interrupts are
delivered to all 8 processor cores.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven 2018-05-07 15:19:53 +02:00 committed by Simon Horman
parent 2acb79e151
commit 45e75c425b
1 changed files with 5 additions and 5 deletions
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10
arch/arm/boot/dts/r8a73a4.dtsi
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@ -57,10 +57,10 @@
timer { timer {
compatible = "arm,armv7-timer"; compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
}; };
dbsc1: memory-controller@e6790000 { dbsc1: memory-controller@e6790000 {
@ -464,7 +464,7 @@
<0 0xf1002000 0 0x2000>, <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>, <0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>; <0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>; clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
clock-names = "clk"; clock-names = "clk";
power-domains = <&pd_c4>; power-domains = <&pd_c4>;