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ARM: OMAP3+: DPLL: drop !CONFIG_COMMON_CLK sections
Remove all of the code that is compiled when CONFIG_COMMON_CLK=n in the OMAP3+ DPLL handling code. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Mike Turquette <mturquette@ti.com> Cc: Rajendra Nayak <rnayak@ti.com>
This commit is contained in:
Paul Walmsley
parent
e127539fb3
commit
455db9c9b2
@ -43,11 +43,7 @@
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/* Private functions */
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/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
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#ifdef CONFIG_COMMON_CLK
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static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
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#else
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static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
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#endif
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{
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const struct dpll_data *dd;
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u32 v;
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@ -61,11 +57,7 @@ static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
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}
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/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
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#ifdef CONFIG_COMMON_CLK
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static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
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#else
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static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
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#endif
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{
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const struct dpll_data *dd;
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int i = 0;
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@ -73,11 +65,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
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const char *clk_name;
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dd = clk->dpll_data;
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#ifdef CONFIG_COMMON_CLK
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clk_name = __clk_get_name(clk->hw.clk);
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#else
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clk_name = __clk_get_name(clk);
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#endif
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state <<= __ffs(dd->idlest_mask);
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@ -101,11 +89,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
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}
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/* From 3430 TRM ES2 4.7.6.2 */
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#ifdef CONFIG_COMMON_CLK
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static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)
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#else
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static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
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#endif
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{
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unsigned long fint;
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u16 f = 0;
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@ -150,22 +134,14 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
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* locked successfully, return 0; if the DPLL did not lock in the time
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* allotted, or DPLL3 was passed in, return -EINVAL.
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*/
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#ifdef CONFIG_COMMON_CLK
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static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
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#else
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static int _omap3_noncore_dpll_lock(struct clk *clk)
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#endif
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{
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const struct dpll_data *dd;
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u8 ai;
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u8 state = 1;
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int r = 0;
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#ifdef CONFIG_COMMON_CLK
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pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk));
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#else
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pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk));
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#endif
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dd = clk->dpll_data;
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state <<= __ffs(dd->idlest_mask);
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@ -203,11 +179,7 @@ done:
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* DPLL3 was passed in, or the DPLL does not support low-power bypass,
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* return -EINVAL.
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*/
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#ifdef CONFIG_COMMON_CLK
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static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)
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#else
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static int _omap3_noncore_dpll_bypass(struct clk *clk)
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#endif
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{
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int r;
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u8 ai;
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@ -216,11 +188,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
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return -EINVAL;
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pr_debug("clock: configuring DPLL %s for low-power bypass\n",
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#ifdef CONFIG_COMMON_CLK
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__clk_get_name(clk->hw.clk));
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#else
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__clk_get_name(clk));
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#endif
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ai = omap3_dpll_autoidle_read(clk);
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@ -243,22 +211,14 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
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* code. If DPLL3 was passed in, or the DPLL does not support
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* low-power stop, return -EINVAL; otherwise, return 0.
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*/
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#ifdef CONFIG_COMMON_CLK
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static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk)
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#else
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static int _omap3_noncore_dpll_stop(struct clk *clk)
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#endif
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{
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u8 ai;
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if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
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return -EINVAL;
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#ifdef CONFIG_COMMON_CLK
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pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk));
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#else
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pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk));
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#endif
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ai = omap3_dpll_autoidle_read(clk);
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@ -282,19 +242,11 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
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* XXX This code is not needed for 3430/AM35xx; can it be optimized
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* out in non-multi-OMAP builds for those chips?
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*/
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#ifdef CONFIG_COMMON_CLK
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static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n)
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#else
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static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
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#endif
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{
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unsigned long fint, clkinp; /* watch out for overflow */
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#ifdef CONFIG_COMMON_CLK
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clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));
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#else
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clkinp = __clk_get_rate(__clk_get_parent(clk));
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#endif
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fint = (clkinp / n) * m;
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if (fint < 1000000000)
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@ -315,20 +267,12 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
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* XXX This code is not needed for 3430/AM35xx; can it be optimized
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* out in non-multi-OMAP builds for those chips?
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*/
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#ifdef CONFIG_COMMON_CLK
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static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
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#else
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static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
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#endif
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{
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unsigned long clkinp, sd; /* watch out for overflow */
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int mod1, mod2;
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#ifdef CONFIG_COMMON_CLK
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clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));
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#else
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clkinp = __clk_get_rate(__clk_get_parent(clk));
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#endif
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/*
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* target sigma-delta to near 250MHz
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@ -355,12 +299,8 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
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* Program the DPLL with the supplied M, N values, and wait for the DPLL to
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* lock.. Returns -EINVAL upon error, or 0 upon success.
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*/
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#ifdef CONFIG_COMMON_CLK
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static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 m, u8 n,
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u16 freqsel)
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#else
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static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
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#endif
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{
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struct dpll_data *dd = clk->dpll_data;
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u8 dco, sd_div;
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@ -417,14 +357,10 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
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*
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* Recalculate and propagate the DPLL rate.
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*/
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#ifdef CONFIG_COMMON_CLK
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unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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#else
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unsigned long omap3_dpll_recalc(struct clk *clk)
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{
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#endif
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return omap2_get_dpll_rate(clk);
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}
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@ -444,14 +380,9 @@ unsigned long omap3_dpll_recalc(struct clk *clk)
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* support low-power stop, or if the DPLL took too long to enter
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* bypass or lock, return -EINVAL; otherwise, return 0.
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*/
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#ifdef CONFIG_COMMON_CLK
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int omap3_noncore_dpll_enable(struct clk_hw *hw)
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{
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struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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#else
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int omap3_noncore_dpll_enable(struct clk *clk)
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{
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#endif
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int r;
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struct dpll_data *dd;
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struct clk *parent;
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@ -460,7 +391,6 @@ int omap3_noncore_dpll_enable(struct clk *clk)
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if (!dd)
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return -EINVAL;
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#ifdef CONFIG_COMMON_CLK
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if (clk->clkdm) {
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r = clkdm_clk_enable(clk->clkdm, hw->clk);
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if (r) {
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@ -475,11 +405,6 @@ int omap3_noncore_dpll_enable(struct clk *clk)
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parent = __clk_get_parent(hw->clk);
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if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) {
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#else
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parent = __clk_get_parent(clk);
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if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) {
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#endif
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WARN_ON(parent != dd->clk_bypass);
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r = _omap3_noncore_dpll_bypass(clk);
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} else {
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@ -487,16 +412,6 @@ int omap3_noncore_dpll_enable(struct clk *clk)
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r = _omap3_noncore_dpll_lock(clk);
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}
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#ifndef CONFIG_COMMON_CLK
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/*
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*FIXME: this is dubious - if clk->rate has changed, what about
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* propagating?
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*/
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if (!r)
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clk->rate = (clk->recalc) ? clk->recalc(clk) :
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omap2_get_dpll_rate(clk);
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#endif
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return r;
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}
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@ -507,7 +422,6 @@ int omap3_noncore_dpll_enable(struct clk *clk)
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* Instructs a non-CORE DPLL to enter low-power stop. This function is
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* intended for use in struct clkops. No return value.
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*/
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#ifdef CONFIG_COMMON_CLK
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void omap3_noncore_dpll_disable(struct clk_hw *hw)
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{
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struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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@ -515,13 +429,6 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw)
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_omap3_noncore_dpll_stop(clk);
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if (clk->clkdm)
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clkdm_clk_disable(clk->clkdm, hw->clk);
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#else
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void omap3_noncore_dpll_disable(struct clk *clk)
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{
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_omap3_noncore_dpll_stop(clk);
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if (clk->clkdm)
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clkdm_clk_disable(clk->clkdm, clk);
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#endif
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}
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@ -538,7 +445,6 @@ void omap3_noncore_dpll_disable(struct clk *clk)
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* target rate if it hasn't been done already, then program and lock
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* the DPLL. Returns -EINVAL upon error, or 0 upon success.
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*/
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#ifdef CONFIG_COMMON_CLK
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int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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@ -608,85 +514,6 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
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return 0;
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}
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#else
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int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
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{
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struct clk *new_parent = NULL;
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unsigned long hw_rate, bypass_rate;
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u16 freqsel = 0;
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struct dpll_data *dd;
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int ret;
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if (!clk || !rate)
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return -EINVAL;
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dd = clk->dpll_data;
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if (!dd)
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return -EINVAL;
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hw_rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk);
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if (rate == hw_rate)
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return 0;
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/*
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* Ensure both the bypass and ref clocks are enabled prior to
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* doing anything; we need the bypass clock running to reprogram
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* the DPLL.
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*/
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omap2_clk_enable(dd->clk_bypass);
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omap2_clk_enable(dd->clk_ref);
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bypass_rate = __clk_get_rate(dd->clk_bypass);
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if (bypass_rate == rate &&
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(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
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pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
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ret = _omap3_noncore_dpll_bypass(clk);
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if (!ret)
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new_parent = dd->clk_bypass;
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} else {
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if (dd->last_rounded_rate != rate)
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rate = clk->round_rate(clk, rate);
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if (dd->last_rounded_rate == 0)
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return -EINVAL;
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/* No freqsel on OMAP4 and OMAP3630 */
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if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
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freqsel = _omap3_dpll_compute_freqsel(clk,
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dd->last_rounded_n);
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if (!freqsel)
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WARN_ON(1);
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}
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pr_debug("clock: %s: set rate: locking rate to %lu.\n",
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__clk_get_name(clk), rate);
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ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
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dd->last_rounded_n, freqsel);
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if (!ret)
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new_parent = dd->clk_ref;
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}
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if (!ret) {
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/*
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* Switch the parent clock in the hierarchy, and make sure
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* that the new parent's usecount is correct. Note: we
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* enable the new parent before disabling the old to avoid
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* any unnecessary hardware disable->enable transitions.
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*/
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if (clk->usecount) {
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omap2_clk_enable(new_parent);
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omap2_clk_disable(clk->parent);
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}
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clk_reparent(clk, new_parent);
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clk->rate = rate;
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}
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omap2_clk_disable(dd->clk_ref);
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omap2_clk_disable(dd->clk_bypass);
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return 0;
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}
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#endif
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/* DPLL autoidle read/set code */
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@ -698,11 +525,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
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* -EINVAL if passed a null pointer or if the struct clk does not
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* appear to refer to a DPLL.
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*/
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#ifdef CONFIG_COMMON_CLK
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u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
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#else
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u32 omap3_dpll_autoidle_read(struct clk *clk)
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#endif
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{
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const struct dpll_data *dd;
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u32 v;
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@ -731,11 +554,7 @@ u32 omap3_dpll_autoidle_read(struct clk *clk)
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* OMAP3430. The DPLL will enter low-power stop when its downstream
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* clocks are gated. No return value.
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*/
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#ifdef CONFIG_COMMON_CLK
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void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
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#else
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void omap3_dpll_allow_idle(struct clk *clk)
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#endif
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{
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const struct dpll_data *dd;
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u32 v;
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@ -745,13 +564,8 @@ void omap3_dpll_allow_idle(struct clk *clk)
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dd = clk->dpll_data;
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if (!dd->autoidle_reg) {
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#ifndef CONFIG_COMMON_CLK
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pr_debug("clock: DPLL %s: autoidle not supported\n",
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__clk_get_name(clk));
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#endif
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if (!dd->autoidle_reg)
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return;
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}
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/*
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* REVISIT: CORE DPLL can optionally enter low-power bypass
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@ -771,11 +585,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
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*
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* Disable DPLL automatic idle control. No return value.
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*/
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#ifdef CONFIG_COMMON_CLK
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void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
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#else
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void omap3_dpll_deny_idle(struct clk *clk)
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#endif
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{
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const struct dpll_data *dd;
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u32 v;
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@ -785,13 +595,8 @@ void omap3_dpll_deny_idle(struct clk *clk)
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dd = clk->dpll_data;
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if (!dd->autoidle_reg) {
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#ifndef CONFIG_COMMON_CLK
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pr_debug("clock: DPLL %s: autoidle not supported\n",
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__clk_get_name(clk));
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#endif
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if (!dd->autoidle_reg)
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return;
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}
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v = __raw_readl(dd->autoidle_reg);
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v &= ~dd->autoidle_mask;
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@ -809,7 +614,6 @@ void omap3_dpll_deny_idle(struct clk *clk)
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* Using parent clock DPLL data, look up DPLL state. If locked, set our
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* rate to the dpll_clk * 2; otherwise, just use dpll_clk.
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*/
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#ifdef CONFIG_COMMON_CLK
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unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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@ -829,22 +633,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
|
||||
break;
|
||||
pclk = to_clk_hw_omap(hw);
|
||||
} while (pclk && !pclk->dpll_data);
|
||||
#else
|
||||
unsigned long omap3_clkoutx2_recalc(struct clk *clk)
|
||||
{
|
||||
const struct dpll_data *dd;
|
||||
unsigned long rate;
|
||||
u32 v;
|
||||
struct clk *pclk;
|
||||
unsigned long parent_rate;
|
||||
|
||||
/* Walk up the parents of clk, looking for a DPLL */
|
||||
pclk = __clk_get_parent(clk);
|
||||
while (pclk && !pclk->dpll_data)
|
||||
pclk = __clk_get_parent(pclk);
|
||||
|
||||
parent_rate = __clk_get_rate(__clk_get_parent(clk));
|
||||
#endif
|
||||
/* clk does not have a DPLL as a parent? error in the clock data */
|
||||
if (!pclk) {
|
||||
WARN_ON(1);
|
||||
@ -865,21 +654,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
|
||||
}
|
||||
|
||||
/* OMAP3/4 non-CORE DPLL clkops */
|
||||
#ifdef CONFIG_COMMON_CLK
|
||||
const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
|
||||
.allow_idle = omap3_dpll_allow_idle,
|
||||
.deny_idle = omap3_dpll_deny_idle,
|
||||
};
|
||||
#else
|
||||
const struct clkops clkops_omap3_noncore_dpll_ops = {
|
||||
.enable = omap3_noncore_dpll_enable,
|
||||
.disable = omap3_noncore_dpll_disable,
|
||||
.allow_idle = omap3_dpll_allow_idle,
|
||||
.deny_idle = omap3_dpll_deny_idle,
|
||||
};
|
||||
|
||||
const struct clkops clkops_omap3_core_dpll_ops = {
|
||||
.allow_idle = omap3_dpll_allow_idle,
|
||||
.deny_idle = omap3_dpll_deny_idle,
|
||||
};
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user