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MIPS: MIPS16e: Add unaligned access support.
Add logic needed to handle unaligned accesses in MIPS16e mode. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
This commit is contained in:
Steven J. Hill
Ralf Baechle
parent
8508488fe7
commit
451b001b05
@ -1304,6 +1304,250 @@ sigill:
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force_sig(SIGILL, current);
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}
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static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr)
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{
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unsigned long value;
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unsigned int res;
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int reg;
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unsigned long orig31;
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u16 __user *pc16;
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unsigned long origpc;
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union mips16e_instruction mips16inst, oldinst;
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origpc = regs->cp0_epc;
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orig31 = regs->regs[31];
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pc16 = (unsigned short __user *)msk_isa16_mode(origpc);
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/*
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* This load never faults.
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*/
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__get_user(mips16inst.full, pc16);
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oldinst = mips16inst;
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/* skip EXTEND instruction */
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if (mips16inst.ri.opcode == MIPS16e_extend_op) {
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pc16++;
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__get_user(mips16inst.full, pc16);
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} else if (delay_slot(regs)) {
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/* skip jump instructions */
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/* JAL/JALX are 32 bits but have OPCODE in first short int */
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if (mips16inst.ri.opcode == MIPS16e_jal_op)
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pc16++;
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pc16++;
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if (get_user(mips16inst.full, pc16))
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goto sigbus;
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}
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switch (mips16inst.ri.opcode) {
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case MIPS16e_i64_op: /* I64 or RI64 instruction */
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switch (mips16inst.i64.func) { /* I64/RI64 func field check */
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case MIPS16e_ldpc_func:
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case MIPS16e_ldsp_func:
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reg = reg16to32[mips16inst.ri64.ry];
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goto loadDW;
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case MIPS16e_sdsp_func:
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reg = reg16to32[mips16inst.ri64.ry];
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goto writeDW;
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case MIPS16e_sdrasp_func:
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reg = 29; /* GPRSP */
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goto writeDW;
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}
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goto sigbus;
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case MIPS16e_swsp_op:
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case MIPS16e_lwpc_op:
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case MIPS16e_lwsp_op:
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reg = reg16to32[mips16inst.ri.rx];
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break;
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case MIPS16e_i8_op:
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if (mips16inst.i8.func != MIPS16e_swrasp_func)
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goto sigbus;
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reg = 29; /* GPRSP */
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break;
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default:
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reg = reg16to32[mips16inst.rri.ry];
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break;
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}
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switch (mips16inst.ri.opcode) {
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case MIPS16e_lb_op:
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case MIPS16e_lbu_op:
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case MIPS16e_sb_op:
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goto sigbus;
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case MIPS16e_lh_op:
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if (!access_ok(VERIFY_READ, addr, 2))
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goto sigbus;
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LoadHW(addr, value, res);
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if (res)
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goto fault;
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MIPS16e_compute_return_epc(regs, &oldinst);
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regs->regs[reg] = value;
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break;
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case MIPS16e_lhu_op:
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if (!access_ok(VERIFY_READ, addr, 2))
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goto sigbus;
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LoadHWU(addr, value, res);
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if (res)
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goto fault;
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MIPS16e_compute_return_epc(regs, &oldinst);
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regs->regs[reg] = value;
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break;
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case MIPS16e_lw_op:
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case MIPS16e_lwpc_op:
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case MIPS16e_lwsp_op:
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if (!access_ok(VERIFY_READ, addr, 4))
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goto sigbus;
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LoadW(addr, value, res);
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if (res)
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goto fault;
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MIPS16e_compute_return_epc(regs, &oldinst);
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regs->regs[reg] = value;
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break;
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case MIPS16e_lwu_op:
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#ifdef CONFIG_64BIT
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/*
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* A 32-bit kernel might be running on a 64-bit processor. But
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* if we're on a 32-bit processor and an i-cache incoherency
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* or race makes us see a 64-bit instruction here the sdl/sdr
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* would blow up, so for now we don't handle unaligned 64-bit
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* instructions on 32-bit kernels.
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*/
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if (!access_ok(VERIFY_READ, addr, 4))
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goto sigbus;
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LoadWU(addr, value, res);
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if (res)
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goto fault;
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MIPS16e_compute_return_epc(regs, &oldinst);
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regs->regs[reg] = value;
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break;
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#endif /* CONFIG_64BIT */
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/* Cannot handle 64-bit instructions in 32-bit kernel */
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goto sigill;
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case MIPS16e_ld_op:
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loadDW:
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#ifdef CONFIG_64BIT
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/*
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* A 32-bit kernel might be running on a 64-bit processor. But
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* if we're on a 32-bit processor and an i-cache incoherency
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* or race makes us see a 64-bit instruction here the sdl/sdr
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* would blow up, so for now we don't handle unaligned 64-bit
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* instructions on 32-bit kernels.
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*/
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if (!access_ok(VERIFY_READ, addr, 8))
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goto sigbus;
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LoadDW(addr, value, res);
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if (res)
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goto fault;
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MIPS16e_compute_return_epc(regs, &oldinst);
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regs->regs[reg] = value;
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break;
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#endif /* CONFIG_64BIT */
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/* Cannot handle 64-bit instructions in 32-bit kernel */
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goto sigill;
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case MIPS16e_sh_op:
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if (!access_ok(VERIFY_WRITE, addr, 2))
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goto sigbus;
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MIPS16e_compute_return_epc(regs, &oldinst);
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value = regs->regs[reg];
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StoreHW(addr, value, res);
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if (res)
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goto fault;
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break;
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case MIPS16e_sw_op:
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case MIPS16e_swsp_op:
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case MIPS16e_i8_op: /* actually - MIPS16e_swrasp_func */
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if (!access_ok(VERIFY_WRITE, addr, 4))
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goto sigbus;
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MIPS16e_compute_return_epc(regs, &oldinst);
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value = regs->regs[reg];
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StoreW(addr, value, res);
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if (res)
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goto fault;
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break;
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case MIPS16e_sd_op:
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writeDW:
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#ifdef CONFIG_64BIT
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/*
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* A 32-bit kernel might be running on a 64-bit processor. But
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* if we're on a 32-bit processor and an i-cache incoherency
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* or race makes us see a 64-bit instruction here the sdl/sdr
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* would blow up, so for now we don't handle unaligned 64-bit
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* instructions on 32-bit kernels.
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*/
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if (!access_ok(VERIFY_WRITE, addr, 8))
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goto sigbus;
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MIPS16e_compute_return_epc(regs, &oldinst);
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value = regs->regs[reg];
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StoreDW(addr, value, res);
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if (res)
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goto fault;
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break;
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#endif /* CONFIG_64BIT */
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/* Cannot handle 64-bit instructions in 32-bit kernel */
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goto sigill;
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default:
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/*
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* Pheeee... We encountered an yet unknown instruction or
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* cache coherence problem. Die sucker, die ...
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*/
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goto sigill;
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}
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#ifdef CONFIG_DEBUG_FS
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unaligned_instructions++;
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#endif
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return;
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fault:
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/* roll back jump/branch */
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regs->cp0_epc = origpc;
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regs->regs[31] = orig31;
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/* Did we have an exception handler installed? */
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if (fixup_exception(regs))
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return;
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die_if_kernel("Unhandled kernel unaligned access", regs);
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force_sig(SIGSEGV, current);
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return;
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sigbus:
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die_if_kernel("Unhandled kernel unaligned access", regs);
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force_sig(SIGBUS, current);
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return;
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sigill:
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die_if_kernel
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("Unhandled kernel unaligned access or invalid instruction", regs);
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force_sig(SIGILL, current);
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}
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asmlinkage void do_ade(struct pt_regs *regs)
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{
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unsigned int __user *pc;
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@ -1351,6 +1595,17 @@ asmlinkage void do_ade(struct pt_regs *regs)
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return;
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}
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if (cpu_has_mips16) {
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seg = get_fs();
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if (!user_mode(regs))
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set_fs(KERNEL_DS);
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emulate_load_store_MIPS16e(regs,
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(void __user *)regs->cp0_badvaddr);
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set_fs(seg);
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return;
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}
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goto sigbus;
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}
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