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Renesas ARM Based SoC Fixes for v5.1
R-Car Gen3 E3 (r8a77990) and RZ/G2E (r8a774c0) SoCs: * Correct SCIF5 DMA channels -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAlyLegEACgkQ189kaWo3 T76QFBAAlYeKbR0QsA92hciDmlWMMvp26LPXDlI8Ue+vcxi9Weps1t2H2ZcCl0Hc vt5EVp5fnM15gpMwDNMVKZan7NKuxPrIqXYO23oR/YW4GUV/H9gwKteAwHEcXVp3 7kp9OvYkPYAXNoFxK8kh26qVoeBZxckdRchHdNq/A+3dXjuamA+s04OK62S5N+4r eEWPZ446IOJZEswN6DCC3uF+92JLW3TrjMoRkqWm+LrKbvFFFgokx8DD+kf3+pES ZZzS9yuY+U/BK0mvRs7GbLNoC83b1TMp2AJDZjf0eA6gs+Nxi+2/AwtNgU7kMRlZ ucBc9qhg3K8r9UZQw83sWs6wcAsBLsgv9KJjY34KFJdXxHWXNIB2hvAUV1uA++hq Vz+wYa+zs7xW2BlSbaw8awa+o1BP01+hjLdsEJg3WJsMM+ayBOB5J3mZ28YHktlE Y6YLD+zxp2GsIA6FaMoJfiocZfm0AutRWyF59OHqhwKHenq+LFL3/J0lNsTEeDTm pU1tlNoxglxMEHIatV8YQtSngrPDeTjny0MIb2k94XXbB3ljL+bXph8JlG3hb8od X5ekBoLWQY+VrB/6Hy2cHQdJSWaZTf/KYF3QyFO8790MJU8rjQ208oYRiTax5U1i K2KIquikCDOiFbRgZy3bR1J9wJUdnrx/EI9qzMyjv+hrcWpxJTM= =6Y1e -----END PGP SIGNATURE----- Merge tag 'renesas-fixes-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into arm/fixes Renesas ARM Based SoC Fixes for v5.1 R-Car Gen3 E3 (r8a77990) and RZ/G2E (r8a774c0) SoCs: * Correct SCIF5 DMA channels * tag 'renesas-fixes-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: arm64: dts: renesas: r8a774c0: Fix SCIF5 DMA channels arm64: dts: renesas: r8a77990: Fix SCIF5 DMA channels
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commit
44cd905041
@ -2,7 +2,7 @@
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/*
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* Device Tree Source for the RZ/G2E (R8A774C0) SoC
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*
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* Copyright (C) 2018 Renesas Electronics Corp.
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* Copyright (C) 2018-2019 Renesas Electronics Corp.
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*/
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#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
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@ -1150,9 +1150,8 @@
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<&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
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<&dmac2 0x5b>, <&dmac2 0x5a>;
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dma-names = "tx", "rx", "tx", "rx";
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dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
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dma-names = "tx", "rx";
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power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
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resets = <&cpg 202>;
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status = "disabled";
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@ -2,7 +2,7 @@
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/*
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* Device Tree Source for the R-Car E3 (R8A77990) SoC
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*
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* Copyright (C) 2018 Renesas Electronics Corp.
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* Copyright (C) 2018-2019 Renesas Electronics Corp.
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*/
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#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
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@ -1067,9 +1067,8 @@
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<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
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<&dmac2 0x5b>, <&dmac2 0x5a>;
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dma-names = "tx", "rx", "tx", "rx";
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dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
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dma-names = "tx", "rx";
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power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
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resets = <&cpg 202>;
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status = "disabled";
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