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x86/boot/compressed/64: Introduce paging_prepare()

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Rename l5_paging_required() to paging_prepare() and change the
interface of the function.

This is a preparation for the next patch, which would make the function
also allocate memory for the 32-bit trampoline.

The function now returns a 128-bit structure. RAX would return
trampoline memory address (zero for now) and RDX would indicate if we
need to enable 5-level paging.

Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
[ Typo fixes and general clarification. ]
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@suse.de>
Cc: Cyrill Gorcunov <gorcunov@openvz.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Matthew Wilcox <willy@infradead.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mm@kvack.org
Link: http://lkml.kernel.org/r/20180209142228.21231-3-kirill.shutemov@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Kirill A. Shutemov 2018-02-09 17:22:26 +03:00 committed by Ingo Molnar
parent 7cc4eb1bdd
commit 4440977be1
2 changed files with 33 additions and 37 deletions
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45
arch/x86/boot/compressed/head_64.S
View File

@ -304,20 +304,6 @@ ENTRY(startup_64)
/* Set up the stack */
leaq boot_stack_end(%rbx), %rsp
#ifdef CONFIG_X86_5LEVEL
/*
* Check if we need to enable 5-level paging.
* RSI holds real mode data and need to be preserved across
* a function call.
*/
pushq %rsi
call l5_paging_required
popq %rsi
/* If l5_paging_required() returned zero, we're done here. */
cmpq $0, %rax
je lvl5
/*
* At this point we are in long mode with 4-level paging enabled,
* but we want to enable 5-level paging.
@ -325,13 +311,29 @@ ENTRY(startup_64)
* The problem is that we cannot do it directly. Setting LA57 in
* long mode would trigger #GP. So we need to switch off long mode
* first.
*
* NOTE: This is not going to work if bootloader put us above 4G
* limit.
*
* The first step is go into compatibility mode.
*/
/*
* paging_prepare() sets up the trampoline and checks if we need to
* enable 5-level paging.
*
* Address of the trampoline is returned in RAX.
* Non zero RDX on return means we need to enable 5-level paging.
*
* RSI holds real mode data and needs to be preserved across
* this function call.
*/
pushq %rsi
call paging_prepare
popq %rsi
/* Save the trampoline address in RCX */
movq %rax, %rcx
/* Check if we need to enable 5-level paging */
cmpq $0, %rdx
jz lvl5
/* Clear additional page table */
leaq lvl5_pgtable(%rbx), %rdi
xorq %rax, %rax
@ -352,7 +354,6 @@ ENTRY(startup_64)
pushq %rax
lretq
lvl5:
#endif
/* Zero EFLAGS */
pushq $0
@ -490,7 +491,6 @@ relocated:
jmp *%rax
.code32
#ifdef CONFIG_X86_5LEVEL
compatible_mode:
/* Setup data and stack segments */
movl $__KERNEL_DS, %eax
@ -526,7 +526,6 @@ compatible_mode:
movl %eax, %cr0
lret
#endif
no_longmode:
/* This isn't an x86-64 CPU so hang */
@ -585,7 +584,5 @@ boot_stack_end:
.balign 4096
pgtable:
.fill BOOT_PGT_SIZE, 1, 0
#ifdef CONFIG_X86_5LEVEL
lvl5_pgtable:
.fill PAGE_SIZE, 1, 0
#endif

25
arch/x86/boot/compressed/pgtable_64.c
View File

@ -9,20 +9,19 @@
*/
unsigned long __force_order;
int l5_paging_required(void)
struct paging_config {
unsigned long trampoline_start;
unsigned long l5_required;
};
struct paging_config paging_prepare(void)
{
/* Check if leaf 7 is supported. */
struct paging_config paging_config = {};
if (native_cpuid_eax(0) < 7)
return 0;
/* Check if LA57 is desired and supported */
if (IS_ENABLED(CONFIG_X86_5LEVEL) && native_cpuid_eax(0) >= 7 &&
(native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31))))
paging_config.l5_required = 1;
/* Check if la57 is supported. */
if (!(native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31))))
return 0;
/* Check if 5-level paging has already been enabled. */
if (native_read_cr4() & X86_CR4_LA57)
return 0;
return 1;
return paging_config;
}