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KVM: x86: Move FPU register accessors into fpu.h
Hyper-v XMM fast hypercalls use XMM registers to pass input/output parameters. To access these, hyperv.c can reuse some FPU register accessors defined in emulator.c. Move them to a common location so both can access them. While at it, reorder the parameters of these accessor methods to make them more readable. Cc: Alexander Graf <graf@amazon.com> Cc: Evgeny Iakovlev <eyakovl@amazon.de> Signed-off-by: Siddharth Chandrasekaran <sidcha@amazon.de> Message-Id: <01a85a6560714d4d3637d3d86e5eba65073318fa.1622019133.git.sidcha@amazon.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Siddharth Chandrasekaran
Paolo Bonzini
parent
a9d6496d66
commit
43e5146436
@ -22,7 +22,6 @@
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#include "kvm_cache_regs.h"
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#include "kvm_emulate.h"
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#include <linux/stringify.h>
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#include <asm/fpu/api.h>
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#include <asm/debugreg.h>
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#include <asm/nospec-branch.h>
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@ -1081,116 +1080,14 @@ static void fetch_register_operand(struct operand *op)
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}
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}
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static void emulator_get_fpu(void)
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{
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fpregs_lock();
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fpregs_assert_state_consistent();
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if (test_thread_flag(TIF_NEED_FPU_LOAD))
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switch_fpu_return();
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}
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static void emulator_put_fpu(void)
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{
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fpregs_unlock();
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}
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static void read_sse_reg(sse128_t *data, int reg)
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{
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emulator_get_fpu();
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switch (reg) {
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case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
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case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
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case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
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case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
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case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
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case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
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case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
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case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
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#ifdef CONFIG_X86_64
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case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
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case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
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case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
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case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
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case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
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case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
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case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
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case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
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#endif
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default: BUG();
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}
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emulator_put_fpu();
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}
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static void write_sse_reg(sse128_t *data, int reg)
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{
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emulator_get_fpu();
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switch (reg) {
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case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
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case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
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case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
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case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
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case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
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case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
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case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
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case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
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#ifdef CONFIG_X86_64
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case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
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case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
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case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
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case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
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case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
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case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
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case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
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case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
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#endif
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default: BUG();
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}
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emulator_put_fpu();
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}
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static void read_mmx_reg(u64 *data, int reg)
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{
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emulator_get_fpu();
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switch (reg) {
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case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
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case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
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case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
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case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
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case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
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case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
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case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
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case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
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default: BUG();
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}
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emulator_put_fpu();
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}
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static void write_mmx_reg(u64 *data, int reg)
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{
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emulator_get_fpu();
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switch (reg) {
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case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
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case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
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case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
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case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
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case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
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case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
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case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
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case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
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default: BUG();
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}
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emulator_put_fpu();
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}
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static int em_fninit(struct x86_emulate_ctxt *ctxt)
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{
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if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
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return emulate_nm(ctxt);
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emulator_get_fpu();
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kvm_fpu_get();
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asm volatile("fninit");
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emulator_put_fpu();
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kvm_fpu_put();
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return X86EMUL_CONTINUE;
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}
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@ -1201,9 +1098,9 @@ static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
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if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
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return emulate_nm(ctxt);
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emulator_get_fpu();
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kvm_fpu_get();
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asm volatile("fnstcw %0": "+m"(fcw));
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emulator_put_fpu();
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kvm_fpu_put();
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ctxt->dst.val = fcw;
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@ -1217,9 +1114,9 @@ static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
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if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
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return emulate_nm(ctxt);
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emulator_get_fpu();
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kvm_fpu_get();
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asm volatile("fnstsw %0": "+m"(fsw));
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emulator_put_fpu();
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kvm_fpu_put();
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ctxt->dst.val = fsw;
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@ -1238,7 +1135,7 @@ static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
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op->type = OP_XMM;
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op->bytes = 16;
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op->addr.xmm = reg;
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read_sse_reg(&op->vec_val, reg);
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kvm_read_sse_reg(reg, &op->vec_val);
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return;
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}
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if (ctxt->d & Mmx) {
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@ -1289,7 +1186,7 @@ static int decode_modrm(struct x86_emulate_ctxt *ctxt,
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op->type = OP_XMM;
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op->bytes = 16;
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op->addr.xmm = ctxt->modrm_rm;
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read_sse_reg(&op->vec_val, ctxt->modrm_rm);
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kvm_read_sse_reg(ctxt->modrm_rm, &op->vec_val);
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return rc;
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}
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if (ctxt->d & Mmx) {
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@ -1866,10 +1763,10 @@ static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
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op->bytes * op->count);
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break;
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case OP_XMM:
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write_sse_reg(&op->vec_val, op->addr.xmm);
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kvm_write_sse_reg(op->addr.xmm, &op->vec_val);
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break;
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case OP_MM:
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write_mmx_reg(&op->mm_val, op->addr.mm);
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kvm_write_mmx_reg(op->addr.mm, &op->mm_val);
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break;
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case OP_NONE:
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/* no writeback */
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@ -4124,11 +4021,11 @@ static int em_fxsave(struct x86_emulate_ctxt *ctxt)
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if (rc != X86EMUL_CONTINUE)
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return rc;
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emulator_get_fpu();
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kvm_fpu_get();
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rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state));
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emulator_put_fpu();
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kvm_fpu_put();
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if (rc != X86EMUL_CONTINUE)
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return rc;
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@ -4172,7 +4069,7 @@ static int em_fxrstor(struct x86_emulate_ctxt *ctxt)
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if (rc != X86EMUL_CONTINUE)
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return rc;
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emulator_get_fpu();
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kvm_fpu_get();
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if (size < __fxstate_size(16)) {
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rc = fxregs_fixup(&fx_state, size);
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@ -4189,7 +4086,7 @@ static int em_fxrstor(struct x86_emulate_ctxt *ctxt)
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rc = asm_safe("fxrstor %[fx]", : [fx] "m"(fx_state));
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out:
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emulator_put_fpu();
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kvm_fpu_put();
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return rc;
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}
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@ -5437,9 +5334,9 @@ static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
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{
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int rc;
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emulator_get_fpu();
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kvm_fpu_get();
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rc = asm_safe("fwait");
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emulator_put_fpu();
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kvm_fpu_put();
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if (unlikely(rc != X86EMUL_CONTINUE))
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return emulate_exception(ctxt, MF_VECTOR, 0, false);
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@ -5450,7 +5347,7 @@ static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
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static void fetch_possible_mmx_operand(struct operand *op)
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{
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if (op->type == OP_MM)
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read_mmx_reg(&op->mm_val, op->addr.mm);
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kvm_read_mmx_reg(op->addr.mm, &op->mm_val);
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}
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static int fastop(struct x86_emulate_ctxt *ctxt, fastop_t fop)
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140
arch/x86/kvm/fpu.h
Normal file
140
arch/x86/kvm/fpu.h
Normal file
@ -0,0 +1,140 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __KVM_FPU_H_
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#define __KVM_FPU_H_
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#include <asm/fpu/api.h>
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typedef u32 __attribute__((vector_size(16))) sse128_t;
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#define __sse128_u union { sse128_t vec; u64 as_u64[2]; u32 as_u32[4]; }
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#define sse128_lo(x) ({ __sse128_u t; t.vec = x; t.as_u64[0]; })
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#define sse128_hi(x) ({ __sse128_u t; t.vec = x; t.as_u64[1]; })
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#define sse128_l0(x) ({ __sse128_u t; t.vec = x; t.as_u32[0]; })
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#define sse128_l1(x) ({ __sse128_u t; t.vec = x; t.as_u32[1]; })
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#define sse128_l2(x) ({ __sse128_u t; t.vec = x; t.as_u32[2]; })
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#define sse128_l3(x) ({ __sse128_u t; t.vec = x; t.as_u32[3]; })
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#define sse128(lo, hi) ({ __sse128_u t; t.as_u64[0] = lo; t.as_u64[1] = hi; t.vec; })
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static inline void _kvm_read_sse_reg(int reg, sse128_t *data)
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{
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switch (reg) {
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case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
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case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
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case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
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case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
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case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
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case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
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case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
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case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
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#ifdef CONFIG_X86_64
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case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
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case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
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case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
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case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
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case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
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case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
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case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
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case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
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#endif
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default: BUG();
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}
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}
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static inline void _kvm_write_sse_reg(int reg, const sse128_t *data)
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{
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switch (reg) {
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case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
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case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
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case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
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case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
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case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
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case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
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case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
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case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
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#ifdef CONFIG_X86_64
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case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
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case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
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case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
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case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
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case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
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case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
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case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
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case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
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#endif
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default: BUG();
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}
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}
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static inline void _kvm_read_mmx_reg(int reg, u64 *data)
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{
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switch (reg) {
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case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
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case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
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case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
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case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
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case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
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case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
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case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
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case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
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default: BUG();
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}
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}
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static inline void _kvm_write_mmx_reg(int reg, const u64 *data)
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{
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switch (reg) {
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case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
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case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
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case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
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case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
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case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
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case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
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case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
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case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
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default: BUG();
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}
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}
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static inline void kvm_fpu_get(void)
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{
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fpregs_lock();
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fpregs_assert_state_consistent();
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if (test_thread_flag(TIF_NEED_FPU_LOAD))
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switch_fpu_return();
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}
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static inline void kvm_fpu_put(void)
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{
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fpregs_unlock();
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}
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static inline void kvm_read_sse_reg(int reg, sse128_t *data)
|
||||
{
|
||||
kvm_fpu_get();
|
||||
_kvm_read_sse_reg(reg, data);
|
||||
kvm_fpu_put();
|
||||
}
|
||||
|
||||
static inline void kvm_write_sse_reg(int reg, const sse128_t *data)
|
||||
{
|
||||
kvm_fpu_get();
|
||||
_kvm_write_sse_reg(reg, data);
|
||||
kvm_fpu_put();
|
||||
}
|
||||
|
||||
static inline void kvm_read_mmx_reg(int reg, u64 *data)
|
||||
{
|
||||
kvm_fpu_get();
|
||||
_kvm_read_mmx_reg(reg, data);
|
||||
kvm_fpu_put();
|
||||
}
|
||||
|
||||
static inline void kvm_write_mmx_reg(int reg, const u64 *data)
|
||||
{
|
||||
kvm_fpu_get();
|
||||
_kvm_write_mmx_reg(reg, data);
|
||||
kvm_fpu_put();
|
||||
}
|
||||
|
||||
#endif
|
||||
@ -13,6 +13,7 @@
|
||||
#define _ASM_X86_KVM_X86_EMULATE_H
|
||||
|
||||
#include <asm/desc_defs.h>
|
||||
#include "fpu.h"
|
||||
|
||||
struct x86_emulate_ctxt;
|
||||
enum x86_intercept;
|
||||
@ -236,8 +237,6 @@ struct x86_emulate_ops {
|
||||
int (*set_xcr)(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr);
|
||||
};
|
||||
|
||||
typedef u32 __attribute__((vector_size(16))) sse128_t;
|
||||
|
||||
/* Type, address-of, and value of an instruction's operand. */
|
||||
struct operand {
|
||||
enum { OP_REG, OP_MEM, OP_MEM_STR, OP_IMM, OP_XMM, OP_MM, OP_NONE } type;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user