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rtw88: 8723d: Add chip_ops::false_alarm_statistics
This ops is used to do statistics of false alarm periodically, and then fine tune RX initial gain to adaptive different circumstance. There are three steps, hold/get/reset counter, to retrieve false alarm counters that consist of CCK and OFDM. In addition to false alarm counters, it also collects CRC ok/error counters of CCK, OFDM and HT. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200504105010.10780-7-yhchuang@realtek.com
This commit is contained in:
Ping-Ke Shih
Kalle Valo
parent
3ac1443915
commit
439d4a978d
@ -539,6 +539,70 @@ static void rtw8723d_efuse_grant(struct rtw_dev *rtwdev, bool on)
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}
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}
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static void rtw8723d_false_alarm_statistics(struct rtw_dev *rtwdev)
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{
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struct rtw_dm_info *dm_info = &rtwdev->dm_info;
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u32 cck_fa_cnt;
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u32 ofdm_fa_cnt;
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u32 crc32_cnt;
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u32 val32;
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/* hold counter */
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rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 1);
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rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 1);
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rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KEEP, 1);
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rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KEEP, 1);
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cck_fa_cnt = rtw_read32_mask(rtwdev, REG_CCK_FA_LSB_11N, MASKBYTE0);
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cck_fa_cnt += rtw_read32_mask(rtwdev, REG_CCK_FA_MSB_11N, MASKBYTE3) << 8;
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val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE1_11N);
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ofdm_fa_cnt = u32_get_bits(val32, BIT_MASK_OFDM_FF_CNT);
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ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_SF_CNT);
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val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE2_11N);
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dm_info->ofdm_cca_cnt = u32_get_bits(val32, BIT_MASK_OFDM_CCA_CNT);
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ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_PF_CNT);
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val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE3_11N);
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ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_RI_CNT);
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ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_CRC_CNT);
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val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE4_11N);
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ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_MNS_CNT);
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dm_info->cck_fa_cnt = cck_fa_cnt;
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dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
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dm_info->total_fa_cnt = cck_fa_cnt + ofdm_fa_cnt;
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dm_info->cck_err_cnt = rtw_read32(rtwdev, REG_IGI_C_11N);
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dm_info->cck_ok_cnt = rtw_read32(rtwdev, REG_IGI_D_11N);
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crc32_cnt = rtw_read32(rtwdev, REG_OFDM_CRC32_CNT_11N);
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dm_info->ofdm_err_cnt = u32_get_bits(crc32_cnt, BIT_MASK_OFDM_LCRC_ERR);
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dm_info->ofdm_ok_cnt = u32_get_bits(crc32_cnt, BIT_MASK_OFDM_LCRC_OK);
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crc32_cnt = rtw_read32(rtwdev, REG_HT_CRC32_CNT_11N);
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dm_info->ht_err_cnt = u32_get_bits(crc32_cnt, BIT_MASK_HT_CRC_ERR);
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dm_info->ht_ok_cnt = u32_get_bits(crc32_cnt, BIT_MASK_HT_CRC_OK);
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dm_info->vht_err_cnt = 0;
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dm_info->vht_ok_cnt = 0;
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val32 = rtw_read32(rtwdev, REG_CCK_CCA_CNT_11N);
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dm_info->cck_cca_cnt = (u32_get_bits(val32, BIT_MASK_CCK_FA_MSB) << 8) |
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u32_get_bits(val32, BIT_MASK_CCK_FA_LSB);
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dm_info->total_cca_cnt = dm_info->cck_cca_cnt + dm_info->ofdm_cca_cnt;
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/* reset counter */
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rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 1);
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rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 0);
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rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 1);
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rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 0);
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rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 0);
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rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 0);
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rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 0);
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rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 2);
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rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 0);
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rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 2);
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rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 1);
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rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 0);
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}
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static struct rtw_chip_ops rtw8723d_ops = {
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.phy_set_param = rtw8723d_phy_set_param,
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.read_efuse = rtw8723d_read_efuse,
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@ -551,6 +615,7 @@ static struct rtw_chip_ops rtw8723d_ops = {
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.set_antenna = NULL,
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.cfg_ldo25 = rtw8723d_cfg_ldo25,
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.efuse_grant = rtw8723d_efuse_grant,
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.false_alarm_statistics = rtw8723d_false_alarm_statistics,
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.config_bfee = NULL,
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.set_gid_table = NULL,
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.cfg_csi_rate = NULL,
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@ -88,16 +88,57 @@ struct rtw8723d_efuse {
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#define BIT_RXBB_DFIR_EN BIT(19)
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#define REG_CCK0_SYS 0x0a00
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#define BIT_CCK_SIDE_BAND BIT(4)
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#define REG_CCK_FA_RST_11N 0x0a2c
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#define BIT_MASK_CCK_CNT_KEEP BIT(12)
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#define BIT_MASK_CCK_CNT_EN BIT(13)
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#define BIT_MASK_CCK_CNT_KPEN (BIT_MASK_CCK_CNT_KEEP | BIT_MASK_CCK_CNT_EN)
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#define BIT_MASK_CCK_FA_KEEP BIT(14)
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#define BIT_MASK_CCK_FA_EN BIT(15)
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#define BIT_MASK_CCK_FA_KPEN (BIT_MASK_CCK_FA_KEEP | BIT_MASK_CCK_FA_EN)
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#define REG_CCK_FA_LSB_11N 0x0a5c
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#define REG_CCK_FA_MSB_11N 0x0a58
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#define REG_CCK_CCA_CNT_11N 0x0a60
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#define BIT_MASK_CCK_FA_MSB GENMASK(7, 0)
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#define BIT_MASK_CCK_FA_LSB GENMASK(15, 8)
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#define REG_OFDM_FA_HOLDC_11N 0x0c00
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#define BIT_MASK_OFDM_FA_KEEP BIT(31)
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#define REG_OFDM_FA_RSTC_11N 0x0c0c
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#define BIT_MASK_OFDM_FA_RST BIT(31)
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#define REG_OFDM0_RXDSP 0x0c40
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#define BIT_MASK_RXDSP GENMASK(28, 24)
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#define BIT_EN_RXDSP BIT(9)
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#define REG_OFDM0_XAAGC1 0x0c50
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#define REG_OFDM0_XBAGC1 0x0c58
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#define REG_OFDM_FA_TYPE1_11N 0x0cf0
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#define BIT_MASK_OFDM_FF_CNT GENMASK(15, 0)
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#define BIT_MASK_OFDM_SF_CNT GENMASK(31, 16)
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#define REG_OFDM_FA_RSTD_11N 0x0d00
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#define BIT_MASK_OFDM_FA_RST1 BIT(27)
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#define BIT_MASK_OFDM_FA_KEEP1 BIT(31)
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#define REG_OFDM1_CFOTRK 0x0d2c
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#define BIT_EN_CFOTRK BIT(28)
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#define REG_OFDM1_CSI1 0x0d40
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#define REG_OFDM1_CSI2 0x0d44
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#define REG_OFDM1_CSI3 0x0d48
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#define REG_OFDM1_CSI4 0x0d4c
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#define REG_OFDM_FA_TYPE2_11N 0x0da0
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#define BIT_MASK_OFDM_CCA_CNT GENMASK(15, 0)
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#define BIT_MASK_OFDM_PF_CNT GENMASK(31, 16)
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#define REG_OFDM_FA_TYPE3_11N 0x0da4
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#define BIT_MASK_OFDM_RI_CNT GENMASK(15, 0)
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#define BIT_MASK_OFDM_CRC_CNT GENMASK(31, 16)
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#define REG_OFDM_FA_TYPE4_11N 0x0da8
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#define BIT_MASK_OFDM_MNS_CNT GENMASK(15, 0)
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#define REG_PAGE_F_RST_11N 0x0f14
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#define BIT_MASK_F_RST_ALL BIT(16)
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#define REG_IGI_C_11N 0x0f84
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#define REG_IGI_D_11N 0x0f88
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#define REG_HT_CRC32_CNT_11N 0x0f90
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#define BIT_MASK_HT_CRC_OK GENMASK(15, 0)
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#define BIT_MASK_HT_CRC_ERR GENMASK(31, 16)
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#define REG_OFDM_CRC32_CNT_11N 0x0f94
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#define BIT_MASK_OFDM_LCRC_OK GENMASK(15, 0)
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#define BIT_MASK_OFDM_LCRC_ERR GENMASK(31, 16)
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#define REG_HT_CRC32_CNT_11N_AGG 0x0fb8
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#endif
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