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media: rcar-vin: enable Gen3 hardware configuration
Add the register needed to work with Gen3 hardware. This patch adds the logic for how to work with the Gen3 hardware. More work is required to enable the subdevice structure needed to configure capturing. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
This commit is contained in:
Niklas Söderlund
Mauro Carvalho Chehab
parent
c65c99b401
commit
4394eb24a8
@ -33,21 +33,23 @@
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#define VNELPRC_REG 0x10 /* Video n End Line Pre-Clip Register */
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#define VNSPPRC_REG 0x14 /* Video n Start Pixel Pre-Clip Register */
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#define VNEPPRC_REG 0x18 /* Video n End Pixel Pre-Clip Register */
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#define VNSLPOC_REG 0x1C /* Video n Start Line Post-Clip Register */
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#define VNELPOC_REG 0x20 /* Video n End Line Post-Clip Register */
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#define VNSPPOC_REG 0x24 /* Video n Start Pixel Post-Clip Register */
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#define VNEPPOC_REG 0x28 /* Video n End Pixel Post-Clip Register */
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#define VNIS_REG 0x2C /* Video n Image Stride Register */
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#define VNMB_REG(m) (0x30 + ((m) << 2)) /* Video n Memory Base m Register */
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#define VNIE_REG 0x40 /* Video n Interrupt Enable Register */
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#define VNINTS_REG 0x44 /* Video n Interrupt Status Register */
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#define VNSI_REG 0x48 /* Video n Scanline Interrupt Register */
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#define VNMTC_REG 0x4C /* Video n Memory Transfer Control Register */
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#define VNYS_REG 0x50 /* Video n Y Scale Register */
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#define VNXS_REG 0x54 /* Video n X Scale Register */
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#define VNDMR_REG 0x58 /* Video n Data Mode Register */
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#define VNDMR2_REG 0x5C /* Video n Data Mode Register 2 */
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#define VNUVAOF_REG 0x60 /* Video n UV Address Offset Register */
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/* Register offsets specific for Gen2 */
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#define VNSLPOC_REG 0x1C /* Video n Start Line Post-Clip Register */
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#define VNELPOC_REG 0x20 /* Video n End Line Post-Clip Register */
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#define VNSPPOC_REG 0x24 /* Video n Start Pixel Post-Clip Register */
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#define VNEPPOC_REG 0x28 /* Video n End Pixel Post-Clip Register */
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#define VNYS_REG 0x50 /* Video n Y Scale Register */
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#define VNXS_REG 0x54 /* Video n X Scale Register */
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#define VNC1A_REG 0x80 /* Video n Coefficient Set C1A Register */
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#define VNC1B_REG 0x84 /* Video n Coefficient Set C1B Register */
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#define VNC1C_REG 0x88 /* Video n Coefficient Set C1C Register */
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@ -73,9 +75,13 @@
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#define VNC8B_REG 0xF4 /* Video n Coefficient Set C8B Register */
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#define VNC8C_REG 0xF8 /* Video n Coefficient Set C8C Register */
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/* Register offsets specific for Gen3 */
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#define VNCSI_IFMD_REG 0x20 /* Video n CSI2 Interface Mode Register */
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/* Register bit fields for R-Car VIN */
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/* Video n Main Control Register bits */
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#define VNMC_DPINE (1 << 27) /* Gen3 specific */
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#define VNMC_SCLE (1 << 26) /* Gen3 specific */
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#define VNMC_FOC (1 << 21)
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#define VNMC_YCAL (1 << 19)
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#define VNMC_INF_YUV8_BT656 (0 << 16)
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@ -119,6 +125,12 @@
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#define VNDMR2_FTEV (1 << 17)
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#define VNDMR2_VLV(n) ((n & 0xf) << 12)
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/* Video n CSI2 Interface Mode Register (Gen3) */
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#define VNCSI_IFMD_DES1 (1 << 26)
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#define VNCSI_IFMD_DES0 (1 << 25)
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#define VNCSI_IFMD_CSI_CHSEL(n) (((n) & 0xf) << 0)
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#define VNCSI_IFMD_CSI_CHSEL_MASK 0xf
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struct rvin_buffer {
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struct vb2_v4l2_buffer vb;
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struct list_head list;
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@ -514,28 +526,10 @@ static void rvin_set_coeff(struct rvin_dev *vin, unsigned short xs)
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rvin_write(vin, p_set->coeff_set[23], VNC8C_REG);
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}
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void rvin_crop_scale_comp(struct rvin_dev *vin)
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static void rvin_crop_scale_comp_gen2(struct rvin_dev *vin)
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{
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u32 xs, ys;
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/* Set Start/End Pixel/Line Pre-Clip */
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rvin_write(vin, vin->crop.left, VNSPPRC_REG);
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rvin_write(vin, vin->crop.left + vin->crop.width - 1, VNEPPRC_REG);
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switch (vin->format.field) {
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case V4L2_FIELD_INTERLACED:
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case V4L2_FIELD_INTERLACED_TB:
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case V4L2_FIELD_INTERLACED_BT:
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rvin_write(vin, vin->crop.top / 2, VNSLPRC_REG);
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rvin_write(vin, (vin->crop.top + vin->crop.height) / 2 - 1,
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VNELPRC_REG);
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break;
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default:
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rvin_write(vin, vin->crop.top, VNSLPRC_REG);
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rvin_write(vin, vin->crop.top + vin->crop.height - 1,
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VNELPRC_REG);
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break;
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}
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/* Set scaling coefficient */
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ys = 0;
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if (vin->crop.height != vin->compose.height)
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@ -573,11 +567,6 @@ void rvin_crop_scale_comp(struct rvin_dev *vin)
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break;
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}
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if (vin->format.pixelformat == V4L2_PIX_FMT_NV16)
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rvin_write(vin, ALIGN(vin->format.width, 0x20), VNIS_REG);
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else
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rvin_write(vin, ALIGN(vin->format.width, 0x10), VNIS_REG);
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vin_dbg(vin,
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"Pre-Clip: %ux%u@%u:%u YS: %d XS: %d Post-Clip: %ux%u@%u:%u\n",
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vin->crop.width, vin->crop.height, vin->crop.left,
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@ -585,6 +574,37 @@ void rvin_crop_scale_comp(struct rvin_dev *vin)
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0, 0);
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}
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void rvin_crop_scale_comp(struct rvin_dev *vin)
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{
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/* Set Start/End Pixel/Line Pre-Clip */
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rvin_write(vin, vin->crop.left, VNSPPRC_REG);
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rvin_write(vin, vin->crop.left + vin->crop.width - 1, VNEPPRC_REG);
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switch (vin->format.field) {
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case V4L2_FIELD_INTERLACED:
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case V4L2_FIELD_INTERLACED_TB:
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case V4L2_FIELD_INTERLACED_BT:
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rvin_write(vin, vin->crop.top / 2, VNSLPRC_REG);
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rvin_write(vin, (vin->crop.top + vin->crop.height) / 2 - 1,
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VNELPRC_REG);
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break;
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default:
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rvin_write(vin, vin->crop.top, VNSLPRC_REG);
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rvin_write(vin, vin->crop.top + vin->crop.height - 1,
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VNELPRC_REG);
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break;
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}
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/* TODO: Add support for the UDS scaler. */
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if (vin->info->model != RCAR_GEN3)
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rvin_crop_scale_comp_gen2(vin);
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if (vin->format.pixelformat == V4L2_PIX_FMT_NV16)
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rvin_write(vin, ALIGN(vin->format.width, 0x20), VNIS_REG);
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else
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rvin_write(vin, ALIGN(vin->format.width, 0x10), VNIS_REG);
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}
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/* -----------------------------------------------------------------------------
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* Hardware setup
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*/
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@ -652,7 +672,10 @@ static int rvin_setup(struct rvin_dev *vin)
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}
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/* Enable VSYNC Field Toogle mode after one VSYNC input */
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dmr2 = VNDMR2_FTEV | VNDMR2_VLV(1);
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if (vin->info->model == RCAR_GEN3)
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dmr2 = VNDMR2_FTEV;
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else
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dmr2 = VNDMR2_FTEV | VNDMR2_VLV(1);
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/* Hsync Signal Polarity Select */
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if (!(vin->mbus_cfg.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW))
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@ -704,6 +727,14 @@ static int rvin_setup(struct rvin_dev *vin)
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if (input_is_yuv == output_is_yuv)
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vnmc |= VNMC_BPS;
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if (vin->info->model == RCAR_GEN3) {
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/* Select between CSI-2 and Digital input */
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if (vin->mbus_cfg.type == V4L2_MBUS_CSI2)
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vnmc &= ~VNMC_DPINE;
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else
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vnmc |= VNMC_DPINE;
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}
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/* Progressive or interlaced mode */
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interrupts = progressive ? VNIE_FIE : VNIE_EFE;
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@ -33,6 +33,7 @@ enum model_id {
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RCAR_H1,
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RCAR_M1,
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RCAR_GEN2,
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RCAR_GEN3,
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};
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/**
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